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Searched refs:reset_mask (Results 1 – 25 of 28) sorted by relevance

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/linux-6.3-rc2/drivers/clk/sunxi/
A Dclk-usb.c84 u32 reset_mask; member
141 if (data->reset_mask == 0) in sunxi_usb_clk_setup()
159 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; in sunxi_usb_clk_setup()
167 .reset_mask = BIT(2) | BIT(1) | BIT(0),
180 .reset_mask = BIT(1) | BIT(0),
191 .reset_mask = BIT(2) | BIT(1) | BIT(0),
202 .reset_mask = BIT(2) | BIT(1) | BIT(0),
214 .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
225 .reset_mask = BIT(19) | BIT(18) | BIT(17),
239 .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dni.c1735 u32 reset_mask = 0; in cayman_gpu_check_soft_reset() local
1746 reset_mask |= RADEON_RESET_GFX; in cayman_gpu_check_soft_reset()
1750 reset_mask |= RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1758 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1779 reset_mask |= RADEON_RESET_IH; in cayman_gpu_check_soft_reset()
1792 reset_mask |= RADEON_RESET_MC; in cayman_gpu_check_soft_reset()
1808 return reset_mask; in cayman_gpu_check_soft_reset()
1817 if (reset_mask == 0) in cayman_gpu_soft_reset()
1945 u32 reset_mask; in cayman_asic_reset() local
1954 if (reset_mask) in cayman_asic_reset()
[all …]
A Dr600.c1617 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local
1640 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1648 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()
1653 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()
1656 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()
1670 reset_mask |= RADEON_RESET_MC; in r600_gpu_check_soft_reset()
1681 return reset_mask; in r600_gpu_check_soft_reset()
1690 if (reset_mask == 0) in r600_gpu_soft_reset()
1883 u32 reset_mask; in r600_asic_reset() local
1892 if (reset_mask) in r600_asic_reset()
[all …]
A Devergreen.c3830 u32 reset_mask = 0; in evergreen_gpu_check_soft_reset() local
3840 reset_mask |= RADEON_RESET_GFX; in evergreen_gpu_check_soft_reset()
3844 reset_mask |= RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()
3852 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()
3865 reset_mask |= RADEON_RESET_IH; in evergreen_gpu_check_soft_reset()
3878 reset_mask |= RADEON_RESET_MC; in evergreen_gpu_check_soft_reset()
3894 return reset_mask; in evergreen_gpu_check_soft_reset()
3903 if (reset_mask == 0) in evergreen_gpu_soft_reset()
4055 u32 reset_mask; in evergreen_asic_reset() local
4064 if (reset_mask) in evergreen_asic_reset()
[all …]
A Dsi.c3771 u32 reset_mask = 0; in si_gpu_check_soft_reset() local
3782 reset_mask |= RADEON_RESET_GFX; in si_gpu_check_soft_reset()
3786 reset_mask |= RADEON_RESET_CP; in si_gpu_check_soft_reset()
3794 reset_mask |= RADEON_RESET_RLC; in si_gpu_check_soft_reset()
3818 reset_mask |= RADEON_RESET_IH; in si_gpu_check_soft_reset()
3831 reset_mask |= RADEON_RESET_MC; in si_gpu_check_soft_reset()
3847 return reset_mask; in si_gpu_check_soft_reset()
3856 if (reset_mask == 0) in si_gpu_soft_reset()
4084 u32 reset_mask; in si_asic_reset() local
4093 if (reset_mask) in si_asic_reset()
[all …]
A Devergreen_dma.c172 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_dma_is_lockup() local
174 if (!(reset_mask & RADEON_RESET_DMA)) { in evergreen_dma_is_lockup()
A Dcik.c4844 u32 reset_mask = 0; in cik_gpu_check_soft_reset() local
4855 reset_mask |= RADEON_RESET_GFX; in cik_gpu_check_soft_reset()
4858 reset_mask |= RADEON_RESET_CP; in cik_gpu_check_soft_reset()
4863 reset_mask |= RADEON_RESET_RLC; in cik_gpu_check_soft_reset()
4887 reset_mask |= RADEON_RESET_IH; in cik_gpu_check_soft_reset()
4900 reset_mask |= RADEON_RESET_MC; in cik_gpu_check_soft_reset()
4911 return reset_mask; in cik_gpu_check_soft_reset()
4928 if (reset_mask == 0) in cik_gpu_soft_reset()
5211 u32 reset_mask; in cik_asic_reset() local
5220 if (reset_mask) in cik_asic_reset()
[all …]
A Dsi_dma.c42 u32 reset_mask = si_gpu_check_soft_reset(rdev); in si_dma_is_lockup() local
50 if (!(reset_mask & mask)) { in si_dma_is_lockup()
A Dni_dma.c288 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_dma_is_lockup() local
296 if (!(reset_mask & mask)) { in cayman_dma_is_lockup()
A Dr600_dma.c209 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_dma_is_lockup() local
211 if (!(reset_mask & RADEON_RESET_DMA)) { in r600_dma_is_lockup()
A Dcik_sdma.c776 u32 reset_mask = cik_gpu_check_soft_reset(rdev); in cik_sdma_is_lockup() local
784 if (!(reset_mask & mask)) { in cik_sdma_is_lockup()
/linux-6.3-rc2/drivers/reset/
A Dreset-ti-sci.c25 u32 reset_mask; member
83 reset_state |= control->reset_mask; in ti_sci_reset_set()
85 reset_state &= ~control->reset_mask; in ti_sci_reset_set()
161 return reset_state & control->reset_mask; in ti_sci_reset_status()
198 control->reset_mask = reset_spec->args[1]; in ti_sci_reset_of_xlate()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_gt_pm_irq.c62 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) in gen6_gt_pm_reset_iir() argument
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
A Dintel_gt_pm_irq.h19 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);
A Dintel_reset.c406 u32 *reset_mask, in gen11_lock_sfc() argument
493 *reset_mask |= sfc_lock.reset_bit; in gen11_lock_sfc()
522 u32 reset_mask, unlock_mask = 0; in __gen11_reset_engines() local
526 reset_mask = GEN11_GRDOM_FULL; in __gen11_reset_engines()
528 reset_mask = 0; in __gen11_reset_engines()
530 reset_mask |= engine->reset_domain; in __gen11_reset_engines()
531 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask); in __gen11_reset_engines()
537 ret = gen6_hw_domain_reset(gt, reset_mask); in __gen11_reset_engines()
/linux-6.3-rc2/drivers/clk/
A Dclk-twl6040.c33 const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */ in twl6040_pdmclk_reset_one_clock() local
36 ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
40 ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
/linux-6.3-rc2/drivers/net/ethernet/ibm/
A Dibmveth.h73 unsigned long reset_mask, unsigned long set_mask, in h_illan_attributes() argument
80 reset_mask, set_mask); in h_illan_attributes()
/linux-6.3-rc2/drivers/misc/cxl/
A Dhcalls.c439 u64 control_mask, u64 reset_mask) in cxl_h_control_faults() argument
448 control_mask, reset_mask); in cxl_h_control_faults()
450 unit_address, process_token, control_mask, reset_mask, in cxl_h_control_faults()
453 control_mask, reset_mask, retbuf[0], rc); in cxl_h_control_faults()
A Dtrace.h610 u64 control_mask, u64 reset_mask, unsigned long r4,
614 control_mask, reset_mask, r4, rc),
620 __field(u64, reset_mask)
629 __entry->reset_mask = reset_mask;
639 __entry->reset_mask,
A Dhcalls.h168 u64 control_mask, u64 reset_mask);
/linux-6.3-rc2/sound/soc/tegra/
A Dtegra210_i2s.c90 unsigned int reset_mask = I2S_SOFT_RESET_MASK; in tegra210_i2s_sw_reset() local
112 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); in tegra210_i2s_sw_reset()
115 !(val & reset_mask & reset_en), in tegra210_i2s_sw_reset()
/linux-6.3-rc2/drivers/crypto/qat/qat_common/
A Dqat_hal.c304 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_reset() local
309 csr_val |= reset_mask; in qat_hal_reset()
476 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_clr_reset() local
485 csr_val &= ~reset_mask; in qat_hal_clr_reset()
491 csr_val &= reset_mask; in qat_hal_clr_reset()
495 csr_val |= reset_mask; in qat_hal_clr_reset()
/linux-6.3-rc2/drivers/net/ethernet/smsc/
A Dsmsc911x.c1446 unsigned int reset_mask = HW_CFG_SRST_; in smsc911x_soft_reset() local
1476 reset_mask = RESET_CTL_DIGITAL_RST_; in smsc911x_soft_reset()
1480 smsc911x_reg_write(pdata, reset_offset, reset_mask); in smsc911x_soft_reset()
1487 } while ((--timeout) && (temp & reset_mask)); in smsc911x_soft_reset()
1489 if (unlikely(temp & reset_mask)) { in smsc911x_soft_reset()
/linux-6.3-rc2/drivers/net/wireless/ath/ath10k/
A Dhw.h297 u32 reset_mask; member
A Dhw.c370 .reset_mask = 0xffffffff,

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