Searched refs:rlc_hdr (Results 1 – 8 of 8) sorted by relevance
352 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in amdgpu_gfx_rlc_init_microcode_v2_1()356 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()360 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()398 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()400 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()430 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()435 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()465 …adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()467 …adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()469 …adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()[all …]
151 const struct rlc_firmware_header_v1_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local155 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()157 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()161 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in amdgpu_ucode_print_rlc_hdr()165 const struct rlc_firmware_header_v2_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local180 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()184 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()190 le32_to_cpu(rlc_hdr->reg_restore_list_size)); in amdgpu_ucode_print_rlc_hdr()192 le32_to_cpu(rlc_hdr->reg_list_format_start)); in amdgpu_ucode_print_rlc_hdr()196 le32_to_cpu(rlc_hdr->starting_offsets_start)); in amdgpu_ucode_print_rlc_hdr()[all …]
947 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v8_0_init_microcode() local1056 le32_to_cpu(rlc_hdr->save_and_restore_offset); in gfx_v8_0_init_microcode()1060 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); in gfx_v8_0_init_microcode()1062 le32_to_cpu(rlc_hdr->reg_restore_list_size); in gfx_v8_0_init_microcode()1064 le32_to_cpu(rlc_hdr->reg_list_format_start); in gfx_v8_0_init_microcode()1068 le32_to_cpu(rlc_hdr->starting_offsets_start); in gfx_v8_0_init_microcode()1070 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); in gfx_v8_0_init_microcode()1072 le32_to_cpu(rlc_hdr->reg_list_size_bytes); in gfx_v8_0_init_microcode()1083 tmp = (unsigned int *)((uintptr_t)rlc_hdr + in gfx_v8_0_init_microcode()1090 tmp = (unsigned int *)((uintptr_t)rlc_hdr + in gfx_v8_0_init_microcode()[all …]
471 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_init_microcode() local513 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()514 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_init_microcode()515 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_init_microcode()1034 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode() local1125 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1128 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1129 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1133 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1134 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
317 const struct rlc_firmware_header_v1_0 *rlc_hdr; in gfx_v6_0_init_microcode() local368 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()369 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()370 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
3975 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_init_microcode() local4016 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()4017 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v10_0_init_microcode()4018 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v10_0_init_microcode()5326 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode() local5359 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5362 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5363 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
1285 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v9_0_init_rlc_microcode() local1313 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()1315 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v9_0_init_rlc_microcode()1316 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v9_0_init_rlc_microcode()
115 const struct rlc_firmware_header_v1_0 *rlc_hdr = in radeon_ucode_print_rlc_hdr() local119 le32_to_cpu(rlc_hdr->ucode_feature_version)); in radeon_ucode_print_rlc_hdr()121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in radeon_ucode_print_rlc_hdr()123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in radeon_ucode_print_rlc_hdr()125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in radeon_ucode_print_rlc_hdr()127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in radeon_ucode_print_rlc_hdr()
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