| /linux-6.3-rc2/drivers/mmc/host/ |
| A D | sdhci.c | 60 sdhci_readw(host, SDHCI_HOST_VERSION)); in sdhci_dumpregs()
62 sdhci_readw(host, SDHCI_BLOCK_SIZE), in sdhci_dumpregs()
63 sdhci_readw(host, SDHCI_BLOCK_COUNT)); in sdhci_dumpregs()
66 sdhci_readw(host, SDHCI_TRANSFER_MODE)); in sdhci_dumpregs()
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs()
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), in sdhci_dumpregs()
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); in sdhci_dumpregs()
89 sdhci_readw(host, SDHCI_COMMAND), in sdhci_dumpregs()
98 sdhci_readw(host, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs()
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
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| A D | sdhci-milbeaut.c | 92 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
105 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
189 ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG); in sdhci_milbeaut_vendor_init()
218 ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_init()
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| A D | sdhci-pci-o2micro.c | 127 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
154 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) in sdhci_o2_get_cd()
200 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
212 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_o2_execute_tuning()
333 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
338 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
359 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
401 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
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| A D | sdhci-sprd.c | 167 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_off()
177 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_on()
328 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
524 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
655 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); in sdhci_sprd_probe()
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| A D | sdhci-pci-gli.c | 256 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
276 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
322 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_execute_tuning_9750()
816 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
996 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9763e_runtime_suspend()
1012 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9763e_runtime_resume()
1019 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), in gl9763e_runtime_resume()
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| A D | sdhci_f_sdh30.c | 70 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0) in sdhci_f_sdh30_reset()
176 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG); in sdhci_f_sdh30_probe()
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| A D | sdhci-pci-dwc-mshc.c | 36 vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R); in sdhci_snps_set_clock()
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| A D | sdhci-pci-arasan.c | 101 val = sdhci_readw(host, PHY_ADDR_REG); in arasan_phy_addr_poll()
125 *data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK; in arasan_phy_read()
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| A D | sdhci-xenon.c | 38 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
201 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
297 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_ios()
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| A D | sdhci-of-at91.c | 76 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
89 if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), in sdhci_at91_set_clock()
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| A D | sdhci-acpi.c | 485 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); in amd_select_drive_strength()
550 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
554 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
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| A D | sdhci.h | 700 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
738 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
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| A D | sdhci-of-dwcmshc.c | 159 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
177 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in dwcmshc_set_uhs_signaling()
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| A D | sdhci-s3c.c | 387 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
403 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) in sdhci_cmu_set_clock()
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| A D | sdhci-of-esdhc.c | 1226 command = SDHCI_GET_CMD(sdhci_readw(host, in esdhc_irq()
1229 sdhci_readw(host, SDHCI_BLOCK_COUNT) && in esdhc_irq()
1357 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); in esdhc_init()
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| A D | sdhci-brcmstb.c | 104 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
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| A D | sdhci-st.c | 261 u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
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| A D | sdhci-pxav3.c | 248 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
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| A D | sdhci-msm.c | 1324 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1777 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in __sdhci_msm_set_clock()
2333 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2362 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
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| A D | sdhci-of-arasan.c | 904 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in arasan_zynqmp_dll_reset()
911 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in arasan_zynqmp_dll_reset()
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| A D | sdhci-xenon-phy.c | 360 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & in xenon_emmc_phy_enable_dll()
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| A D | sdhci-pci-core.c | 1637 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1641 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
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| A D | sdhci-esdhc-imx.c | 1558 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); in esdhc_cqe_enable()
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| A D | sdhci-tegra.c | 257 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in tegra_sdhci_configure_card_clk()
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