| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | soc21.c | 257 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register() argument
262 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
263 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc21_read_indexed_register()
267 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
275 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
278 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
287 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
303 se_num, sh_num, reg_offset); in soc21_read_register()
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| A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| A D | nv.c | 409 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
414 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
415 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
419 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
427 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
430 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
439 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
455 se_num, sh_num, reg_offset); in nv_read_register()
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| A D | soc15.c | 402 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
407 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
408 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
412 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
420 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
423 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
434 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
450 se_num, sh_num, reg_offset); in soc15_read_register()
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| A D | cik.c | 1124 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1129 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1219 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
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| A D | vi.c | 749 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
754 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
768 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
769 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
773 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
844 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
855 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
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| A D | si.c | 1166 u32 sh_num, u32 reg_offset) in si_get_register_value() argument
1171 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1240 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register() argument
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
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| A D | amdgpu_kms.c | 728 unsigned sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
738 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
739 sh_num = 0xffffffff; in amdgpu_info_ioctl()
740 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
753 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
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| A D | gfx_v9_4.c | 94 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh() argument
111 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
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| A D | amdgpu_gfx.h | 226 u32 sh_num, u32 instance);
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| A D | gfx_v9_4_2.c | 847 u32 sh_num, u32 instance) in gfx_v9_4_2_select_se_sh() argument
864 if (sh_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
868 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
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| A D | gfx_v6_0.c | 1288 u32 sh_num, u32 instance) in gfx_v6_0_select_se_sh() argument
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1302 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1303 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1307 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
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| A D | gfx_v7_0.c | 1555 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1564 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1569 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1570 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1574 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
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| A D | amdgpu.h | 557 u32 sh_num, u32 reg_offset, u32 *value);
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| A D | gfx_v11_0.c | 115 u32 sh_num, u32 instance);
1480 u32 sh_num, u32 instance) in gfx_v11_0_select_se_sh() argument
1497 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1501 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
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| A D | gfx_v8_0.c | 3397 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3411 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3414 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
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| A D | gfx_v9_0.c | 2229 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2244 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2247 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
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| A D | gfx_v10_0.c | 3493 u32 sh_num, u32 instance);
4713 u32 sh_num, u32 instance) in gfx_v10_0_select_se_sh() argument
4730 if (sh_num == 0xffffffff) in gfx_v10_0_select_se_sh()
4734 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | si.c | 2947 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2951 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2954 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in si_select_se_sh()
2955 else if (sh_num == 0xffffffff) in si_select_se_sh()
2958 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
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| A D | cik.c | 3027 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3031 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3034 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in cik_select_se_sh()
3035 else if (sh_num == 0xffffffff) in cik_select_se_sh()
3038 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()
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