1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3  * Copyright 2020-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 /*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/
26 
27 #ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
28 #define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
29 
30 struct pm4_mes_map_process_aldebaran {
31 	union {
32 		union PM4_MES_TYPE_3_HEADER header;	/* header */
33 		uint32_t ordinal1;
34 	};
35 
36 	union {
37 		struct {
38 			uint32_t pasid:16;	    /* 0 - 15  */
39 			uint32_t single_memops:1;   /* 16      */
40 			uint32_t reserved1:1;	    /* 17      */
41 			uint32_t debug_vmid:4;	    /* 18 - 21 */
42 			uint32_t new_debug:1;	    /* 22      */
43 			uint32_t tmz:1;		    /* 23      */
44 			uint32_t diq_enable:1;      /* 24      */
45 			uint32_t process_quantum:7; /* 25 - 31 */
46 		} bitfields2;
47 		uint32_t ordinal2;
48 	};
49 
50 	uint32_t vm_context_page_table_base_addr_lo32;
51 
52 	uint32_t vm_context_page_table_base_addr_hi32;
53 
54 	uint32_t sh_mem_bases;
55 
56 	uint32_t sh_mem_config;
57 
58 	uint32_t sq_shader_tba_lo;
59 
60 	uint32_t sq_shader_tba_hi;
61 
62 	uint32_t sq_shader_tma_lo;
63 
64 	uint32_t sq_shader_tma_hi;
65 
66 	uint32_t reserved6;
67 
68 	uint32_t gds_addr_lo;
69 
70 	uint32_t gds_addr_hi;
71 
72 	union {
73 		struct {
74 			uint32_t num_gws:7;
75 			uint32_t sdma_enable:1;
76 			uint32_t num_oac:4;
77 			uint32_t gds_size_hi:4;
78 			uint32_t gds_size:6;
79 			uint32_t num_queues:10;
80 		} bitfields14;
81 		uint32_t ordinal14;
82 	};
83 
84 	uint32_t spi_gdbg_per_vmid_cntl;
85 
86 	uint32_t tcp_watch_cntl[4];
87 
88 	uint32_t completion_signal_lo;
89 
90 	uint32_t completion_signal_hi;
91 
92 };
93 
94 #endif
95