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Searched refs:spx5_rmw (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_port.c352 spx5_rmw(0, in sparx5_port_disable()
358 spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS, in sparx5_port_disable()
386 spx5_rmw(0, in sparx5_port_disable()
447 spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0), in sparx5_port_disable()
529 spx5_rmw(BIT(inst), in sparx5_port_mux_set()
849 spx5_rmw(hsd ? 0 : bt_indx, in sparx5_dev_switch()
854 spx5_rmw(hsd ? 0 : bt_indx, in sparx5_dev_switch()
859 spx5_rmw(hsd ? 0 : bt_indx, in sparx5_dev_switch()
1201 spx5_rmw(REW_PCP_MAP_DE1_PCP_DE1_SET(pcp), in sparx5_port_qos_pcp_rewr_set()
1205 spx5_rmw(REW_DEI_MAP_DE1_DEI_DE1_SET(dei), in sparx5_port_qos_pcp_rewr_set()
[all …]
A Dsparx5_fdma.c136 spx5_rmw(BIT(rx->channel_id), in sparx5_fdma_rx_activate()
147 spx5_rmw(0, BIT(rx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_rx_deactivate()
151 spx5_rmw(0, BIT(rx->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_rx_deactivate()
183 spx5_rmw(0, BIT(tx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_tx_deactivate()
286 spx5_rmw(BIT(rx->channel_id), in sparx5_fdma_napi_callback()
511 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_fdma_injection_mode()
517 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(100), in sparx5_fdma_injection_mode()
524 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1) | in sparx5_fdma_injection_mode()
534 spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(1), in sparx5_fdma_injection_mode()
540 spx5_rmw(HSCH_PORT_MODE_AGE_DIS_SET(1), in sparx5_fdma_injection_mode()
[all …]
A Dsparx5_vlan.c29 spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1), in sparx5_vlan_init()
36 spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid), in sparx5_vlan_init()
47 spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) | in sparx5_vlan_port_setup()
127 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_update_mask()
131 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_update_mask()
135 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_update_mask()
234 spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid), in sparx5_vlan_port_apply()
A Dsparx5_ptp.c284 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_get_hwtimestamp()
342 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
369 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
422 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)), in sparx5_ptp_adjfine()
431 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0), in sparx5_ptp_adjfine()
450 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_settime64()
466 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | in sparx5_ptp_settime64()
489 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_ptp_gettime64()
527 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_adjtime()
617 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0x7), in sparx5_ptp_init()
[all …]
A Dsparx5_main.c389 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), in sparx5_init_switchcore()
394 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), in sparx5_init_switchcore()
489 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | in sparx5_init_coreclock()
506 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), in sparx5_init_coreclock()
521 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
527 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), in sparx5_init_coreclock()
532 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET in sparx5_init_coreclock()
538 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), in sparx5_init_coreclock()
580 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, in sparx5_board_init()
611 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), in sparx5_start()
[all …]
A Dsparx5_psfp.c75 spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID, in sparx5_isdx_conf_set()
78 spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX, in sparx5_isdx_conf_set()
121 spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) | in sparx5_psfp_sf_set()
150 spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) | in sparx5_psfp_sg_set()
330 spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1), in sparx5_psfp_init()
A Dsparx5_police.c32 spx5_rmw(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(max_pup_tokens), in sparx5_policer_service_conf_set()
36 spx5_rmw(ANA_AC_SDLB_THRES_THRES_SET(thres), ANA_AC_SDLB_THRES_THRES, in sparx5_policer_service_conf_set()
A Dsparx5_qos.c248 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_lg_conf_set()
256 spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first), in sparx5_lg_conf_set()
338 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_shaper_conf_set()
342 spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE, in sparx5_shaper_conf_set()
367 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | in sparx5_dwrr_conf_set()
373 spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count), in sparx5_dwrr_conf_set()
378 spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]), in sparx5_dwrr_conf_set()
A Dsparx5_packet.c290 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_injection_timeout()
322 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_manual_injection_mode()
328 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0), in sparx5_manual_injection_mode()
335 spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0), in sparx5_manual_injection_mode()
A Dsparx5_calendar.c211 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), in sparx5_config_auto_calendar()
222 spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */ in sparx5_config_auto_calendar()
234 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8), in sparx5_config_auto_calendar()
543 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), in sparx5_dsm_calendar_update()
547 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]), in sparx5_dsm_calendar_update()
A Dsparx5_sdlb.c61 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(0), in sparx5_sdlb_group_disable()
68 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(1), in sparx5_sdlb_group_enable()
A Dsparx5_vcap_impl.c1540 spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, in sparx5_vcap_is0_port_key_selection()
1569 spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0xf), in sparx5_vcap_is2_port_key_selection()
1584 spx5_rmw(keysel, REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, in sparx5_vcap_es0_port_key_selection()
1587 spx5_rmw(REW_ES0_CTRL_ES0_LU_ENA_SET(1), REW_ES0_CTRL_ES0_LU_ENA, in sparx5_vcap_es0_port_key_selection()
1640 spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(0), in sparx5_vcap_port_key_deselection()
1647 spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0), in sparx5_vcap_port_key_deselection()
1653 spx5_rmw(REW_ES0_CTRL_ES0_LU_ENA_SET(0), in sparx5_vcap_port_key_deselection()
1659 spx5_rmw(EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(0), in sparx5_vcap_port_key_deselection()
A Dsparx5_mactable.c482 spx5_rmw(LRN_AUTOAGE_CFG_UNIT_SIZE_SET(2) | /* 10 ms */ in sparx5_set_ageing()
A Dsparx5_main.h647 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, in spx5_rmw() function
A Dsparx5_switchdev.c508 spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(enable), in sparx5_cpu_copy_ena()
A Dsparx5_ethtool.c1163 spx5_rmw(ANA_AC_PORT_SGE_CFG_MASK_SET(0xf0f0), in sparx5_config_stats()
1177 spx5_rmw(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(1) | in sparx5_config_port_stats()

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