Searched refs:target_itr (Results 1 – 8 of 8) sorted by relevance
483 itr = rc->target_itr; in iavf_update_itr()507 if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS && in iavf_update_itr()508 (q_vector->rx.target_itr & IAVF_ITR_MASK) == in iavf_update_itr()515 rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY; in iavf_update_itr()527 itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC; in iavf_update_itr()634 rc->target_itr = itr; in iavf_update_itr()1687 q_vector->rx.target_itr); in iavf_update_enable_itr()1688 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_update_enable_itr()1697 q_vector->tx.target_itr); in iavf_update_enable_itr()1698 q_vector->tx.current_itr = q_vector->tx.target_itr; in iavf_update_enable_itr()[all …]
424 u16 target_itr; /* target ITR setting for ring(s) */ member
454 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_map_vector_to_rxq()458 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_map_vector_to_rxq()480 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_map_vector_to_txq()483 q_vector->tx.target_itr >> 1); in iavf_map_vector_to_txq()484 q_vector->tx.current_itr = q_vector->tx.target_itr; in iavf_map_vector_to_txq()
800 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_set_itr_per_queue()803 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_set_itr_per_queue()
1197 itr = rc->target_itr; in i40e_update_itr()1221 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && in i40e_update_itr()1222 (q_vector->rx.target_itr & I40E_ITR_MASK) == in i40e_update_itr()1229 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; in i40e_update_itr()1241 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; in i40e_update_itr()1347 rc->target_itr = itr; in i40e_update_itr()2654 q_vector->rx.target_itr); in i40e_update_enable_itr()2655 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_update_enable_itr()2664 q_vector->tx.target_itr); in i40e_update_enable_itr()2665 q_vector->tx.current_itr = q_vector->tx.target_itr; in i40e_update_enable_itr()[all …]
435 u16 target_itr; /* target ITR setting for ring(s) */ member
3871 q_vector->rx.target_itr = in i40e_vsi_configure_msix()3874 q_vector->rx.target_itr >> 1); in i40e_vsi_configure_msix()3875 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_vsi_configure_msix()3878 q_vector->tx.target_itr = in i40e_vsi_configure_msix()3881 q_vector->tx.target_itr >> 1); in i40e_vsi_configure_msix()3882 q_vector->tx.current_itr = q_vector->tx.target_itr; in i40e_vsi_configure_msix()3985 q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()3986 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr >> 1); in i40e_configure_msi_and_legacy()3987 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_configure_msi_and_legacy()3989 q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()[all …]
2987 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in i40e_set_itr_per_queue()2990 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in i40e_set_itr_per_queue()
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