| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp_cm.c | 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
213 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
215 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
269 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
277 reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
296 reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
304 reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_degamma_reg_field()
469 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp1_program_input_csc()
[all …]
|
| A D | dcn10_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
563 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument
573 dpp->tf_shift = tf_shift; in dpp1_construct()
|
| A D | dcn10_dpp_dscl.c | 54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
369 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
|
| A D | dcn10_resource.c | 356 static const struct dcn_dpp_shift tf_shift = { variable
588 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
|
| A D | dcn10_dpp.h | 1356 const struct dcn_dpp_shift *tf_shift; member
1518 const struct dcn_dpp_shift *tf_shift,
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dpp_cm.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
176 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
178 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
181 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
185 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
190 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
192 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
194 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
198 reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
344 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
[all …]
|
| A D | dcn30_dpp.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
634 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
638 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
643 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
645 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
647 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
651 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1472 const struct dcn3_dpp_shift *tf_shift, in dpp3_construct() argument
[all …]
|
| A D | dcn30_dpp.h | 562 const struct dcn3_dpp_shift *tf_shift; member
581 const struct dcn3_dpp_shift *tf_shift,
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/ |
| A D | dcn32_dpp.c | 150 const struct dcn3_dpp_shift *tf_shift, in dpp32_construct() argument
160 dpp->tf_shift = tf_shift; in dpp32_construct()
|
| A D | dcn32_dpp.h | 35 const struct dcn3_dpp_shift *tf_shift,
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dpp_cm.c | 47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
284 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
286 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
362 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
366 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
371 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
373 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
375 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
|
| A D | dcn20_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
408 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument
418 dpp->tf_shift = tf_shift; in dpp2_construct()
|
| A D | dcn20_dpp.h | 682 const struct dcn2_dpp_shift *tf_shift; member
772 const struct dcn2_dpp_shift *tf_shift,
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dpp.h | 61 const struct dcn201_dpp_shift *tf_shift; member
80 const struct dcn201_dpp_shift *tf_shift,
|
| A D | dcn201_dpp.c | 42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
297 const struct dcn201_dpp_shift *tf_shift, in dpp201_construct() argument
307 dpp->tf_shift = tf_shift; in dpp201_construct()
|
| A D | dcn201_resource.c | 475 static const struct dcn201_dpp_shift tf_shift = { variable
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 505 static const struct dcn3_dpp_shift tf_shift = { variable
520 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 545 static const struct dcn3_dpp_shift tf_shift = { variable
560 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 442 static const struct dcn2_dpp_shift tf_shift = { variable
510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 413 static const struct dcn3_dpp_shift tf_shift = { variable
739 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/ |
| A D | dcn316_resource.c | 483 static const struct dcn3_dpp_shift tf_shift = { variable
936 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/ |
| A D | dcn314_resource.c | 508 static const struct dcn3_dpp_shift tf_shift = { variable
973 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn315/ |
| A D | dcn315_resource.c | 487 static const struct dcn3_dpp_shift tf_shift = { variable
937 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn321/ |
| A D | dcn321_resource.c | 368 static const struct dcn3_dpp_shift tf_shift = { variable
943 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn321_dpp_create()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 486 static const struct dcn3_dpp_shift tf_shift = { variable
941 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
|