| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_hwseq.c | 177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
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| A D | dce_stream_encoder.c | 1488 int tg_inst, bool enable) in setup_stereo_sync() argument
1491 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1497 int tg_inst) in dig_connect_to_otg() argument
1501 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1507 uint32_t tg_inst = 0; in dig_source_otg() local
1510 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1512 return tg_inst; in dig_source_otg()
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| A D | dce_hwseq.h | 1207 unsigned int tg_inst);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 265 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; in dc_dmub_srv_drr_update_cmd()
275 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) in dc_dmub_srv_set_drr_manual_trigger_cmd() argument
281 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; in dc_dmub_srv_set_drr_manual_trigger_cmd()
307 int tg_inst = 0; in dc_dmub_srv_get_timing_generator_offset() local
314 tg_inst = pipe->stream_res.tg->inst; in dc_dmub_srv_get_timing_generator_offset()
318 return tg_inst; in dc_dmub_srv_get_timing_generator_offset()
343 int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); in dc_dmub_srv_p_state_delegate() local
345 config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; in dc_dmub_srv_p_state_delegate()
346 config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; in dc_dmub_srv_p_state_delegate()
347 config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; in dc_dmub_srv_p_state_delegate()
[all …]
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| A D | dc_dmub_srv.h | 75 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtot…
77 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/virtual/ |
| A D | virtual_stream_encoder.c | 93 int tg_inst) in virtual_dig_connect_to_otg() argument
98 int tg_inst, in virtual_setup_stereo_sync() argument
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_stream_encoder.c | 1483 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1486 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1492 int tg_inst) in enc1_dig_connect_to_otg() argument
1496 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1502 uint32_t tg_inst = 0; in enc1_dig_source_otg() local
1505 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
1507 return tg_inst; in enc1_dig_source_otg()
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| A D | dcn10_stream_encoder.h | 666 int tg_inst, bool enable);
698 int tg_inst);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | stream_encoder.h | 220 int tg_inst,
228 int tg_inst);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 2098 int tg_inst = pool->timing_generator_count - 1; in acquire_first_free_pipe() local
2101 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; in acquire_first_free_pipe()
2345 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
2360 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state()
2370 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
2373 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
2374 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
2376 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
2377 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
2384 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
[all …]
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| A D | dc.c | 1180 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local
1187 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required()
1195 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required()
1533 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_boot_timing() local
1554 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_boot_timing()
1564 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_boot_timing()
1567 if (tg_inst != link->link_enc->preferred_engine) in dc_validate_boot_timing()
1570 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_boot_timing()
1625 tg_inst, &pix_clk_100hz); in dc_validate_boot_timing()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 3074 uint32_t tg_inst; member
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