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Searched refs:tiling (Results 1 – 25 of 39) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/gem/
A Di915_gem_tiling.c62 if (tiling == I915_TILING_NONE) in i915_gem_fence_size()
68 stride *= i915_gem_tile_height(tiling); in i915_gem_fence_size()
96 unsigned int tiling, unsigned int stride) in i915_gem_fence_alignment() argument
104 if (tiling == I915_TILING_NONE) in i915_gem_fence_alignment()
120 unsigned int tiling, unsigned int stride) in i915_tiling_ok() argument
126 if (tiling == I915_TILING_NONE) in i915_tiling_ok()
129 if (tiling > I915_TILING_LAST) in i915_tiling_ok()
232 unsigned int tiling, unsigned int stride) in i915_gem_object_set_tiling() argument
282 if (tiling == I915_TILING_NONE) { in i915_gem_object_set_tiling()
300 vma->size, tiling, stride); in i915_gem_object_set_tiling()
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A Di915_gem_tiling.h16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
A Di915_gem_object.h328 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
330 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
331 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
348 unsigned int tiling, unsigned int stride);
/linux-6.3-rc2/drivers/gpu/drm/tegra/
A Dfb.c44 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
59 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
60 tiling->value = 0; in tegra_fb_get_tiling()
64 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
65 tiling->value = 0; in tegra_fb_get_tiling()
70 tiling->value = 0; in tegra_fb_get_tiling()
75 tiling->value = 1; in tegra_fb_get_tiling()
80 tiling->value = 2; in tegra_fb_get_tiling()
85 tiling->value = 3; in tegra_fb_get_tiling()
90 tiling->value = 4; in tegra_fb_get_tiling()
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A Dhub.c432 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
446 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_shared_plane_atomic_check()
450 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
456 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && in tegra_shared_plane_atomic_check()
637 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) in tegra_shared_plane_atomic_update()
717 unsigned long height = tegra_plane_state->tiling.value; in tegra_shared_plane_atomic_update()
720 switch (tegra_plane_state->tiling.mode) { in tegra_shared_plane_atomic_update()
A Dgem.h49 struct tegra_bo_tiling tiling; member
A Dplane.h49 struct tegra_bo_tiling tiling; member
A Dplane.c63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
A Ddrm.h198 struct tegra_bo_tiling *tiling);
A Ddc.c427 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
429 switch (window->tiling.mode) { in tegra_dc_setup_window()
446 switch (window->tiling.mode) { in tegra_dc_setup_window()
626 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
658 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
662 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
758 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
A Ddrm.c653 bo->tiling.mode = mode; in tegra_gem_set_tiling()
654 bo->tiling.value = value; in tegra_gem_set_tiling()
675 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
688 args->value = bo->tiling.value; in tegra_gem_get_tiling()
/linux-6.3-rc2/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_client_blt.c97 enum client_tiling tiling; member
228 if (src->tiling) { in prepare_blit()
234 if (dst->tiling) { in prepare_blit()
328 t->buffers[i].tiling = in tiled_blits_create_buffers()
360 enum client_tiling tiling, in tiled_offset() argument
366 if (tiling == CLIENT_TILING_LINEAR) in tiled_offset()
371 if (tiling == CLIENT_TILING_4) { in tiled_offset()
415 switch (tiling) { in repr_tiling()
445 buf->tiling, x, y); in verify_buffer()
452 repr_tiling(buf->tiling), in verify_buffer()
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A Di915_gem_mman.c35 unsigned int tiling; member
48 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
54 if (tile->tiling == I915_TILING_X) { in tiled_offset()
111 tile->tiling, tile->stride, err); in check_partial_mapping()
321 int tiling; in igt_partial_tiling() local
359 tile.tiling = I915_TILING_NONE; in igt_partial_tiling()
366 for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) { in igt_partial_tiling()
380 tile.tiling = tiling; in igt_partial_tiling()
381 switch (tiling) { in igt_partial_tiling()
491 tile.tiling = in igt_smoke_tiling()
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/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_ggtt_fencing.c77 if (fence->tiling) { in i965_write_fence_reg()
86 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
118 if (fence->tiling) { in i915_write_fence_reg()
120 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
121 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
152 if (fence->tiling) { in i830_write_fence_reg()
156 if (fence->tiling == I915_TILING_Y) in i830_write_fence_reg()
209 fence->tiling = 0; in fence_update()
228 fence->tiling = i915_gem_object_get_tiling(vma->obj); in fence_update()
304 fence->tiling = 0; in i915_vma_revoke_fence()
A Dintel_ggtt_fencing.h40 u32 tiling; member
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_plane_initial.c125 switch (plane_config->tiling) { in initial_plane_vma()
132 plane_config->tiling; in initial_plane_vma()
135 MISSING_CASE(plane_config->tiling); in initial_plane_vma()
274 if (plane_config->tiling) in intel_find_initial_plane_obj()
A Dintel_fb.c1883 unsigned int tiling, stride; in intel_framebuffer_init() local
1892 tiling = i915_gem_object_get_tiling(obj); in intel_framebuffer_init()
1901 if (tiling != I915_TILING_NONE && in intel_framebuffer_init()
1902 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
1908 if (tiling == I915_TILING_X) { in intel_framebuffer_init()
1910 } else if (tiling == I915_TILING_Y) { in intel_framebuffer_init()
1931 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
1952 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { in intel_framebuffer_init()
A Dskl_universal_plane.c2383 u32 val, base, offset, stride_mult, tiling, alpha; in skl_get_initial_plane_config() local
2431 tiling = val & PLANE_CTL_TILED_MASK; in skl_get_initial_plane_config()
2432 switch (tiling) { in skl_get_initial_plane_config()
2437 plane_config->tiling = I915_TILING_X; in skl_get_initial_plane_config()
2441 plane_config->tiling = I915_TILING_Y; in skl_get_initial_plane_config()
2473 MISSING_CASE(tiling); in skl_get_initial_plane_config()
/linux-6.3-rc2/drivers/gpu/drm/vc4/
A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
A Dvc4_plane.c829 u32 tiling, src_y; in vc4_plane_mode_set() local
867 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
930 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
966 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
972 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
975 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
978 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
1069 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
1109 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
/linux-6.3-rc2/drivers/staging/media/ipu3/
A Dipu3-css-params.c313 unsigned int tiling; member
426 unsigned int tiling = 0; in imgu_css_osys_calc_frame_and_stripe_params() local
466 &tiling); in imgu_css_osys_calc_frame_and_stripe_params()
472 frame_params[pin].tiling = tiling; in imgu_css_osys_calc_frame_and_stripe_params()
998 fr_pr->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
1081 if (frame_params[pin].tiling) { in imgu_css_osys_calc()
1150 param->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20v2.c343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
A Ddisplay_rq_dlg_calc_20.c343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c330 unsigned int tiling, in get_meta_and_pte_attr() argument
336 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
411 (enum dm_swizzle_mode) (tiling), in get_meta_and_pte_attr()
449 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c288 unsigned int tiling, in get_meta_and_pte_attr() argument
295 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
365 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
405 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()

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