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Searched refs:tiling_flags (Results 1 – 25 of 29) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dradeon_object.c531 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
536 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
552 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
590 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
612 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
620 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
665 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
672 uint32_t *tiling_flags, in radeon_bo_get_tiling_flags() argument
677 if (tiling_flags) in radeon_bo_get_tiling_flags()
678 *tiling_flags = bo->tiling_flags; in radeon_bo_get_tiling_flags()
[all …]
A Dradeon_fb.c138 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
165 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
170 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
173 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
180 if (tiling_flags) { in radeonfb_create_pinned_object()
182 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
A Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
A Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
A Dr300.c717 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
719 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
721 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
786 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
788 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
790 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
871 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
873 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
875 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
A Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
A Devergreen_cs.c92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
94 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
96 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1184 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1448 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1476 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
2362 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
[all …]
A Datombios_crtc.c1145 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1265 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1339 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1577 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1579 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1582 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
A Dr100.c1291 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1633 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1635 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3091 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3101 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3108 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()
3110 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3113 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3115 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3119 if (tiling_flags & RADEON_TILING_SWAP_16BIT) in r100_set_surface_reg()
[all …]
A Dr600_cs.c1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
A Dradeon_gem.c588 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
609 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
A Dradeon_vm.c147 list[0].tiling_flags = 0; in radeon_vm_get_bos()
159 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
A Dradeon_display.c492 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
552 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
A Dradeon.h355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
464 uint32_t tiling_flags; member
495 u32 tiling_flags; member
1967 uint32_t tiling_flags, uint32_t pitch,
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_display.c201 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
256 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
711 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
714 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
835 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
893 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) in check_tiling_flags_gfx6()
1082 uint64_t *tiling_flags, bool *tmz_surface) in amdgpu_display_get_fb_info() argument
1088 *tiling_flags = 0; in amdgpu_display_get_fb_info()
1103 if (tiling_flags) in amdgpu_display_get_fb_info()
1104 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in amdgpu_display_get_fb_info()
[all …]
A Damdgpu_object.h115 u64 tiling_flags; member
308 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
309 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
A Damdgpu_object.c1103 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1110 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1114 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1126 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1134 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1135 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
A Ddce_v6_0.c1819 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1855 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1938 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1941 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1942 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1943 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1944 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1945 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1953 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1957 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
A Ddce_v8_0.c1789 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1826 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1829 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1911 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1914 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1915 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1916 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1917 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1918 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1927 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
A Ddce_v10_0.c1860 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1897 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1900 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1990 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1993 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1994 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1995 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1996 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1997 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2010 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
A Ddce_v11_0.c1902 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1939 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1942 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2032 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2035 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2036 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2037 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2038 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2039 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2052 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
A Damdgpu_mode.h301 uint64_t tiling_flags; member
/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c176 uint64_t tiling_flags) in fill_gfx8_tiling_info_from_flags() argument
182 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()
183 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
184 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags()
185 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_gfx8_tiling_info_from_flags()
186 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_gfx8_tiling_info_from_flags()
198 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_gfx8_tiling_info_from_flags()
204 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_gfx8_tiling_info_from_flags()
766 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
837 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); in fill_plane_buffer_attributes()
[all …]
A Damdgpu_dm_plane.h46 const uint64_t tiling_flags,
/linux-6.3-rc2/include/uapi/drm/
A Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member

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