/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
A D | mediatek,topckgen.yaml | 21 - mediatek,mt6797-topckgen 22 - mediatek,mt7622-topckgen 23 - mediatek,mt8135-topckgen 24 - mediatek,mt8173-topckgen 25 - mediatek,mt8516-topckgen 32 - mediatek,mt2701-topckgen 33 - mediatek,mt2712-topckgen 34 - mediatek,mt6765-topckgen 35 - mediatek,mt6779-topckgen 36 - mediatek,mt6795-topckgen [all …]
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A D | mediatek,mt8365-sys-clock.yaml | 14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks. 21 - mediatek,mt8365-topckgen 43 topckgen: clock-controller@10000000 { 44 compatible = "mediatek,mt8365-topckgen", "syscon";
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/linux-6.3-rc2/Documentation/devicetree/bindings/sound/ |
A D | mt8186-afe-pcm.yaml | 36 mediatek,topckgen: 103 - mediatek,topckgen 122 mediatek,topckgen = <&topckgen>; 125 <&topckgen 15>, //CLK_TOP_AUDIO 126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS 128 <&topckgen 17>, //CLK_TOP_AUD_1 130 <&topckgen 18>, //CLK_TOP_AUD_2 132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1 133 <&topckgen 101>, //CLK_TOP_APLL1_D8 135 <&topckgen 104>, //CLK_TOP_APLL2_D8 [all …]
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A D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>, 70 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 71 <&topckgen CLK_TOP_AUD_48K_TIMING>, 72 <&topckgen CLK_TOP_AUD_44K_TIMING>, 73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 81 <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 82 <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 83 <&topckgen CLK_TOP_AUD_I2S3_MCLK>, [all …]
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A D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>, 27 <&topckgen TOP_AUD_INTBUS_SEL>, 28 <&topckgen TOP_APLL1_DIV0>, 29 <&topckgen TOP_APLL2_DIV0>, 30 <&topckgen TOP_I2S0_M_CK_SEL>, 31 <&topckgen TOP_I2S1_M_CK_SEL>, 32 <&topckgen TOP_I2S2_M_CK_SEL>, 33 <&topckgen TOP_I2S3_M_CK_SEL>, 34 <&topckgen TOP_I2S3_B_CK_SEL>;
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A D | mt8195-afe-pcm.yaml | 34 mediatek,topckgen: 138 - mediatek,topckgen 157 mediatek,topckgen = <&topckgen>; 161 <&topckgen 163>, //CLK_TOP_APLL1 162 <&topckgen 166>, //CLK_TOP_APLL2 170 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL 172 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL 173 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL 174 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL 175 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL [all …]
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A D | mediatek,mt8188-afe.yaml | 28 mediatek,topckgen: 146 - mediatek,topckgen 164 mediatek,topckgen = <&topckgen>; 178 <&topckgen 83>, //CLK_TOP_A1SYS_HP 179 <&topckgen 31>, //CLK_TOP_AUD_INTBUS 180 <&topckgen 32>, //CLK_TOP_AUDIO_H 182 <&topckgen 81>, //CLK_TOP_DPTX 183 <&topckgen 77>, //CLK_TOP_I2SO1 184 <&topckgen 78>, //CLK_TOP_I2SO2 185 <&topckgen 79>, //CLK_TOP_I2SI1 [all …]
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A D | mt6797-afe-pcm.txt | 29 <&topckgen CLK_TOP_MUX_AUDIO>, 30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 31 <&topckgen CLK_TOP_SYSPLL3_D4>, 32 <&topckgen CLK_TOP_SYSPLL1_D4>,
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A D | mt8192-afe-pcm.yaml | 34 mediatek,topckgen: 36 description: The phandle of the mediatek topckgen controller 64 - mediatek,topckgen 86 mediatek,topckgen = <&topckgen>;
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/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
A D | mt8516.dtsi | 182 topckgen: topckgen@10000000 { label 219 <&topckgen CLK_TOP_APXGPT>; 305 <&topckgen CLK_TOP_UART0>; 319 <&topckgen CLK_TOP_UART1>; 333 <&topckgen CLK_TOP_UART2>; 348 <&topckgen CLK_TOP_APDMA>; 362 <&topckgen CLK_TOP_APDMA>; 376 <&topckgen CLK_TOP_APDMA>; 392 <&topckgen CLK_TOP_SPI>; 456 <&topckgen CLK_TOP_PWM_B>, [all …]
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A D | mt8186.dtsi | 356 topckgen: syscon@10000000 { label 483 <&topckgen CLK_TOP_MDP>, 810 <&topckgen CLK_TOP_SPI>, 834 <&topckgen CLK_TOP_SPI>, 847 <&topckgen CLK_TOP_SPI>, 860 <&topckgen CLK_TOP_SPI>, 873 <&topckgen CLK_TOP_SPI>, 886 <&topckgen CLK_TOP_SPI>, 927 <&topckgen CLK_TOP_AUDIO>, 930 <&topckgen CLK_TOP_AUD_1>, [all …]
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A D | mt8192.dtsi | 341 topckgen: syscon@10000000 { label 682 <&topckgen CLK_TOP_SPI_SEL>, 707 <&topckgen CLK_TOP_SPI_SEL>, 721 <&topckgen CLK_TOP_SPI_SEL>, 735 <&topckgen CLK_TOP_SPI_SEL>, 749 <&topckgen CLK_TOP_SPI_SEL>, 763 <&topckgen CLK_TOP_SPI_SEL>, 777 <&topckgen CLK_TOP_SPI_SEL>, 847 mediatek,topckgen = <&topckgen>; 875 <&topckgen CLK_TOP_APLL1>, [all …]
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A D | mt7622.dtsi | 259 <&topckgen CLK_TOP_AXI_SEL>; 292 topckgen: topckgen@10210000 { label 332 clocks = <&topckgen CLK_TOP_RTC>; 500 <&topckgen CLK_TOP_SPI0_SEL>, 581 <&topckgen CLK_TOP_FLASH_SEL>; 593 <&topckgen CLK_TOP_SPI1_SEL>, 624 <&topckgen CLK_TOP_AUD1_SEL>, 625 <&topckgen CLK_TOP_AUD2_SEL>, 696 <&topckgen CLK_TOP_AUD2PLL>; 718 <&topckgen CLK_TOP_AXI_SEL>; [all …]
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A D | mt7986a.dtsi | 164 topckgen: topckgen@1001b000 { label 254 <&topckgen CLK_TOP_UART_SEL>; 304 clocks = <&topckgen CLK_TOP_MPLL_D2>, 305 <&topckgen CLK_TOP_SPI_SEL>, 318 clocks = <&topckgen CLK_TOP_MPLL_D2>, 319 <&topckgen CLK_TOP_SPIM_MST_SEL>, 337 <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 517 <&topckgen CLK_TOP_NETSYS_SEL>, 518 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 526 <&topckgen CLK_TOP_SGM_325M_SEL>; [all …]
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A D | mt8195.dtsi | 389 topckgen: syscon@10000000 { label 486 <&topckgen CLK_TOP_CAM>, 487 <&topckgen CLK_TOP_CCU>, 488 <&topckgen CLK_TOP_IMG>, 885 mediatek,topckgen = <&topckgen>; 1015 <&topckgen CLK_TOP_SPI>, 1029 <&topckgen CLK_TOP_SPI>, 1043 <&topckgen CLK_TOP_SPI>, 1057 <&topckgen CLK_TOP_SPI>, 1071 <&topckgen CLK_TOP_SPI>, [all …]
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A D | mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>; 103 <&topckgen CLK_TOP_F_MP0_PLL1>; 116 <&topckgen CLK_TOP_F_BIG_PLL1>; 246 topckgen: syscon@10000000 { label 285 <&topckgen CLK_TOP_MFG_SEL>, 286 <&topckgen CLK_TOP_VENC_SEL>, 289 <&topckgen CLK_TOP_VDEC_SEL>; 556 <&topckgen CLK_TOP_SPI_SEL>, 635 <&topckgen CLK_TOP_SPI_SEL>, 648 <&topckgen CLK_TOP_SPI_SEL>, [all …]
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A D | mt8173.dtsi | 466 <&topckgen CLK_TOP_VENC_SEL>; 534 <&topckgen CLK_TOP_RTC_SEL>; 762 <&topckgen CLK_TOP_SPI_SEL>, 858 <&topckgen CLK_TOP_AUDIO_SEL>, 860 <&topckgen CLK_TOP_APLL1_DIV0>, 861 <&topckgen CLK_TOP_APLL2_DIV0>, 880 <&topckgen CLK_TOP_APLL2>; 898 <&topckgen CLK_TOP_AXI_SEL>; 908 <&topckgen CLK_TOP_AXI_SEL>; 1399 <&topckgen CLK_TOP_VDEC_SEL>, [all …]
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A D | mt8167.dtsi | 20 topckgen: topckgen@10000000 { label 21 compatible = "mediatek,mt8167-topckgen", "syscon"; 51 clocks = <&topckgen CLK_TOP_SMI_MM>; 59 clocks = <&topckgen CLK_TOP_SMI_MM>, 60 <&topckgen CLK_TOP_RG_VDEC>; 67 clocks = <&topckgen CLK_TOP_SMI_MM>; 74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, 75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
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A D | mt8183.dtsi | 803 topckgen: syscon@10000000 { label 1180 <&topckgen CLK_TOP_MUX_SPI>, 1380 <&topckgen CLK_TOP_MUX_SPI>, 1407 <&topckgen CLK_TOP_MUX_SPI>, 1420 <&topckgen CLK_TOP_MUX_SPI>, 1493 <&topckgen CLK_TOP_MUX_SPI>, 1506 <&topckgen CLK_TOP_MUX_SPI>, 1602 <&topckgen CLK_TOP_APLL1_CK>, 1604 <&topckgen CLK_TOP_APLL2_CK>, 1606 <&topckgen CLK_TOP_APLL1_D8>, [all …]
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/linux-6.3-rc2/arch/arm/boot/dts/ |
A D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>; 137 topckgen: syscon@10210000 { label 253 <&topckgen CLK_TOP_UNIVPLL2_D4>; 282 <&topckgen CLK_TOP_SPI0_SEL>, 293 <&topckgen CLK_TOP_FLASH_SEL>; 320 <&topckgen CLK_TOP_SATA_SEL>, 321 <&topckgen CLK_TOP_HIF_SEL>; 388 <&topckgen CLK_TOP_AXI_SEL>, 389 <&topckgen CLK_TOP_HIF_SEL>; 391 <&topckgen CLK_TOP_SYSPLL1_D2>, [all …]
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A D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label 156 clocks = <&topckgen CLK_TOP_MM_SEL>, 157 <&topckgen CLK_TOP_MFG_SEL>, 158 <&topckgen CLK_TOP_ETHIF_SEL>; 343 <&topckgen CLK_TOP_SPI0_SEL>, 389 <&topckgen CLK_TOP_FLASH_SEL>; 403 <&topckgen CLK_TOP_SPI1_SEL>, 416 <&topckgen CLK_TOP_SPI2_SEL>, 435 <&topckgen CLK_TOP_AUD_MUX1_SEL>, 613 <&topckgen CLK_TOP_ETHIF_SEL>; [all …]
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A D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label 228 "mediatek,mt2701-topckgen", 277 clocks = <&topckgen CLK_TOP_MM_SEL>, 278 <&topckgen CLK_TOP_MFG_SEL>, 279 <&topckgen CLK_TOP_ETHIF_SEL>; 488 <&topckgen CLK_TOP_SPI0_SEL>, 552 <&topckgen CLK_TOP_FLASH_SEL>; 567 <&topckgen CLK_TOP_SPI1_SEL>, 581 <&topckgen CLK_TOP_SPI2_SEL>, 866 <&topckgen CLK_TOP_ETHIF_SEL>; [all …]
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/linux-6.3-rc2/Documentation/devicetree/bindings/media/ |
A D | mediatek,vcodec-decoder.yaml | 143 <&topckgen CLK_TOP_UNIVPLL_D2>, 144 <&topckgen CLK_TOP_CCI400_SEL>, 145 <&topckgen CLK_TOP_VDEC_SEL>, 146 <&topckgen CLK_TOP_VCODECPLL>, 148 <&topckgen CLK_TOP_VENC_LT_SEL>, 149 <&topckgen CLK_TOP_VCODECPLL_370P5>; 158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 159 <&topckgen CLK_TOP_CCI400_SEL>, 160 <&topckgen CLK_TOP_VDEC_SEL>, 164 <&topckgen CLK_TOP_UNIVPLL_D2>, [all …]
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/linux-6.3-rc2/Documentation/devicetree/bindings/arm/mediatek/ |
A D | mediatek,mt8186-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks. 31 - mediatek,mt8186-topckgen 53 topckgen: syscon@10000000 { 54 compatible = "mediatek,mt8186-topckgen", "syscon";
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A D | mediatek,mt8195-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks. 28 - mediatek,mt8195-topckgen 51 topckgen: syscon@10000000 { 52 compatible = "mediatek,mt8195-topckgen", "syscon";
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