| /linux-6.3-rc2/drivers/clk/spear/ |
| A D | spear1310_clock.c | 376 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; variable
945 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, in spear1310_clk_init()
946 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
956 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, in spear1310_clk_init()
957 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
967 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, in spear1310_clk_init()
968 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
978 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, in spear1310_clk_init()
979 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
989 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, in spear1310_clk_init()
[all …]
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| A D | spear6xx_clock.c | 99 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; variable
166 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, in spear6xx_clk_init()
167 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear6xx_clk_init()
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| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt7986-topckgen.c | 84 static const char *const uart_parents[] __initconst = { "top_xtal", variable
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
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| A D | clk-mt7981-topckgen.c | 136 static const char * const uart_parents[] __initconst = { variable
303 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt6795-topckgen.c | 306 static const char * const uart_parents[] = { variable
466 TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),
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| A D | clk-mt7629.c | 163 static const char * const uart_parents[] = { variable
506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
512 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
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| A D | clk-mt8173-topckgen.c | 127 static const char * const uart_parents[] = { variable
545 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
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| A D | clk-mt8186-topckgen.c | 117 static const char * const uart_parents[] = { variable
530 uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
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| A D | clk-mt7622.c | 185 static const char * const uart_parents[] = { variable
536 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
542 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
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| A D | clk-mt8135.c | 226 static const char * const uart_parents[] __initconst = { variable
374 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
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| A D | clk-mt6797.c | 158 static const char * const uart_parents[] = { variable
340 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
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| A D | clk-mt8195-topckgen.c | 322 static const char * const uart_parents[] = { variable
923 uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
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| A D | clk-mt2701.c | 217 static const char * const uart_parents[] = { variable
506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt6779.c | 356 static const char * const uart_parents[] = { variable
686 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
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| A D | clk-mt2712.c | 314 static const char * const uart_parents[] = { variable
758 uart_parents, 0x060, 8, 1, 15),
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| A D | clk-mt6765.c | 221 static const char * const uart_parents[] = { variable
400 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| A D | clk-mt8183.c | 254 static const char * const uart_parents[] = { variable
497 uart_parents, 0x70,
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| A D | clk-mt8192.c | 265 static const char * const uart_parents[] = { variable
602 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
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| A D | clk-mt8365.c | 152 static const char * const uart_parents[] = { variable
437 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
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| /linux-6.3-rc2/drivers/clk/sprd/ |
| A D | sc9860-clk.c | 387 static const char * const uart_parents[] = { "ext-26m", "twpll-48m", variable
389 static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
391 static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
393 static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
395 static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
397 static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
611 static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
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| A D | ums512-clk.c | 788 static const struct clk_parent_data uart_parents[] = { variable
797 static SPRD_MUX_CLK_DATA(uart0_clk, "uart0-clk", uart_parents,
799 static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
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