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Searched refs:uvd (Results 1 – 22 of 22) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_uvd.c155 if (adev->uvd.address_64_bit) in amdgpu_uvd_create_msg_bo_helper()
339 adev->uvd.filp[i] = NULL; in amdgpu_uvd_sw_init()
352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; in amdgpu_uvd_sw_init()
355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; in amdgpu_uvd_sw_init()
358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; in amdgpu_uvd_sw_init()
361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; in amdgpu_uvd_sw_init()
409 ring = &adev->uvd.inst[0].ring; in amdgpu_uvd_entity_init()
500 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, in amdgpu_uvd_resume()
536 adev->uvd.filp[i] = NULL; in amdgpu_uvd_free_handles()
745 if (!adev->uvd.use_ctx_buf){ in amdgpu_uvd_cs_msg_decode()
[all …]
A Duvd_v7_0.c384 adev->uvd.num_uvd_inst = 1; in uvd_v7_0_early_init()
388 adev->uvd.num_enc_rings = 1; in uvd_v7_0_early_init()
390 adev->uvd.num_enc_rings = 2; in uvd_v7_0_early_init()
446 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_sw_init()
449 &adev->uvd.inst[j].irq, 0, in uvd_v7_0_sw_init()
470 &adev->uvd.inst[j].irq, 0, in uvd_v7_0_sw_init()
536 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_hw_init()
814 ring = &adev->uvd.inst[i].ring; in uvd_v7_0_sriov_start()
973 ring = &adev->uvd.inst[k].ring; in uvd_v7_0_start()
1873 adev->uvd.inst[i].ring.me = i; in uvd_v7_0_set_ring_funcs()
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A Duvd_v6_0.c67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); in uvd_v6_0_enc_support()
360 adev->uvd.num_uvd_inst = 1; in uvd_v6_0_early_init()
369 adev->uvd.num_enc_rings = 2; in uvd_v6_0_early_init()
406 adev->uvd.inst->irq.num_types = 1; in uvd_v6_0_sw_init()
407 adev->uvd.num_enc_rings = 0; in uvd_v6_0_sw_init()
412 ring = &adev->uvd.inst->ring; in uvd_v6_0_sw_init()
425 ring = &adev->uvd.inst->ring_enc[i]; in uvd_v6_0_sw_init()
428 &adev->uvd.inst->irq, 0, in uvd_v6_0_sw_init()
862 ring = &adev->uvd.inst->ring_enc[0]; in uvd_v6_0_start()
1655 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; in uvd_v6_0_set_irq_funcs()
[all …]
A Duvd_v3_1.c263 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v3_1_mc_resume()
267 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; in uvd_v3_1_mc_resume()
285 uint32_t keysel = adev->uvd.keyselect; in uvd_v3_1_fw_validate()
517 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v3_1_process_interrupt()
529 adev->uvd.inst->irq.num_types = 1; in uvd_v3_1_set_irq_funcs()
537 adev->uvd.num_uvd_inst = 1; in uvd_v3_1_early_init()
562 ring = &adev->uvd.inst->ring; in uvd_v3_1_sw_init()
574 ptr = adev->uvd.inst[0].cpu_addr; in uvd_v3_1_sw_init()
578 memcpy(&adev->uvd.keyselect, ptr, 4); in uvd_v3_1_sw_init()
701 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v3_1_hw_fini()
[all …]
A Duvd_v4_2.c96 adev->uvd.num_uvd_inst = 1; in uvd_v4_2_early_init()
119 ring = &adev->uvd.inst->ring; in uvd_v4_2_sw_init()
159 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_hw_init()
215 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v4_2_hw_fini()
239 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v4_2_suspend()
280 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_start()
592 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v4_2_mc_resume()
596 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; in uvd_v4_2_mc_resume()
703 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v4_2_process_interrupt()
802 adev->uvd.inst->irq.num_types = 1; in uvd_v4_2_set_irq_funcs()
[all …]
A Duvd_v5_0.c94 adev->uvd.num_uvd_inst = 1; in uvd_v5_0_early_init()
117 ring = &adev->uvd.inst->ring; in uvd_v5_0_sw_init()
155 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_init()
213 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v5_0_hw_fini()
237 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v5_0_suspend()
283 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
285 upper_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
317 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_start()
625 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v5_0_process_interrupt()
910 adev->uvd.inst->irq.num_types = 1; in uvd_v5_0_set_irq_funcs()
[all …]
A Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
A Damdgpu_kms.c213 fw_info->ver = adev->uvd.fw_version; in amdgpu_firmware_info()
401 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
402 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
405 if (adev->uvd.inst[i].ring.sched.ready) in amdgpu_hw_ip_info()
421 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
422 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
425 for (j = 0; j < adev->uvd.num_enc_rings; j++) in amdgpu_hw_ip_info()
426 if (adev->uvd.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
950 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
A Damdgpu_fence.c488 index = ALIGN(adev->uvd.fw->size, 8); in amdgpu_fence_driver_start_ring()
489 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; in amdgpu_fence_driver_start_ring()
490 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; in amdgpu_fence_driver_start_ring()
A Damdgpu_virt.c549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
A Damdgpu.h931 struct amdgpu_uvd uvd; member
A Damdgpu_ucode.c690 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dradeon_uvd.c191 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
205 &rdev->uvd.gpu_addr); in radeon_uvd_init()
213 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); in radeon_uvd_init()
223 rdev->uvd.filp[i] = NULL; in radeon_uvd_init()
224 rdev->uvd.img_size[i] = 0; in radeon_uvd_init()
234 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_fini()
255 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_suspend()
275 rdev->uvd.filp[i] = NULL; in radeon_uvd_suspend()
288 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_resume()
296 ptr = rdev->uvd.cpu_addr; in radeon_uvd_resume()
[all …]
A Duvd_v4_2.c46 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
74 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
A Duvd_v2_2.c113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
A Duvd_v1_0.c121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
145 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
A Dradeon_drv.c263 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
264 module_param_named(uvd, radeon_uvd, int, 0444);
A Dradeon_fence.c833 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; in radeon_fence_driver_start_ring()
834 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
A Dradeon.h2421 struct radeon_uvd uvd; member
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu10_hwmgr.h112 uint32_t uvd : 1; member
A Dsmu8_hwmgr.h135 uint32_t uvd : 1; member
A Dsmu8_hwmgr.c1996 adev->uvd.decode_image_width >= WIDTH_4K) in smu8_dpm_powergate_uvd()

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