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Searched refs:vgpu_vreg (Results 1 – 9 of 9) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dedid.c143 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in gmbus0_mmio_write()
186 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; in gmbus1_mmio_write()
239 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) in gmbus1_mmio_write()
273 vgpu_vreg(vgpu, offset) = wvalue; in gmbus1_mmio_write()
343 u32 value = vgpu_vreg(vgpu, offset); in gmbus2_mmio_read()
345 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE)) in gmbus2_mmio_read()
346 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE; in gmbus2_mmio_read()
357 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE; in gmbus2_mmio_write()
493 vgpu_vreg(vgpu, offset) = value; in intel_gvt_i2c_handle_aux_ch_write()
499 msg = vgpu_vreg(vgpu, offset + 4); in intel_gvt_i2c_handle_aux_ch_write()
[all …]
A Dinterrupt.c186 (vgpu_vreg(vgpu, reg) ^ imr)); in intel_vgpu_reg_imr_handler()
188 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler()
227 vgpu_vreg(vgpu, reg) |= ier; in intel_vgpu_reg_master_irq_handler()
257 (vgpu_vreg(vgpu, reg) ^ ier)); in intel_vgpu_reg_ier_handler()
259 vgpu_vreg(vgpu, reg) = ier; in intel_vgpu_reg_ier_handler()
300 vgpu_vreg(vgpu, reg) &= ~iir; in intel_vgpu_reg_iir_handler()
334 u32 val = vgpu_vreg(vgpu, in update_upstream_irq()
336 & vgpu_vreg(vgpu, in update_upstream_irq()
366 vgpu_vreg(vgpu, isr) &= ~clear_bits; in update_upstream_irq()
367 vgpu_vreg(vgpu, isr) |= set_bits; in update_upstream_irq()
[all …]
A Dhandlers.c278 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write()
301 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write()
350 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
1307 vgpu_vreg(vgpu, offset + in dp_aux_ch_ctl_mmio_write()
1577 vgpu_vreg(vgpu, offset) |= in power_well_ctl_mmio_write()
1580 vgpu_vreg(vgpu, offset) &= in power_well_ctl_mmio_write()
1668 vgpu_vreg(vgpu, offset) = v; in dpll_status_read()
1786 vgpu_vreg(vgpu, offset) = v; in skl_lcpll_write()
1799 vgpu_vreg(vgpu, offset) = v; in bxt_de_pll_enable_write()
1812 vgpu_vreg(vgpu, offset) = v; in bxt_port_pll_enable_write()
[all …]
A Dexeclist.c98 status.ldw = vgpu_vreg(vgpu, status_reg); in emulate_execlist_status()
99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status()
117 vgpu_vreg(vgpu, status_reg) = status.ldw; in emulate_execlist_status()
118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status()
139 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); in emulate_csb_update()
152 vgpu_vreg(vgpu, offset) = status->ldw; in emulate_csb_update()
153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update()
156 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; in emulate_csb_update()
262 status.ldw = vgpu_vreg(vgpu, status_reg); in get_next_execlist_slot()
263 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot()
[all …]
A Ddebugfs.c66 vreg = vgpu_vreg(param->vgpu, offset); in mmio_diff_handler()
A Ddisplay.c44 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe()
69 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
A Dscheduler.c274 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
278 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
282 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
A Dgvt.h466 #define vgpu_vreg(vgpu, offset) \ macro
A Dcmd_parser.c954 vreg = &vgpu_vreg(s->vgpu, offset); in cmd_reg_handler()
1026 vgpu_vreg(vgpu, offset) = data; in cmd_reg_handler()

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