1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
7
8 #include <asm/hyperv-tlfs.h>
9
10 /*
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
13 */
14
15 enum intercept_words {
16 INTERCEPT_CR = 0,
17 INTERCEPT_DR,
18 INTERCEPT_EXCEPTION,
19 INTERCEPT_WORD3,
20 INTERCEPT_WORD4,
21 INTERCEPT_WORD5,
22 MAX_INTERCEPT,
23 };
24
25 enum {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
37 INTERCEPT_DR1_READ,
38 INTERCEPT_DR2_READ,
39 INTERCEPT_DR3_READ,
40 INTERCEPT_DR4_READ,
41 INTERCEPT_DR5_READ,
42 INTERCEPT_DR6_READ,
43 INTERCEPT_DR7_READ,
44 INTERCEPT_DR0_WRITE = 48,
45 INTERCEPT_DR1_WRITE,
46 INTERCEPT_DR2_WRITE,
47 INTERCEPT_DR3_WRITE,
48 INTERCEPT_DR4_WRITE,
49 INTERCEPT_DR5_WRITE,
50 INTERCEPT_DR6_WRITE,
51 INTERCEPT_DR7_WRITE,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
55 INTERCEPT_INTR = 96,
56 INTERCEPT_NMI,
57 INTERCEPT_SMI,
58 INTERCEPT_INIT,
59 INTERCEPT_VINTR,
60 INTERCEPT_SELECTIVE_CR0,
61 INTERCEPT_STORE_IDTR,
62 INTERCEPT_STORE_GDTR,
63 INTERCEPT_STORE_LDTR,
64 INTERCEPT_STORE_TR,
65 INTERCEPT_LOAD_IDTR,
66 INTERCEPT_LOAD_GDTR,
67 INTERCEPT_LOAD_LDTR,
68 INTERCEPT_LOAD_TR,
69 INTERCEPT_RDTSC,
70 INTERCEPT_RDPMC,
71 INTERCEPT_PUSHF,
72 INTERCEPT_POPF,
73 INTERCEPT_CPUID,
74 INTERCEPT_RSM,
75 INTERCEPT_IRET,
76 INTERCEPT_INTn,
77 INTERCEPT_INVD,
78 INTERCEPT_PAUSE,
79 INTERCEPT_HLT,
80 INTERCEPT_INVLPG,
81 INTERCEPT_INVLPGA,
82 INTERCEPT_IOIO_PROT,
83 INTERCEPT_MSR_PROT,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
86 INTERCEPT_SHUTDOWN,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
89 INTERCEPT_VMMCALL,
90 INTERCEPT_VMLOAD,
91 INTERCEPT_VMSAVE,
92 INTERCEPT_STGI,
93 INTERCEPT_CLGI,
94 INTERCEPT_SKINIT,
95 INTERCEPT_RDTSCP,
96 INTERCEPT_ICEBP,
97 INTERCEPT_WBINVD,
98 INTERCEPT_MONITOR,
99 INTERCEPT_MWAIT,
100 INTERCEPT_MWAIT_COND,
101 INTERCEPT_XSETBV,
102 INTERCEPT_RDPRU,
103 TRAP_EFER_WRITE,
104 TRAP_CR0_WRITE,
105 TRAP_CR1_WRITE,
106 TRAP_CR2_WRITE,
107 TRAP_CR3_WRITE,
108 TRAP_CR4_WRITE,
109 TRAP_CR5_WRITE,
110 TRAP_CR6_WRITE,
111 TRAP_CR7_WRITE,
112 TRAP_CR8_WRITE,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
116 INTERCEPT_INVPCID,
117 INTERCEPT_MCOMMIT,
118 INTERCEPT_TLBSYNC,
119 };
120
121
122 struct __attribute__ ((__packed__)) vmcb_control_area {
123 u32 intercepts[MAX_INTERCEPT];
124 u32 reserved_1[15 - MAX_INTERCEPT];
125 u16 pause_filter_thresh;
126 u16 pause_filter_count;
127 u64 iopm_base_pa;
128 u64 msrpm_base_pa;
129 u64 tsc_offset;
130 u32 asid;
131 u8 tlb_ctl;
132 u8 reserved_2[3];
133 u32 int_ctl;
134 u32 int_vector;
135 u32 int_state;
136 u8 reserved_3[4];
137 u32 exit_code;
138 u32 exit_code_hi;
139 u64 exit_info_1;
140 u64 exit_info_2;
141 u32 exit_int_info;
142 u32 exit_int_info_err;
143 u64 nested_ctl;
144 u64 avic_vapic_bar;
145 u64 ghcb_gpa;
146 u32 event_inj;
147 u32 event_inj_err;
148 u64 nested_cr3;
149 u64 virt_ext;
150 u32 clean;
151 u32 reserved_5;
152 u64 next_rip;
153 u8 insn_len;
154 u8 insn_bytes[15];
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
159 u8 reserved_7[8];
160 u64 vmsa_pa; /* Used for an SEV-ES guest */
161 u8 reserved_8[720];
162 /*
163 * Offset 0x3e0, 32 bytes reserved
164 * for use by hypervisor/software.
165 */
166 union {
167 struct hv_vmcb_enlightenments hv_enlightenments;
168 u8 reserved_sw[32];
169 };
170 };
171
172
173 #define TLB_CONTROL_DO_NOTHING 0
174 #define TLB_CONTROL_FLUSH_ALL_ASID 1
175 #define TLB_CONTROL_FLUSH_ASID 3
176 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
177
178 #define V_TPR_MASK 0x0f
179
180 #define V_IRQ_SHIFT 8
181 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
182
183 #define V_GIF_SHIFT 9
184 #define V_GIF_MASK (1 << V_GIF_SHIFT)
185
186 #define V_INTR_PRIO_SHIFT 16
187 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
188
189 #define V_IGN_TPR_SHIFT 20
190 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
191
192 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
193
194 #define V_INTR_MASKING_SHIFT 24
195 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
196
197 #define V_GIF_ENABLE_SHIFT 25
198 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
199
200 #define AVIC_ENABLE_SHIFT 31
201 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
202
203 #define X2APIC_MODE_SHIFT 30
204 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
205
206 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
207 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
208
209 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
210 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
211
212 #define SVM_IOIO_STR_SHIFT 2
213 #define SVM_IOIO_REP_SHIFT 3
214 #define SVM_IOIO_SIZE_SHIFT 4
215 #define SVM_IOIO_ASIZE_SHIFT 7
216
217 #define SVM_IOIO_TYPE_MASK 1
218 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
219 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
220 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
221 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
222
223 #define SVM_VM_CR_VALID_MASK 0x001fULL
224 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
225 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
226
227 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
228 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
229 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
230
231
232 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
233 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
234 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
235 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
236
237
238 /* AVIC */
239 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
240 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
241 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
242
243 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
244 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
245 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
246 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
247 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
248
249 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
250
251 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
252
253 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
254 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
255 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
256
257 enum avic_ipi_failure_cause {
258 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
259 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
260 AVIC_IPI_FAILURE_INVALID_TARGET,
261 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
262 };
263
264 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(9, 0)
265
266 /*
267 * For AVIC, the max index allowed for physical APIC ID
268 * table is 0xff (255).
269 */
270 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
271
272 /*
273 * For x2AVIC, the max index allowed for physical APIC ID
274 * table is 0x1ff (511).
275 */
276 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
277
278 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
279 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
280
281
282 struct vmcb_seg {
283 u16 selector;
284 u16 attrib;
285 u32 limit;
286 u64 base;
287 } __packed;
288
289 /* Save area definition for legacy and SEV-MEM guests */
290 struct vmcb_save_area {
291 struct vmcb_seg es;
292 struct vmcb_seg cs;
293 struct vmcb_seg ss;
294 struct vmcb_seg ds;
295 struct vmcb_seg fs;
296 struct vmcb_seg gs;
297 struct vmcb_seg gdtr;
298 struct vmcb_seg ldtr;
299 struct vmcb_seg idtr;
300 struct vmcb_seg tr;
301 /* Reserved fields are named following their struct offset */
302 u8 reserved_0xa0[42];
303 u8 vmpl;
304 u8 cpl;
305 u8 reserved_0xcc[4];
306 u64 efer;
307 u8 reserved_0xd8[112];
308 u64 cr4;
309 u64 cr3;
310 u64 cr0;
311 u64 dr7;
312 u64 dr6;
313 u64 rflags;
314 u64 rip;
315 u8 reserved_0x180[88];
316 u64 rsp;
317 u64 s_cet;
318 u64 ssp;
319 u64 isst_addr;
320 u64 rax;
321 u64 star;
322 u64 lstar;
323 u64 cstar;
324 u64 sfmask;
325 u64 kernel_gs_base;
326 u64 sysenter_cs;
327 u64 sysenter_esp;
328 u64 sysenter_eip;
329 u64 cr2;
330 u8 reserved_0x248[32];
331 u64 g_pat;
332 u64 dbgctl;
333 u64 br_from;
334 u64 br_to;
335 u64 last_excp_from;
336 u64 last_excp_to;
337 u8 reserved_0x298[72];
338 u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
339 } __packed;
340
341 /* Save area definition for SEV-ES and SEV-SNP guests */
342 struct sev_es_save_area {
343 struct vmcb_seg es;
344 struct vmcb_seg cs;
345 struct vmcb_seg ss;
346 struct vmcb_seg ds;
347 struct vmcb_seg fs;
348 struct vmcb_seg gs;
349 struct vmcb_seg gdtr;
350 struct vmcb_seg ldtr;
351 struct vmcb_seg idtr;
352 struct vmcb_seg tr;
353 u64 vmpl0_ssp;
354 u64 vmpl1_ssp;
355 u64 vmpl2_ssp;
356 u64 vmpl3_ssp;
357 u64 u_cet;
358 u8 reserved_0xc8[2];
359 u8 vmpl;
360 u8 cpl;
361 u8 reserved_0xcc[4];
362 u64 efer;
363 u8 reserved_0xd8[104];
364 u64 xss;
365 u64 cr4;
366 u64 cr3;
367 u64 cr0;
368 u64 dr7;
369 u64 dr6;
370 u64 rflags;
371 u64 rip;
372 u64 dr0;
373 u64 dr1;
374 u64 dr2;
375 u64 dr3;
376 u64 dr0_addr_mask;
377 u64 dr1_addr_mask;
378 u64 dr2_addr_mask;
379 u64 dr3_addr_mask;
380 u8 reserved_0x1c0[24];
381 u64 rsp;
382 u64 s_cet;
383 u64 ssp;
384 u64 isst_addr;
385 u64 rax;
386 u64 star;
387 u64 lstar;
388 u64 cstar;
389 u64 sfmask;
390 u64 kernel_gs_base;
391 u64 sysenter_cs;
392 u64 sysenter_esp;
393 u64 sysenter_eip;
394 u64 cr2;
395 u8 reserved_0x248[32];
396 u64 g_pat;
397 u64 dbgctl;
398 u64 br_from;
399 u64 br_to;
400 u64 last_excp_from;
401 u64 last_excp_to;
402 u8 reserved_0x298[80];
403 u32 pkru;
404 u32 tsc_aux;
405 u8 reserved_0x2f0[24];
406 u64 rcx;
407 u64 rdx;
408 u64 rbx;
409 u64 reserved_0x320; /* rsp already available at 0x01d8 */
410 u64 rbp;
411 u64 rsi;
412 u64 rdi;
413 u64 r8;
414 u64 r9;
415 u64 r10;
416 u64 r11;
417 u64 r12;
418 u64 r13;
419 u64 r14;
420 u64 r15;
421 u8 reserved_0x380[16];
422 u64 guest_exit_info_1;
423 u64 guest_exit_info_2;
424 u64 guest_exit_int_info;
425 u64 guest_nrip;
426 u64 sev_features;
427 u64 vintr_ctrl;
428 u64 guest_exit_code;
429 u64 virtual_tom;
430 u64 tlb_id;
431 u64 pcpu_id;
432 u64 event_inj;
433 u64 xcr0;
434 u8 reserved_0x3f0[16];
435
436 /* Floating point area */
437 u64 x87_dp;
438 u32 mxcsr;
439 u16 x87_ftw;
440 u16 x87_fsw;
441 u16 x87_fcw;
442 u16 x87_fop;
443 u16 x87_ds;
444 u16 x87_cs;
445 u64 x87_rip;
446 u8 fpreg_x87[80];
447 u8 fpreg_xmm[256];
448 u8 fpreg_ymm[256];
449 } __packed;
450
451 struct ghcb_save_area {
452 u8 reserved_0x0[203];
453 u8 cpl;
454 u8 reserved_0xcc[116];
455 u64 xss;
456 u8 reserved_0x148[24];
457 u64 dr7;
458 u8 reserved_0x168[16];
459 u64 rip;
460 u8 reserved_0x180[88];
461 u64 rsp;
462 u8 reserved_0x1e0[24];
463 u64 rax;
464 u8 reserved_0x200[264];
465 u64 rcx;
466 u64 rdx;
467 u64 rbx;
468 u8 reserved_0x320[8];
469 u64 rbp;
470 u64 rsi;
471 u64 rdi;
472 u64 r8;
473 u64 r9;
474 u64 r10;
475 u64 r11;
476 u64 r12;
477 u64 r13;
478 u64 r14;
479 u64 r15;
480 u8 reserved_0x380[16];
481 u64 sw_exit_code;
482 u64 sw_exit_info_1;
483 u64 sw_exit_info_2;
484 u64 sw_scratch;
485 u8 reserved_0x3b0[56];
486 u64 xcr0;
487 u8 valid_bitmap[16];
488 u64 x87_state_gpa;
489 } __packed;
490
491 #define GHCB_SHARED_BUF_SIZE 2032
492
493 struct ghcb {
494 struct ghcb_save_area save;
495 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
496
497 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
498
499 u8 reserved_0xff0[10];
500 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
501 u32 ghcb_usage;
502 } __packed;
503
504
505 #define EXPECTED_VMCB_SAVE_AREA_SIZE 740
506 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
507 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
508 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
509 #define EXPECTED_GHCB_SIZE PAGE_SIZE
510
511 #define BUILD_BUG_RESERVED_OFFSET(x, y) \
512 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
513
__unused_size_checks(void)514 static inline void __unused_size_checks(void)
515 {
516 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
517 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
518 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
519 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
520 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
521
522 /* Check offsets of reserved fields */
523
524 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
525 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
526 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
527 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
528 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
529 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
530
531 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
532 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
533 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
534 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
535 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
536 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
537 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x2f0);
538 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
539 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
540 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
541
542 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
543 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
544 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
545 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
546 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
547 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
548 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
549 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
550 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
551 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
552
553 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
554 }
555
556 struct vmcb {
557 struct vmcb_control_area control;
558 struct vmcb_save_area save;
559 } __packed;
560
561 #define SVM_CPUID_FUNC 0x8000000a
562
563 #define SVM_VM_CR_SVM_DISABLE 4
564
565 #define SVM_SELECTOR_S_SHIFT 4
566 #define SVM_SELECTOR_DPL_SHIFT 5
567 #define SVM_SELECTOR_P_SHIFT 7
568 #define SVM_SELECTOR_AVL_SHIFT 8
569 #define SVM_SELECTOR_L_SHIFT 9
570 #define SVM_SELECTOR_DB_SHIFT 10
571 #define SVM_SELECTOR_G_SHIFT 11
572
573 #define SVM_SELECTOR_TYPE_MASK (0xf)
574 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
575 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
576 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
577 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
578 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
579 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
580 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
581
582 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
583 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
584 #define SVM_SELECTOR_CODE_MASK (1 << 3)
585
586 #define SVM_EVTINJ_VEC_MASK 0xff
587
588 #define SVM_EVTINJ_TYPE_SHIFT 8
589 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
590
591 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
592 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
593 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
594 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
595
596 #define SVM_EVTINJ_VALID (1 << 31)
597 #define SVM_EVTINJ_VALID_ERR (1 << 11)
598
599 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
600 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
601
602 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
603 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
604 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
605 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
606
607 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
608 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
609
610 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
611 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
612 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
613
614 #define SVM_EXITINFO_REG_MASK 0x0F
615
616 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
617
618 /* GHCB Accessor functions */
619
620 #define GHCB_BITMAP_IDX(field) \
621 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
622
623 #define DEFINE_GHCB_ACCESSORS(field) \
624 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
625 { \
626 return test_bit(GHCB_BITMAP_IDX(field), \
627 (unsigned long *)&ghcb->save.valid_bitmap); \
628 } \
629 \
630 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
631 { \
632 return ghcb->save.field; \
633 } \
634 \
635 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
636 { \
637 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
638 } \
639 \
640 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
641 { \
642 __set_bit(GHCB_BITMAP_IDX(field), \
643 (unsigned long *)&ghcb->save.valid_bitmap); \
644 ghcb->save.field = value; \
645 }
646
647 DEFINE_GHCB_ACCESSORS(cpl)
648 DEFINE_GHCB_ACCESSORS(rip)
649 DEFINE_GHCB_ACCESSORS(rsp)
650 DEFINE_GHCB_ACCESSORS(rax)
651 DEFINE_GHCB_ACCESSORS(rcx)
652 DEFINE_GHCB_ACCESSORS(rdx)
653 DEFINE_GHCB_ACCESSORS(rbx)
654 DEFINE_GHCB_ACCESSORS(rbp)
655 DEFINE_GHCB_ACCESSORS(rsi)
656 DEFINE_GHCB_ACCESSORS(rdi)
657 DEFINE_GHCB_ACCESSORS(r8)
658 DEFINE_GHCB_ACCESSORS(r9)
659 DEFINE_GHCB_ACCESSORS(r10)
660 DEFINE_GHCB_ACCESSORS(r11)
661 DEFINE_GHCB_ACCESSORS(r12)
662 DEFINE_GHCB_ACCESSORS(r13)
663 DEFINE_GHCB_ACCESSORS(r14)
664 DEFINE_GHCB_ACCESSORS(r15)
665 DEFINE_GHCB_ACCESSORS(sw_exit_code)
666 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
667 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
668 DEFINE_GHCB_ACCESSORS(sw_scratch)
669 DEFINE_GHCB_ACCESSORS(xcr0)
670
671 #endif
672