| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
421 int vlevel, vlevel_max; in dcn301_calculate_wm_and_dlg_fp() local
433 vlevel = 0; in dcn301_calculate_wm_and_dlg_fp()
435 vlevel = vlevel_max; in dcn301_calculate_wm_and_dlg_fp()
440 vlevel = min(max(vlevel_req, 2), vlevel_max); in dcn301_calculate_wm_and_dlg_fp()
445 vlevel = min(max(vlevel_req, 1), vlevel_max); in dcn301_calculate_wm_and_dlg_fp()
451 vlevel = min(vlevel_req, vlevel_max); in dcn301_calculate_wm_and_dlg_fp()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 257 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
1038 int vlevel) in subvp_validate_static_schedulability() argument
1089 int *vlevel, in dcn32_full_validate_bw_helper() argument
1121 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); in dcn32_full_validate_bw_helper()
1186 *vlevel = i; in dcn32_full_validate_bw_helper()
1219 *vlevel = i; in dcn32_full_validate_bw_helper()
1656 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn32_internal_validate_bw()
1864 int flag_vlevel = vlevel; in dcn32_internal_validate_bw()
1888 vlevel = i; in dcn32_internal_validate_bw()
1898 *vlevel_out = vlevel; in dcn32_internal_validate_bw()
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| A D | dcn32_fpu.h | 64 int vlevel);
72 int vlevel);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
71 int vlevel,
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| A D | dcn20_fpu.c | 1043 int vlevel) in dcn20_calculate_dlg_params() argument
1622 int vlevel, in dcn20_calculate_wm() argument
1678 pipes[0].clks_cfg.voltage = vlevel; in dcn20_calculate_wm()
1683 if (vlevel < 1) { in dcn20_calculate_wm()
1697 if (vlevel < 2) { in dcn20_calculate_wm()
1710 if (vlevel < 3) { in dcn20_calculate_wm()
1910 int vlevel = 0; in dcn20_validate_bandwidth_internal() local
2121 int vlevel, vlevel_max; in dcn21_calculate_wm() local
2174 vlevel = 0; in dcn21_calculate_wm()
2176 vlevel = vlevel_max; in dcn21_calculate_wm()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.h | 50 int vlevel);
70 int vlevel);
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| A D | dcn30_fpu.c | 381 int vlevel) in dcn30_fpu_calculate_wm_and_dlg() argument
385 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
386 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
393 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
395 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
402 if (vlevel == 0) { in dcn30_fpu_calculate_wm_and_dlg()
419 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
452 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == … in dcn30_fpu_calculate_wm_and_dlg()
523 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
627 int vlevel) in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() argument
[all …]
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.h | 73 int vlevel);
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| A D | dcn30_resource.c | 1659 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1689 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1690 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1693 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1706 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1709 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1715 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1888 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
1889 *vlevel_out = vlevel; in dcn30_internal_validate_bw()
2045 int vlevel) in dcn30_calculate_wm_and_dlg() argument
[all …]
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 1854 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1917 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1918 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1919 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1922 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1923 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
2036 return vlevel; in dcn20_validate_apply_pipe_split_flags()
2050 int pipe_cnt, i, pipe_idx, vlevel; in dcn20_fast_validate_bw() local
2071 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2074 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); in dcn20_fast_validate_bw()
[all …]
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| A D | dcn20_resource.h | 126 int vlevel,
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.h | 44 int vlevel);
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| A D | dcn31_fpu.c | 484 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
503 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
505 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
552 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.h | 47 int vlevel);
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| A D | dcn31_resource.c | 1754 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1757 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1790 int vlevel = 0; in dcn31_validate_bandwidth() local
1798 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true); in dcn31_validate_bandwidth()
1815 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 819 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
844 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
846 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
856 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
857 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
861 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); in dcn21_fast_validate_bw()
920 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
951 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /linux-6.3-rc2/arch/arm64/kvm/ |
| A D | arch_timer.c | 664 bool vlevel, plevel; in kvm_timer_should_notify_user() local
669 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
672 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 88 int vlevel);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/ |
| A D | dcn32_resource.c | 1837 int vlevel = 0; in dcn32_validate_bandwidth() local
1867 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dcn32_validate_bandwidth()
1886 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn32_validate_bandwidth()
2035 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2038 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| A D | dcn32_resource.h | 98 int vlevel);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/ |
| A D | dcn314_resource.c | 1708 int vlevel = 0; in dcn314_validate_bandwidth() local
1717 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); in dcn314_validate_bandwidth()
1734 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1393 int vlevel) in dcn301_calculate_wm_and_dlg() argument
1396 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn301_calculate_wm_and_dlg()
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