1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_SUBVP_STATE_H 27 #define DMUB_SUBVP_STATE_H 28 29 #include "dmub_cmd.h" 30 31 #define DMUB_SUBVP_INST0 0 32 #define DMUB_SUBVP_INST1 1 33 #define SUBVP_MAX_WATERMARK 0xFFFF 34 35 struct dmub_subvp_hubp_state { 36 uint32_t CURSOR0_0_CURSOR_POSITION; 37 uint32_t CURSOR0_0_CURSOR_HOT_SPOT; 38 uint32_t CURSOR0_0_CURSOR_DST_OFFSET; 39 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 40 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 41 uint32_t CURSOR0_0_CURSOR_SIZE; 42 uint32_t CURSOR0_0_CURSOR_CONTROL; 43 uint32_t HUBPREQ0_CURSOR_SETTINGS; 44 uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH; 45 uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE; 46 uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 47 uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS; 48 uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS; 49 uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; 50 uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 51 uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C; 52 uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; 53 uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; 54 }; 55 56 enum subvp_error_code { 57 DMUB_SUBVP_INVALID_STATE, 58 DMUB_SUBVP_INVALID_TRANSITION, 59 }; 60 61 enum subvp_state { 62 DMUB_SUBVP_DISABLED, 63 DMUB_SUBVP_IDLE, 64 DMUB_SUBVP_TRY_ACQUIRE_LOCKS, 65 DMUB_SUBVP_WAIT_FOR_LOCKS, 66 DMUB_SUBVP_PRECONFIGURE, 67 DMUB_SUBVP_PREPARE, 68 DMUB_SUBVP_ENABLE, 69 DMUB_SUBVP_SWITCHING, 70 DMUB_SUBVP_END, 71 DMUB_SUBVP_RESTORE, 72 }; 73 74 /* Defines information for SUBVP to handle vertical interrupts. */ 75 struct dmub_subvp_vertical_interrupt_event { 76 /** 77 * @inst: Hardware instance of vertical interrupt. 78 */ 79 uint8_t otg_inst; 80 81 /** 82 * @pad: Align structure to 4 byte boundary. 83 */ 84 uint8_t pad[3]; 85 86 enum subvp_state curr_state; 87 }; 88 89 struct dmub_subvp_vertical_interrupt_state { 90 /** 91 * @events: Event list. 92 */ 93 struct dmub_subvp_vertical_interrupt_event events[DMUB_MAX_STREAMS]; 94 }; 95 96 struct dmub_subvp_vline_interrupt_event { 97 98 uint8_t hubp_inst; 99 uint8_t pad[3]; 100 }; 101 102 struct dmub_subvp_vline_interrupt_state { 103 struct dmub_subvp_vline_interrupt_event events[DMUB_MAX_PLANES]; 104 }; 105 106 struct dmub_subvp_interrupt_ctx { 107 struct dmub_subvp_vertical_interrupt_state vertical_int; 108 struct dmub_subvp_vline_interrupt_state vline_int; 109 }; 110 111 struct dmub_subvp_pipe_state { 112 uint32_t pix_clk_100hz; 113 uint16_t main_vblank_start; 114 uint16_t main_vblank_end; 115 uint16_t mall_region_lines; 116 uint16_t prefetch_lines; 117 uint16_t prefetch_to_mall_start_lines; 118 uint16_t processing_delay_lines; 119 uint8_t main_pipe_index; 120 uint8_t phantom_pipe_index; 121 uint16_t htotal; // htotal for main / phantom pipe 122 uint16_t vtotal; 123 uint16_t optc_underflow_count; 124 uint16_t hubp_underflow_count; 125 uint8_t pad[2]; 126 }; 127 128 /** 129 * struct dmub_subvp_vblank_drr_info - Store DRR state when handling 130 * SubVP + VBLANK with DRR multi-display case. 131 * 132 * The info stored in this struct is only valid if drr_in_use = 1. 133 */ 134 struct dmub_subvp_vblank_drr_info { 135 uint8_t drr_in_use; 136 uint8_t drr_window_size_ms; // DRR window size -- indicates largest VMIN/VMAX adjustment per frame 137 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 138 uint16_t max_vtotal_supported; // Max VTOTAL that can still support SubVP static scheduling requirements 139 uint16_t prev_vmin; // Store VMIN value before MCLK switch (used to restore after MCLK end) 140 uint16_t prev_vmax; // Store VMAX value before MCLK switch (used to restore after MCLK end) 141 uint8_t use_ramping; // Use ramping or not 142 uint8_t pad[1]; 143 }; 144 145 struct dmub_subvp_vblank_pipe_info { 146 uint32_t pix_clk_100hz; 147 uint16_t vblank_start; 148 uint16_t vblank_end; 149 uint16_t vstartup_start; 150 uint16_t vtotal; 151 uint16_t htotal; 152 uint8_t pipe_index; 153 uint8_t pad[1]; 154 struct dmub_subvp_vblank_drr_info drr_info; // DRR considered as part of SubVP + VBLANK case 155 }; 156 157 enum subvp_switch_type { 158 DMUB_SUBVP_ONLY, // Used for SubVP only, and SubVP + VACTIVE 159 DMUB_SUBVP_AND_SUBVP, // 2 SubVP displays 160 DMUB_SUBVP_AND_VBLANK, 161 DMUB_SUBVP_AND_FPO, 162 }; 163 164 /* SubVP state. */ 165 struct dmub_subvp_state { 166 struct dmub_subvp_pipe_state pipe_state[DMUB_MAX_SUBVP_STREAMS]; 167 struct dmub_subvp_interrupt_ctx int_ctx; 168 struct dmub_subvp_vblank_pipe_info vblank_info; 169 enum subvp_state state; // current state 170 enum subvp_switch_type switch_type; // enum take up 4 bytes (?) 171 uint8_t mclk_pending; 172 uint8_t num_subvp_streams; 173 uint8_t vertical_int_margin_us; 174 uint8_t pstate_allow_width_us; 175 uint32_t subvp_mclk_switch_count; 176 uint32_t subvp_wait_lock_count; 177 uint32_t driver_wait_lock_count; 178 uint32_t subvp_vblank_frame_count; 179 uint16_t watermark_a_cache; 180 uint8_t pad[2]; 181 }; 182 183 #endif /* _DMUB_SUBVP_STATE_H_ */ 184