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Searched refs:vlv_dpio_read (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_dpio_phy.c718 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
732 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
738 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
809 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
825 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
873 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable()
881 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable()
891 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable()
914 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable()
1026 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable()
[all …]
A Dintel_dpll.c1606 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
1611 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
1616 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
1620 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
1653 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
1705 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
1798 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
1806 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
1846 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll()
1863 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in _chv_enable_pll()
[all …]
A Dintel_display_power_well.c1439 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1445 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1454 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1529 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
A Dintel_display.c3096 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
3124 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get()
3125 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
3126 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get()
3127 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get()
3128 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_crtc_clock_get()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Dvlv_sideband.h78 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
A Dvlv_sideband.c230 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg) in vlv_dpio_read() function

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