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Searched refs:wptr (Results 1 – 25 of 120) sorted by relevance

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/linux-6.3-rc2/drivers/media/usb/pvrusb2/
A Dpvrusb2-debugifc.c55 const char *wptr; in debugifc_isolate_word() local
60 wptr = NULL; in debugifc_isolate_word()
68 wptr = buf; in debugifc_isolate_word()
73 *wstrPtr = wptr; in debugifc_isolate_word()
182 const char *wptr; in pvr2_debugifc_do1cmd() local
189 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
196 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
223 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
226 if (scnt && wptr) { in pvr2_debugifc_do1cmd()
256 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
[all …]
/linux-6.3-rc2/drivers/media/platform/amphion/
A Dvpu_rpc.c41 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space()
45 ptr2 = desc->wptr; in vpu_rpc_check_buffer_space()
63 u32 wptr; in vpu_rpc_send_cmd_buf() local
72 wptr = desc->wptr; in vpu_rpc_send_cmd_buf()
78 wptr += 4; in vpu_rpc_send_cmd_buf()
80 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
81 wptr = desc->start; in vpu_rpc_send_cmd_buf()
87 wptr += 4; in vpu_rpc_send_cmd_buf()
89 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
90 wptr = desc->start; in vpu_rpc_send_cmd_buf()
[all …]
A Dvpu_malone.c187 u32 wptr; member
516 desc->wptr = readl(&str_buf->wptr); in vpu_malone_get_stream_buffer_desc()
529 writel(wptr, &str_buf->wptr); in vpu_malone_update_wptr()
1041 wptr = readl(&str_buf->wptr); in vpu_malone_add_padding_scode()
1046 size = ALIGN(wptr, 4) - wptr; in vpu_malone_add_padding_scode()
1479 u32 wptr = readl(&str_buf->wptr); in vpu_malone_input_frame_data() local
1486 scode.wptr = wptr; in vpu_malone_input_frame_data()
1494 wptr = scode.wptr; in vpu_malone_input_frame_data()
1504 wptr = scode.wptr; in vpu_malone_input_frame_data()
1533 u32 wptr = readl(&str_buf->wptr); in vpu_malone_input_stream_data() local
[all …]
A Dvpu_helpers.c283 offset = *wptr; in vpu_helper_copy_to_stream_buffer()
303 u32 *wptr, u8 val, u32 size) in vpu_helper_memset_stream_buffer() argument
310 if (!stream_buffer || !wptr) in vpu_helper_memset_stream_buffer()
316 offset = *wptr; in vpu_helper_memset_stream_buffer()
334 *wptr = offset; in vpu_helper_memset_stream_buffer()
346 if (desc.rptr > desc.wptr) in vpu_helper_get_free_space()
347 return desc.rptr - desc.wptr; in vpu_helper_get_free_space()
348 else if (desc.rptr < desc.wptr) in vpu_helper_get_free_space()
361 if (desc.wptr > desc.rptr) in vpu_helper_get_used_space()
362 return desc.wptr - desc.rptr; in vpu_helper_get_used_space()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.c151 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write() local
155 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
157 wptr <<= 2; in amdgpu_ih_ring_write()
158 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
161 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
163 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
207 u32 wptr; in amdgpu_ih_process() local
212 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
221 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
230 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
[all …]
A Dcz_ih.c193 u32 wptr, tmp; in cz_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
221 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
A Diceland_ih.c193 u32 wptr, tmp; in iceland_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
220 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
A Dtonga_ih.c195 u32 wptr, tmp; in tonga_ih_get_wptr() local
197 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
208 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
223 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
A Dsi_ih.c110 u32 wptr, tmp; in si_ih_get_wptr() local
112 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
114 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
115 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
123 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
A Dcik_ih.c191 u32 wptr, tmp; in cik_ih_get_wptr() local
193 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
195 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
196 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
208 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
A Damdgpu_ring_mux.c204 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) in amdgpu_ring_mux_set_wptr() argument
230 e->sw_wptr = wptr; in amdgpu_ring_mux_set_wptr()
231 e->start_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
234 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) { in amdgpu_ring_mux_set_wptr()
235 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr); in amdgpu_ring_mux_set_wptr()
236 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
239 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
331 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx()
431 chunk->start = ring->wptr; in amdgpu_ring_mux_start_ib()
474 chunk->end = ring->wptr; in amdgpu_ring_mux_end_ib()
A Dsdma_v5_0.c311 u64 wptr; in sdma_v5_0_ring_get_wptr() local
319 wptr = wptr << 32; in sdma_v5_0_ring_get_wptr()
324 return wptr >> 2; in sdma_v5_0_ring_get_wptr()
352 ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
353 *wptr_saved = ring->wptr << 2; in sdma_v5_0_ring_set_wptr()
366 ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
375 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
379 ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
388 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
393 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
[all …]
A Dsdma_v6_0.c137 u64 wptr = 0; in sdma_v6_0_ring_get_wptr() local
145 return wptr >> 2; in sdma_v6_0_ring_get_wptr()
174 ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
175 *wptr_saved = ring->wptr << 2; in sdma_v6_0_ring_set_wptr()
188 ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
197 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
201 ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
210 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
215 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
218 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
[all …]
A Dih_v6_0.c393 u32 wptr, tmp; in ih_v6_0_get_wptr() local
396 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_0_get_wptr()
399 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
402 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
403 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
405 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in ih_v6_0_get_wptr()
411 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_0_get_wptr()
414 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
421 return (wptr & ih->ptr_mask); in ih_v6_0_get_wptr()
487 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_0_self_irq() local
[all …]
A Dvega10_ih.c338 u32 wptr, tmp; in vega10_ih_get_wptr() local
347 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
349 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
357 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
360 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
366 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
369 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
377 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
A Dvcn_v2_0.c921 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1079 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1237 ring->wptr = 0; in vcn_v2_0_pause_dpg_mode()
1247 ring->wptr = 0; in vcn_v2_0_pause_dpg_mode()
1361 lower_32_bits(ring->wptr) | 0x80000000); in vcn_v2_0_dec_ring_set_wptr()
1364 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1416 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v2_0_dec_ring_insert_nop()
1819 adev->vcn.inst->ring_dec.wptr = 0; in vcn_v2_0_start_mmsch()
1824 adev->vcn.inst->ring_enc[i].wptr = 0; in vcn_v2_0_start_mmsch()
1951 ring->wptr = 0; in vcn_v2_0_start_sriov()
[all …]
A Dvcn_v3_0.c315 ring->wptr = 0; in vcn_v3_0_hw_init()
328 ring->wptr = 0; in vcn_v3_0_hw_init()
1078 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
1082 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start_dpg_mode()
1254 lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1255 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start()
1393 ring->wptr = 0; in vcn_v3_0_start_sriov()
1407 ring->wptr = 0; in vcn_v3_0_start_sriov()
1636 ring->wptr = 0; in vcn_v3_0_pause_dpg_mode()
1646 ring->wptr = 0; in vcn_v3_0_pause_dpg_mode()
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/linux-6.3-rc2/drivers/net/ppp/
A Dbsd_comp.c586 if (wptr) \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
893 wptr = obuf; in bsd_decompress()
894 *wptr++ = adrs; in bsd_decompress()
895 *wptr++ = ctrl; in bsd_decompress()
896 *wptr++ = 0; in bsd_decompress()
994 wptr += codelen; in bsd_decompress()
[all …]
A Dppp_deflate.c190 unsigned char *wptr; in z_compress() local
204 wptr = obuf; in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
211 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
212 wptr += PPP_HDRLEN; in z_compress()
213 put_unaligned_be16(state->seqno, wptr); in z_compress()
214 wptr += DEFLATE_OVHD; in z_compress()
216 state->strm.next_out = wptr; in z_compress()
/linux-6.3-rc2/drivers/net/ethernet/tehuti/
A Dtehuti.c171 f->wptr = 0; in bdx_fifo_init()
1112 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1167 f->m.wptr = delta; in bdx_recycle_skb()
1210 size = f->m.wptr - f->m.rptr; in bdx_rx_receive()
1427 d->wptr = d->start; in bdx_tx_db_init()
1505 db->wptr->addr.skb = skb; in bdx_tx_map_skb()
1568 fsize = f->m.rptr - f->m.wptr; in bdx_tx_space()
1639 len = f->m.wptr - f->m.memsz; in bdx_tx_transmit()
1641 f->m.wptr = len; in bdx_tx_transmit()
1806 f->m.wptr += size; in bdx_tx_push_desc()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dradeon_ring.c87 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
128 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
176 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
214 ring->wptr = ring->wptr_old; in radeon_ring_undo()
314 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
470 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
476 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show()
478 wptr, wptr); in radeon_debugfs_ring_info_show()
492 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/linux-6.3-rc2/drivers/gpu/drm/amd/amdkfd/
A Dkfd_kernel_queue.c233 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
243 wptr = kq->pending_wptr; in kq_acquire_packet_buffer()
249 pr_debug("wptr: %d\n", wptr); in kq_acquire_packet_buffer()
252 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
263 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in kq_acquire_packet_buffer()
271 while (wptr > 0) { in kq_acquire_packet_buffer()
272 queue_address[wptr] = kq->nop_packet; in kq_acquire_packet_buffer()
273 wptr = (wptr + 1) % queue_size_dwords; in kq_acquire_packet_buffer()
278 *buffer_ptr = &queue_address[wptr]; in kq_acquire_packet_buffer()
279 kq->pending_wptr = wptr + packet_size_in_dwords; in kq_acquire_packet_buffer()
/linux-6.3-rc2/drivers/crypto/ccp/
A Dtee-dev.c124 tee->rb_mgr.wptr = 0; in tee_init_ring()
259 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd()
266 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
271 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
281 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
284 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
307 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd()
308 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd()
309 tee->rb_mgr.wptr = 0; in tee_submit_cmd()
312 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
/linux-6.3-rc2/drivers/video/fbdev/
A Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()

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