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/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
[all …]
A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
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A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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A Dr300d.h84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
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A Dr600d.h111 # define CB_FORMAT(x) ((x) << 2) argument
382 #define S0_X(x) ((x) << 0) argument
383 #define S0_Y(x) ((x) << 4) argument
384 #define S1_X(x) ((x) << 8) argument
385 #define S1_Y(x) ((x) << 12) argument
386 #define S2_X(x) ((x) << 16) argument
387 #define S2_Y(x) ((x) << 20) argument
388 #define S3_X(x) ((x) << 24) argument
390 #define S4_X(x) ((x) << 0) argument
391 #define S4_Y(x) ((x) << 4) argument
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A Dr520d.h37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
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A Drs400d.h33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
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A Devergreend.h53 #define HOST_SMC_MSG(x) ((x) << 0) argument
56 #define HOST_SMC_RESP(x) ((x) << 8) argument
99 #define CLKF(x) ((x) << 0) argument
101 #define CLKR(x) ((x) << 7) argument
103 #define CLKFRAC(x) ((x) << 12) argument
107 #define IBIAS(x) ((x) << 20) argument
226 #define CLKV(x) ((x) << 0) argument
229 #define CLKS(x) ((x) << 0) argument
277 #define STATE0(x) ((x) << 0) argument
279 #define STATE1(x) ((x) << 5) argument
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A Drv250d.h32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
[all …]
A Drv770d.h47 # define UPLL_REF_DIV(x) ((x) << 16) argument
62 # define UPLL_FB_DIV(x) ((x) << 0) argument
119 #define CLKF(x) ((x) << 0) argument
121 #define CLKR(x) ((x) << 7) argument
123 #define CLKFRAC(x) ((x) << 12) argument
127 #define IBIAS(x) ((x) << 20) argument
271 #define CLKS(x) ((x) << 4) argument
274 #define CLKV(x) ((x) << 0) argument
291 #define STATE0(x) ((x) << 0) argument
293 #define STATE1(x) ((x) << 8) argument
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/linux-6.3-rc2/drivers/media/platform/verisilicon/
A Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
28 #define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) argument
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A Dhantro_g1_regs.h28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
80 #define G1_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) argument
101 #define G1_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) argument
102 #define G1_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) argument
111 #define G1_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) argument
153 #define G1_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) argument
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/linux-6.3-rc2/lib/crypto/
A Dchacha.c24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
35 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 8); in chacha_permute()
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/linux-6.3-rc2/drivers/net/ethernet/chelsio/cxgb/
A Dregs.h197 #define V_DAY(x) ((x) << S_DAY) argument
202 #define V_MONTH(x) ((x) << S_MONTH) argument
252 #define V_READY(x) ((x) << S_READY) argument
304 #define V_BANKS(x) ((x) << S_BANKS) argument
328 #define V_BUSY(x) ((x) << S_BUSY) argument
459 #define V_OP(x) ((x) << S_OP) argument
613 #define V_TPIWR(x) ((x) << S_TPIWR) argument
845 #define V_SACK(x) ((x) << S_SACK) argument
850 #define V_ECN(x) ((x) << S_ECN) argument
859 #define V_MSS(x) ((x) << S_MSS) argument
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/linux-6.3-rc2/drivers/phy/microchip/
A Dsparx5_serdes_regs.h941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
944 FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
2096 FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
2456 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2457 FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
2458 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2459 FIELD_GET(SD_LANE_MISC_RX_ENA, x)
2462 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
2463 FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
2464 #define SD_LANE_MISC_MUX_ENA_GET(x)\ argument
[all …]
/linux-6.3-rc2/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_main_regs.h4418 FIELD_GET(FDMA_CTRL_NRESET, x)
4443 #define GCB_CHIP_ID_ONE_SET(x)\ argument
4444 FIELD_PREP(GCB_CHIP_ID_ONE, x)
4445 #define GCB_CHIP_ID_ONE_GET(x)\ argument
4446 FIELD_GET(GCB_CHIP_ID_ONE, x)
6322 FIELD_GET(QS_INJ_CTRL_EOF, x)
6328 FIELD_GET(QS_INJ_CTRL_SOF, x)
6391 #define QSYS_ATOP_ATOP_SET(x)\ argument
6392 FIELD_PREP(QSYS_ATOP_ATOP, x)
6393 #define QSYS_ATOP_ATOP_GET(x)\ argument
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/linux-6.3-rc2/drivers/net/ethernet/chelsio/cxgb3/
A Dregs.h5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
33 #define V_FLMODE(x) ((x) << S_FLMODE) argument
82 #define V_RSPQ(x) ((x) << S_RSPQ) argument
113 #define V_CQ(x) ((x) << S_CQ) argument
804 #define V_OP(x) ((x) << S_OP) argument
822 #define V_AE(x) ((x) << S_AE) argument
828 #define V_PE(x) ((x) << S_PE) argument
833 #define V_UE(x) ((x) << S_UE) argument
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/linux-6.3-rc2/include/soc/mscc/
A Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) argument
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) argument
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) argument
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
64 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) argument
76 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) argument
99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) argument
116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) argument
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A Docelot_hsio.h106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
166 #define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) argument
172 #define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) argument
178 #define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) argument
194 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
228 #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) argument
241 #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0)) argument
253 #define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) argument
258 #define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) argument
310 #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) argument
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/linux-6.3-rc2/drivers/net/ethernet/chelsio/cxgb4/
A Dt4_regs.h77 #define QID_V(x) ((x) << QID_S) argument
80 #define DBPRIO_V(x) ((x) << DBPRIO_S) argument
84 #define PIDX_V(x) ((x) << PIDX_S) argument
89 #define DBTYPE_V(x) ((x) << DBTYPE_S) argument
162 #define BUSY_V(x) ((x) << BUSY_S) argument
400 #define TSOP_V(x) ((x) << TSOP_S) argument
773 #define BIR_V(x) ((x) << BIR_S) argument
2873 #define OP_V(x) ((x) << OP_S) argument
2926 #define MA_V(x) ((x) << MA_S) argument
2930 #define TP_V(x) ((x) << TP_S) argument
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dnavi10_sdma_pkt_open.h77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) argument
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) argument
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) argument
90 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) argument
96 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
102 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
3463 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER… argument
3526 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_d… argument
4227 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op… argument
4440 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_sh… argument
[all …]
A Dsdma_v6_0_0_pkt_open.h80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) argument
84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) argument
92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) argument
93 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) argument
4107 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER… argument
4125 #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEAD… argument
4131 #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEAD… argument
4182 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_d… argument
5015 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op… argument
5228 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_sh… argument
[all …]
/linux-6.3-rc2/drivers/net/ethernet/microchip/lan966x/
A Dlan966x_regs.h74 #define ANA_ANAINTR_INTR_SET(x)\ argument
75 FIELD_PREP(ANA_ANAINTR_INTR, x)
77 FIELD_GET(ANA_ANAINTR_INTR, x)
164 #define ANA_PGID_PGID_SET(x)\ argument
165 FIELD_PREP(ANA_PGID_PGID, x)
166 #define ANA_PGID_PGID_GET(x)\ argument
167 FIELD_GET(ANA_PGID_PGID, x)
1001 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) argument
1003 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) argument
1009 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) argument
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