1 /****************************************************************************** 2 * Filename: hw_adi.h 3 * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) 4 * Revision: 42365 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_ADI_H__ 38 #define __HW_ADI_H__ 39 40 //***************************************************************************** 41 // 42 // This file contains macros for controlling the ADI master and 43 // accessing ADI slave registers via the ADI Master. 44 // There are 3 categories of macros in this file: 45 // - macros that provide an offset to a register 46 // located within the DDI Master itself. 47 // - macros that define bits or bitfields 48 // within the DDI Master Registers. 49 // - macros that provide an "instruction offset" 50 // that are used when accessing a ADI Slave. 51 // 52 // The macros that that provide ADI Master register offsets and 53 // define bits and bitfields for those registers are the typical 54 // macros that appear in most hw_<module>.h header files. In 55 // the following example ADI_O_SLAVECONF is a macro for a 56 // register offset and ADI_SLAVECONF_WAITFORACK is a macro for 57 // a bit in that register. This example code will set the WAITFORACK 58 // bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this 59 // access the Master not the Slave). 60 // 61 // HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; 62 // 63 // The "instruction offset" macros are used to pass an instruction to 64 // the ADI Master when accessing ADI slave registers. These macros are 65 // only used when accessing ADI Slave Registers. (Remember ADI 66 // Master Registers are accessed normally). 67 // 68 // The instructions supported when accessing an ADI Slave Register follow: 69 // - Direct Access to an ADI Slave register. I.e. read or 70 // write the register. 71 // - Set the specified bits in a ADI Slave register. 72 // - Clear the specified bits in a ADI Slave register. 73 // - Mask write of 4 bits to the a ADI Slave register. 74 // - Mask write of 8 bits to the a ADI Slave register. 75 // - Mask write of 16 bits to the a ADI Slave register. 76 // 77 // Note: only the "Direct Access" offset should be used when reading 78 // a ADI Slave register. Only 4-bit reads are supported and 8 bits write are 79 // supported natively. If accessing wider bitfields, the read/write operation 80 // will be spread out over a number of transactions. This is hidden for the 81 // user, but can potentially be very timeconsuming. Especially of running 82 // on a slow clock. 83 // 84 // The generic format of using these macros for a read follows: 85 // // Read low 8-bits in ADI_SLAVE_OFF 86 // myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); 87 // 88 // // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) 89 // myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); 90 // 91 // Notes: In the above example: 92 // - ADI_MASTER_BASE is the base address of the ADI Master defined 93 // in the hw_memmap.h header file. 94 // - ADI_SLAVE_OFF is the ADI Slave offset defined in the 95 // hw_<adi_slave>.h header file (e.g. hw_adi_3_refsys_top.h for the refsys 96 // module). 97 // - ADI_O_DIR is the "instruction offset" macro defined in this 98 // file that specifies the Direct Access instruction. 99 // 100 // Writes can use any of the "instruction macros". 101 // The following examples do a "direct write" to an ADI Slave register 102 // ADI_SLAVE_OFF using different size operands: 103 // 104 // // ---------- DIRECT WRITES ---------- 105 // // Write 32-bits aligned 106 // HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; 107 // 108 // // Write 16-bits aligned to high 16-bits then low 16-bits 109 // // Add 2 to get to high 16-bits. 110 // HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; 111 // HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; 112 // 113 // // Write each byte at ADI_SLAVE_OFF, one at a time. 114 // // Add 1,2,or 3 to get to bytes 1,2, or 3. 115 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; 116 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; 117 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; 118 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; 119 // 120 // // ---------- SET/CLR ---------- 121 // The set and clear functions behave similarly to eachother. Each 122 // can be performed on an 8-, 16-, or 32-bit operand. 123 // Examples follow: 124 // // Set all odd bits in a 32-bit words 125 // HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; 126 // 127 // // Clear all bits in byte 2 (data[23:16]) using 32-bit operand 128 // HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; 129 // 130 // // Set even bits in byte 2 (data[23:16]) using 8-bit operand 131 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; 132 // 133 // // ---------- MASKED WRITES ---------- 134 // The mask writes are a bit different. They operate on nibbles, 135 // bytes, and 16-bit elements. Two operands are required; a 'mask' 136 // and 'data'; The operands are concatenated and written to the master. 137 // e.g. the mask and data are combined as follows for a 16 bit masked 138 // write: 139 // (mask << 16) | data; 140 // Examples follow: 141 // 142 // // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). 143 // // Byte write is needed. 144 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; 145 // 146 // // Do an 4 bit masked write of 4 to data[7:4]). 147 // // Add 1 for next nibble 148 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; 149 // 150 //***************************************************************************** 151 152 //***************************************************************************** 153 // 154 // The following are defines for the ADI master instruction offsets. 155 // 156 //***************************************************************************** 157 #define ADI_O_DIR 0x00000000 // Offset for the direct access 158 // instruction 159 #define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. 160 #define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. 161 #define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. 162 // Data bit[n] is written if mask 163 // bit[n] is set ('1'). 164 // Bits 7:4 are mask. Bits 3:0 are data. 165 // Requires 'byte' write. 166 #define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. 167 // Data bit[n] is written if mask 168 // bit[n] is set ('1'). Bits 15:8 are 169 // mask. Bits 7:0 are data. Requires 170 // 'short' write. 171 #define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. 172 // Data bit[n] is written if mask 173 // bit[n] is set ('1'). Bits 31:16 174 // are mask. Bits 15:0 are data. 175 // Requires 'long' write. 176 177 //***************************************************************************** 178 // 179 // The following are defines for the ADI register offsets. 180 // 181 //***************************************************************************** 182 #define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register 183 #define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the 188 // ADI_O_SLAVESTAT register. 189 // 190 //***************************************************************************** 191 #define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ 192 // signal. Writing 0 to this bit 193 // forces a sync with slave, 194 // ensuring that req will be 0. It 195 // is recommended to write 0 to 196 // this register before power down 197 // of the master. 198 #define ADI_SLAVESTAT_DI_REQ_M 0x00000002 199 #define ADI_SLAVESTAT_DI_REQ_S 1 200 #define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK 201 // signal 202 #define ADI_SLAVESTAT_DI_ACK_M 0x00000001 203 #define ADI_SLAVESTAT_DI_ACK_S 0 204 //***************************************************************************** 205 // 206 // The following are defines for the bit fields in the 207 // ADI_O_SLAVECONF register. 208 // 209 //***************************************************************************** 210 #define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer 211 // accessible when this bit is set. 212 // (unless sticky_bit_overwrite is 213 // asserted on top module) 214 #define ADI_SLAVECONF_CONFLOCK_M \ 215 0x00000080 216 #define ADI_SLAVECONF_CONFLOCK_S 7 217 #define ADI_SLAVECONF_WAITFORACK \ 218 0x00000004 // A transaction on the ADI 219 // interface does not end until ack 220 // has been received from the slave 221 // when this bit is set. 222 223 #define ADI_SLAVECONF_WAITFORACK_M \ 224 0x00000004 225 #define ADI_SLAVECONF_WAITFORACK_S 2 226 #define ADI_SLAVECONF_ADICLKSPEED_M \ 227 0x00000003 // Sets the period of an ADI 228 // transactions. All transactions 229 // takes an even number of clock 230 // cycles,- ADI clock rising edge 231 // occurs in the middle of the 232 // period. Data and ctrl to slave 233 // is set up in beginning of cycle, 234 // and data from slave is read in 235 // after the transaction 00: An ADI 236 // transaction takes 2 master clock 237 // cyclkes 01: An ADI transaction 238 // takes 4 master clock cycles 10: 239 // And ADI Transaction takes 8 240 // master clock cycles 11: An ADI 241 // transaction takes 16 master 242 // clock cycles 243 244 #define ADI_SLAVECONF_ADICLKSPEED_S 0 245 246 //***************************************************************************** 247 // 248 // The following are defines pseudo-magic numbers that should go away. 249 // New code should not use these registers and old code should be ported 250 // to not use these. 251 // 252 //***************************************************************************** 253 #define ADI_O_DIR03 0x00000000 // Direct access for adi byte 254 // offsets 0 to 3 255 #define ADI_O_DIR47 0x00000004 // Direct access for adi byte 256 // offsets 4 to 7 257 #define ADI_O_DIR811 0x00000008 // Direct access for adi byte 258 // offsets 8 to 11 259 #define ADI_O_DIR1215 0x0000000C // Direct access for adi byte 260 // offsets 12 to 15 261 #define ADI_O_SET03 0x00000010 // Set register for ADI byte 262 // offsets 0 to 3 263 #define ADI_O_SET47 0x00000014 // Set register for ADI byte 264 // offsets 4 to 7 265 #define ADI_O_SET811 0x00000018 // Set register for ADI byte 266 // offsets 8 to 11 267 #define ADI_O_SET1215 0x0000001C // Set register for ADI byte 268 // offsets 12 to 15 269 #define ADI_O_CLR03 0x00000020 // Clear register for ADI byte 270 // offsets 0 to 3 271 #define ADI_O_CLR47 0x00000024 // Clear register for ADI byte 272 // offsets 4 to 7 273 #define ADI_O_CLR811 0x00000028 // Clear register for ADI byte 274 // offsets 8 to 11 275 #define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte 276 // offsets 12 to 15 277 #define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register 278 #define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration 279 // register 280 #define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI 281 // Registers at byte offsets 0 and 282 // 1 283 #define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI 284 // Registers at byte offsets 2 and 285 // 3 286 #define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI 287 // Registers at byte offsets 4 and 288 // 5 289 #define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI 290 // Registers at byte offsets 6 and 291 // 7 292 #define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI 293 // Registers at byte offsets 8 and 294 // 9 295 #define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI 296 // Registers at byte offsets 10 and 297 // 11 298 #define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI 299 // Registers at byte offsets 12 and 300 // 13 301 #define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI 302 // Registers at byte offsets 14 and 303 // 15 304 #define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI 305 // Registers at byte offsets 0 and 306 // 1 307 #define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI 308 // Registers at byte offsets 2 and 309 // 3 310 #define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI 311 // Registers at byte offsets 4 and 312 // 5 313 #define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI 314 // Registers at byte offsets 6 and 315 // 7 316 #define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI 317 // Registers at byte offsets 8 and 318 // 9 319 #define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI 320 // Registers at byte offsets 10 and 321 // 11 322 #define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI 323 // Registers at byte offsets 12 and 324 // 13 325 #define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI 326 // Registers at byte offsets 14 and 327 // 15 328 #define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI 329 // Registers at byte offsets 0 and 330 // 1 331 #define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI 332 // Registers at byte offsets 2 and 333 // 3 334 #define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI 335 // Registers at byte offsets 4 and 336 // 5 337 #define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI 338 // Registers at byte offsets 6 and 339 // 7 340 #define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI 341 // Registers at byte offsets 8 and 342 // 9 343 #define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI 344 // Registers at byte offsets 10 and 345 // 11 346 #define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI 347 // Registers at byte offsets 12 and 348 // 13 349 #define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI 350 // Registers at byte offsets 14 and 351 // 15 352 353 //***************************************************************************** 354 // 355 // The following are defines for the bit fields in the ADI_O_DIR03 register. 356 // 357 //***************************************************************************** 358 #define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 359 #define ADI_DIR03_B3_S 24 360 #define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 361 #define ADI_DIR03_B2_S 16 362 #define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 363 #define ADI_DIR03_B1_S 8 364 #define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 365 #define ADI_DIR03_B0_S 0 366 //***************************************************************************** 367 // 368 // The following are defines for the bit fields in the ADI_O_DIR47 register. 369 // 370 //***************************************************************************** 371 #define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 372 #define ADI_DIR47_B3_S 24 373 #define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 374 #define ADI_DIR47_B2_S 16 375 #define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 376 #define ADI_DIR47_B1_S 8 377 #define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 378 #define ADI_DIR47_B0_S 0 379 //***************************************************************************** 380 // 381 // The following are defines for the bit fields in the ADI_O_DIR811 register. 382 // 383 //***************************************************************************** 384 #define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register 385 // 11 386 #define ADI_DIR811_B3_S 24 387 #define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register 388 // 10 389 #define ADI_DIR811_B2_S 16 390 #define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 391 #define ADI_DIR811_B1_S 8 392 #define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 393 #define ADI_DIR811_B0_S 0 394 //***************************************************************************** 395 // 396 // The following are defines for the bit fields in the ADI_O_DIR1215 register. 397 // 398 //***************************************************************************** 399 #define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register 400 // 15 401 #define ADI_DIR1215_B3_S 24 402 #define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register 403 // 14 404 #define ADI_DIR1215_B2_S 16 405 #define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register 406 // 13 407 #define ADI_DIR1215_B1_S 8 408 #define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register 409 // 12 410 #define ADI_DIR1215_B0_S 0 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the ADI_O_SET03 register. 414 // 415 //***************************************************************************** 416 #define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the 417 // corresponding bit in ADI 418 // register 3. Read returns 0. 419 #define ADI_SET03_S3_S 24 420 #define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the 421 // corresponding bit in ADI 422 // register 2. Read returns 0. 423 #define ADI_SET03_S2_S 16 424 #define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the 425 // corresponding bit in ADI 426 // register 1. Read returns 0. 427 #define ADI_SET03_S1_S 8 428 #define ADI_SET03_S0_M 0x000000FF // A high bit value will set the 429 // corresponding bit in ADI 430 // register 0. Read returns 0. 431 #define ADI_SET03_S0_S 0 432 //***************************************************************************** 433 // 434 // The following are defines for the bit fields in the ADI_O_SET47 register. 435 // 436 //***************************************************************************** 437 #define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the 438 // corresponding bit in ADI 439 // register 7. Read returns 0. 440 #define ADI_SET47_S3_S 24 441 #define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the 442 // corresponding bit in ADI 443 // register 6. Read returns 0. 444 #define ADI_SET47_S2_S 16 445 #define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the 446 // corresponding bit in ADI 447 // register 5. Read returns 0. 448 #define ADI_SET47_S1_S 8 449 #define ADI_SET47_S0_M 0x000000FF // A high bit value will set the 450 // corresponding bit in ADI 451 // register 4. Read returns 0. 452 #define ADI_SET47_S0_S 0 453 //***************************************************************************** 454 // 455 // The following are defines for the bit fields in the ADI_O_SET811 register. 456 // 457 //***************************************************************************** 458 #define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the 459 // corresponding bit in ADI 460 // register 11. Read returns 0. 461 #define ADI_SET811_S3_S 24 462 #define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the 463 // corresponding bit in ADI 464 // register 10. Read returns 0. 465 #define ADI_SET811_S2_S 16 466 #define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the 467 // corresponding bit in ADI 468 // register 9. Read returns 0. 469 #define ADI_SET811_S1_S 8 470 #define ADI_SET811_S0_M 0x000000FF // A high bit value will set the 471 // corresponding bit in ADI 472 // register 8. Read returns 0. 473 #define ADI_SET811_S0_S 0 474 //***************************************************************************** 475 // 476 // The following are defines for the bit fields in the ADI_O_SET1215 register. 477 // 478 //***************************************************************************** 479 #define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the 480 // corresponding bit in ADI 481 // register 15. Read returns 0. 482 #define ADI_SET1215_S3_S 24 483 #define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the 484 // corresponding bit in ADI 485 // register 14. Read returns 0. 486 #define ADI_SET1215_S2_S 16 487 #define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the 488 // corresponding bit in ADI 489 // register 13. Read returns 0. 490 #define ADI_SET1215_S1_S 8 491 #define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the 492 // corresponding bit in ADI 493 // register 12. Read returns 0. 494 #define ADI_SET1215_S0_S 0 495 //***************************************************************************** 496 // 497 // The following are defines for the bit fields in the ADI_O_CLR03 register. 498 // 499 //***************************************************************************** 500 #define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the 501 // corresponding bit in ADI 502 // register 3 503 #define ADI_CLR03_S3_S 24 504 #define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the 505 // corresponding bit in ADI 506 // register 2 507 #define ADI_CLR03_S2_S 16 508 #define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the 509 // corresponding bit in ADI 510 // register 1 511 #define ADI_CLR03_S1_S 8 512 #define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the 513 // corresponding bit in ADI 514 // register 0 515 #define ADI_CLR03_S0_S 0 516 //***************************************************************************** 517 // 518 // The following are defines for the bit fields in the ADI_O_CLR47 register. 519 // 520 //***************************************************************************** 521 #define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the 522 // corresponding bit in ADI 523 // register 7 524 #define ADI_CLR47_S3_S 24 525 #define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the 526 // corresponding bit in ADI 527 // register 6 528 #define ADI_CLR47_S2_S 16 529 #define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the 530 // corresponding bit in ADI 531 // register 5 532 #define ADI_CLR47_S1_S 8 533 #define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the 534 // corresponding bit in ADI 535 // register 4 536 #define ADI_CLR47_S0_S 0 537 //***************************************************************************** 538 // 539 // The following are defines for the bit fields in the ADI_O_CLR811 register. 540 // 541 //***************************************************************************** 542 #define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the 543 // corresponding bit in ADI 544 // register 11 545 #define ADI_CLR811_S3_S 24 546 #define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the 547 // corresponding bit in ADI 548 // register 10 549 #define ADI_CLR811_S2_S 16 550 #define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the 551 // corresponding bit in ADI 552 // register 9 553 #define ADI_CLR811_S1_S 8 554 #define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the 555 // corresponding bit in ADI 556 // register 8 557 #define ADI_CLR811_S0_S 0 558 //***************************************************************************** 559 // 560 // The following are defines for the bit fields in the ADI_O_CLR1215 register. 561 // 562 //***************************************************************************** 563 #define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the 564 // corresponding bit in ADI 565 // register 15 566 #define ADI_CLR1215_S3_S 24 567 #define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the 568 // corresponding bit in ADI 569 // register 14 570 #define ADI_CLR1215_S2_S 16 571 #define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the 572 // corresponding bit in ADI 573 // register 13 574 #define ADI_CLR1215_S1_S 8 575 #define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the 576 // corresponding bit in ADI 577 // register 12 578 #define ADI_CLR1215_S0_S 0 579 //***************************************************************************** 580 // 581 // The following are defines for the bit fields in the 582 // ADI_O_SLAVESTAT register. 583 // 584 //***************************************************************************** 585 #define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ 586 // signal. Writing 0 to this bit 587 // forces a sync with slave, 588 // ensuring that req will be 0. It 589 // is recommended to write 0 to 590 // this register before power down 591 // of the master. 592 #define ADI_SLAVESTAT_DI_REQ_M 0x00000002 593 #define ADI_SLAVESTAT_DI_REQ_S 1 594 #define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK 595 // signal 596 #define ADI_SLAVESTAT_DI_ACK_M 0x00000001 597 #define ADI_SLAVESTAT_DI_ACK_S 0 598 //***************************************************************************** 599 // 600 // The following are defines for the bit fields in the 601 // ADI_O_SLAVECONF register. 602 // 603 //***************************************************************************** 604 #define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer 605 // accessible when this bit is set. 606 // (unless sticky_bit_overwrite is 607 // asserted on top module) 608 #define ADI_SLAVECONF_CONFLOCK_M \ 609 0x00000080 610 #define ADI_SLAVECONF_CONFLOCK_S 7 611 #define ADI_SLAVECONF_WAITFORACK \ 612 0x00000004 // A transaction on the ADI 613 // interface does not end until ack 614 // has been received from the slave 615 // when this bit is set. 616 617 #define ADI_SLAVECONF_WAITFORACK_M \ 618 0x00000004 619 #define ADI_SLAVECONF_WAITFORACK_S 2 620 #define ADI_SLAVECONF_ADICLKSPEED_M \ 621 0x00000003 // Sets the period of an ADI 622 // transactions. All transactions 623 // takes an even number of clock 624 // cycles,- ADI clock rising edge 625 // occurs in the middle of the 626 // period. Data and ctrl to slave 627 // is set up in beginning of cycle, 628 // and data from slave is read in 629 // after the transaction 00: An ADI 630 // transaction takes 2 master clock 631 // cyclkes 01: An ADI transaction 632 // takes 4 master clock cycles 10: 633 // And ADI Transaction takes 8 634 // master clock cycles 11: An ADI 635 // transaction takes 16 master 636 // clock cycles 637 638 #define ADI_SLAVECONF_ADICLKSPEED_S 0 639 //***************************************************************************** 640 // 641 // The following are defines for the bit fields in the ADI_O_MASK4B01 register. 642 // 643 //***************************************************************************** 644 #define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 645 // register 1 646 #define ADI_MASK4B01_M1H_S 28 647 #define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 648 // register 1, - only bits selected 649 // by mask M1H will be affected by 650 // access 651 #define ADI_MASK4B01_D1H_S 24 652 #define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 653 // register 1 654 #define ADI_MASK4B01_M1L_S 20 655 #define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 656 // register 1, - only bits selected 657 // by mask M1L will be affected by 658 // access 659 #define ADI_MASK4B01_D1L_S 16 660 #define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 661 // register 0 662 #define ADI_MASK4B01_M0H_S 12 663 #define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 664 // register 0, - only bits selected 665 // by mask M0H will be affected by 666 // access 667 #define ADI_MASK4B01_D0H_S 8 668 #define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 669 // register 0 670 #define ADI_MASK4B01_M0L_S 4 671 #define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI 672 // register 0, - only bits selected 673 // by mask M0L will be affected by 674 // access 675 #define ADI_MASK4B01_D0L_S 0 676 //***************************************************************************** 677 // 678 // The following are defines for the bit fields in the ADI_O_MASK4B23 register. 679 // 680 //***************************************************************************** 681 #define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 682 // register 3 683 #define ADI_MASK4B23_M1H_S 28 684 #define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 685 // register 3, - only bits selected 686 // by mask M1H will be affected by 687 // access 688 #define ADI_MASK4B23_D1H_S 24 689 #define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 690 // register 3 691 #define ADI_MASK4B23_M1L_S 20 692 #define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 693 // register 3, - only bits selected 694 // by mask M1L will be affected by 695 // access 696 #define ADI_MASK4B23_D1L_S 16 697 #define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 698 // register 2 699 #define ADI_MASK4B23_M0H_S 12 700 #define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 701 // register 2, - only bits selected 702 // by mask M0H will be affected by 703 // access 704 #define ADI_MASK4B23_D0H_S 8 705 #define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 706 // register 2 707 #define ADI_MASK4B23_M0L_S 4 708 #define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI 709 // register 2, - only bits selected 710 // by mask M0L will be affected by 711 // access 712 #define ADI_MASK4B23_D0L_S 0 713 //***************************************************************************** 714 // 715 // The following are defines for the bit fields in the ADI_O_MASK4B45 register. 716 // 717 //***************************************************************************** 718 #define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 719 // register 5 720 #define ADI_MASK4B45_M1H_S 28 721 #define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 722 // register 5, - only bits selected 723 // by mask M1H will be affected by 724 // access 725 #define ADI_MASK4B45_D1H_S 24 726 #define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 727 // register 5 728 #define ADI_MASK4B45_M1L_S 20 729 #define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 730 // register 5, - only bits selected 731 // by mask M1L will be affected by 732 // access 733 #define ADI_MASK4B45_D1L_S 16 734 #define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 735 // register 4 736 #define ADI_MASK4B45_M0H_S 12 737 #define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 738 // register 4, - only bits selected 739 // by mask M0H will be affected by 740 // access 741 #define ADI_MASK4B45_D0H_S 8 742 #define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 743 // register 4 744 #define ADI_MASK4B45_M0L_S 4 745 #define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI 746 // register 4, - only bits selected 747 // by mask M0L will be affected by 748 // access 749 #define ADI_MASK4B45_D0L_S 0 750 //***************************************************************************** 751 // 752 // The following are defines for the bit fields in the ADI_O_MASK4B67 register. 753 // 754 //***************************************************************************** 755 #define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 756 // register 7 757 #define ADI_MASK4B67_M1H_S 28 758 #define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 759 // register 7, - only bits selected 760 // by mask M1H will be affected by 761 // access 762 #define ADI_MASK4B67_D1H_S 24 763 #define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 764 // register 7 765 #define ADI_MASK4B67_M1L_S 20 766 #define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 767 // register 7, - only bits selected 768 // by mask M1L will be affected by 769 // access 770 #define ADI_MASK4B67_D1L_S 16 771 #define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 772 // register 6 773 #define ADI_MASK4B67_M0H_S 12 774 #define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 775 // register 6, - only bits selected 776 // by mask M0H will be affected by 777 // access 778 #define ADI_MASK4B67_D0H_S 8 779 #define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 780 // register 6 781 #define ADI_MASK4B67_M0L_S 4 782 #define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI 783 // register 6, - only bits selected 784 // by mask M0L will be affected by 785 // access 786 #define ADI_MASK4B67_D0L_S 0 787 //***************************************************************************** 788 // 789 // The following are defines for the bit fields in the ADI_O_MASK4B89 register. 790 // 791 //***************************************************************************** 792 #define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 793 // register 9 794 #define ADI_MASK4B89_M1H_S 28 795 #define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 796 // register 9, - only bits selected 797 // by mask M1H will be affected by 798 // access 799 #define ADI_MASK4B89_D1H_S 24 800 #define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 801 // register 9 802 #define ADI_MASK4B89_M1L_S 20 803 #define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 804 // register 9, - only bits selected 805 // by mask M1L will be affected by 806 // access 807 #define ADI_MASK4B89_D1L_S 16 808 #define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 809 // register 8 810 #define ADI_MASK4B89_M0H_S 12 811 #define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 812 // register 8, - only bits selected 813 // by mask M0H will be affected by 814 // access 815 #define ADI_MASK4B89_D0H_S 8 816 #define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 817 // register 8 818 #define ADI_MASK4B89_M0L_S 4 819 #define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI 820 // register 8, - only bits selected 821 // by mask M0L will be affected by 822 // access 823 #define ADI_MASK4B89_D0L_S 0 824 //***************************************************************************** 825 // 826 // The following are defines for the bit fields in the 827 // ADI_O_MASK4B1011 register. 828 // 829 //***************************************************************************** 830 #define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 831 // register 11 832 #define ADI_MASK4B1011_M1H_S 28 833 #define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 834 // register 11, - only bits 835 // selected by mask M1H will be 836 // affected by access 837 #define ADI_MASK4B1011_D1H_S 24 838 #define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 839 // register 11 840 #define ADI_MASK4B1011_M1L_S 20 841 #define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 842 // register 11, - only bits 843 // selected by mask M1L will be 844 // affected by access 845 #define ADI_MASK4B1011_D1L_S 16 846 #define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 847 // register 10 848 #define ADI_MASK4B1011_M0H_S 12 849 #define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 850 // register 10, - only bits 851 // selected by mask M0H will be 852 // affected by access 853 #define ADI_MASK4B1011_D0H_S 8 854 #define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 855 // register 10 856 #define ADI_MASK4B1011_M0L_S 4 857 #define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI 858 // register 10, - only bits 859 // selected by mask M0L will be 860 // affected by access 861 #define ADI_MASK4B1011_D0L_S 0 862 //***************************************************************************** 863 // 864 // The following are defines for the bit fields in the 865 // ADI_O_MASK4B1213 register. 866 // 867 //***************************************************************************** 868 #define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 869 // register 13 870 #define ADI_MASK4B1213_M1H_S 28 871 #define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 872 // register 13, - only bits 873 // selected by mask M1H will be 874 // affected by access 875 #define ADI_MASK4B1213_D1H_S 24 876 #define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 877 // register 13 878 #define ADI_MASK4B1213_M1L_S 20 879 #define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 880 // register 13, - only bits 881 // selected by mask M1L will be 882 // affected by access 883 #define ADI_MASK4B1213_D1L_S 16 884 #define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 885 // register 12 886 #define ADI_MASK4B1213_M0H_S 12 887 #define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 888 // register 12, - only bits 889 // selected by mask M0H will be 890 // affected by access 891 #define ADI_MASK4B1213_D0H_S 8 892 #define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 893 // register 12 894 #define ADI_MASK4B1213_M0L_S 4 895 #define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI 896 // register 12, - only bits 897 // selected by mask M0L will be 898 // affected by access 899 #define ADI_MASK4B1213_D0L_S 0 900 //***************************************************************************** 901 // 902 // The following are defines for the bit fields in the 903 // ADI_O_MASK4B1415 register. 904 // 905 //***************************************************************************** 906 #define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 907 // register 15 908 #define ADI_MASK4B1415_M1H_S 28 909 #define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 910 // register 15, - only bits 911 // selected by mask M1H will be 912 // affected by access 913 #define ADI_MASK4B1415_D1H_S 24 914 #define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 915 // register 15 916 #define ADI_MASK4B1415_M1L_S 20 917 #define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 918 // register 15, - only bits 919 // selected by mask M1L will be 920 // affected by access 921 #define ADI_MASK4B1415_D1L_S 16 922 #define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 923 // register 14 924 #define ADI_MASK4B1415_M0H_S 12 925 #define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 926 // register 14, - only bits 927 // selected by mask M0H will be 928 // affected by access 929 #define ADI_MASK4B1415_D0H_S 8 930 #define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 931 // register 14 932 #define ADI_MASK4B1415_M0L_S 4 933 #define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI 934 // register 14, - only bits 935 // selected by mask M0L will be 936 // affected by access 937 #define ADI_MASK4B1415_D0L_S 0 938 //***************************************************************************** 939 // 940 // The following are defines for the bit fields in the ADI_O_MASK8B01 register. 941 // 942 //***************************************************************************** 943 #define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 944 #define ADI_MASK8B01_M1_S 24 945 #define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only 946 // bits selected by mask M1 will be 947 // affected by access 948 #define ADI_MASK8B01_D1_S 16 949 #define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 950 #define ADI_MASK8B01_M0_S 8 951 #define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only 952 // bits selected by mask M0 will be 953 // affected by access 954 #define ADI_MASK8B01_D0_S 0 955 //***************************************************************************** 956 // 957 // The following are defines for the bit fields in the ADI_O_MASK8B23 register. 958 // 959 //***************************************************************************** 960 #define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 961 #define ADI_MASK8B23_M1_S 24 962 #define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only 963 // bits selected by mask M1 will be 964 // affected by access 965 #define ADI_MASK8B23_D1_S 16 966 #define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 967 #define ADI_MASK8B23_M0_S 8 968 #define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only 969 // bits selected by mask M0 will be 970 // affected by access 971 #define ADI_MASK8B23_D0_S 0 972 //***************************************************************************** 973 // 974 // The following are defines for the bit fields in the ADI_O_MASK8B45 register. 975 // 976 //***************************************************************************** 977 #define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 978 #define ADI_MASK8B45_M1_S 24 979 #define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only 980 // bits selected by mask M1 will be 981 // affected by access 982 #define ADI_MASK8B45_D1_S 16 983 #define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 984 #define ADI_MASK8B45_M0_S 8 985 #define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only 986 // bits selected by mask M0 will be 987 // affected by access 988 #define ADI_MASK8B45_D0_S 0 989 //***************************************************************************** 990 // 991 // The following are defines for the bit fields in the ADI_O_MASK8B67 register. 992 // 993 //***************************************************************************** 994 #define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 995 #define ADI_MASK8B67_M1_S 24 996 #define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only 997 // bits selected by mask M1 will be 998 // affected by access 999 #define ADI_MASK8B67_D1_S 16 1000 #define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 1001 #define ADI_MASK8B67_M0_S 8 1002 #define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only 1003 // bits selected by mask M0 will be 1004 // affected by access 1005 #define ADI_MASK8B67_D0_S 0 1006 //***************************************************************************** 1007 // 1008 // The following are defines for the bit fields in the ADI_O_MASK8B89 register. 1009 // 1010 //***************************************************************************** 1011 #define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 1012 #define ADI_MASK8B89_M1_S 24 1013 #define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only 1014 // bits selected by mask M1 will be 1015 // affected by access 1016 #define ADI_MASK8B89_D1_S 16 1017 #define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 1018 #define ADI_MASK8B89_M0_S 8 1019 #define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only 1020 // bits selected by mask M0 will be 1021 // affected by access 1022 #define ADI_MASK8B89_D0_S 0 1023 //***************************************************************************** 1024 // 1025 // The following are defines for the bit fields in the 1026 // ADI_O_MASK8B1011 register. 1027 // 1028 //***************************************************************************** 1029 #define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 1030 #define ADI_MASK8B1011_M1_S 24 1031 #define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - 1032 // only bits selected by mask M1 1033 // will be affected by access 1034 #define ADI_MASK8B1011_D1_S 16 1035 #define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 1036 #define ADI_MASK8B1011_M0_S 8 1037 #define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - 1038 // only bits selected by mask M0 1039 // will be affected by access 1040 #define ADI_MASK8B1011_D0_S 0 1041 //***************************************************************************** 1042 // 1043 // The following are defines for the bit fields in the 1044 // ADI_O_MASK8B1213 register. 1045 // 1046 //***************************************************************************** 1047 #define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 1048 #define ADI_MASK8B1213_M1_S 24 1049 #define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - 1050 // only bits selected by mask M1 1051 // will be affected by access 1052 #define ADI_MASK8B1213_D1_S 16 1053 #define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 1054 #define ADI_MASK8B1213_M0_S 8 1055 #define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - 1056 // only bits selected by mask M0 1057 // will be affected by access 1058 #define ADI_MASK8B1213_D0_S 0 1059 //***************************************************************************** 1060 // 1061 // The following are defines for the bit fields in the 1062 // ADI_O_MASK8B1415 register. 1063 // 1064 //***************************************************************************** 1065 #define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 1066 #define ADI_MASK8B1415_M1_S 24 1067 #define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - 1068 // only bits selected by mask M1 1069 // will be affected by access 1070 #define ADI_MASK8B1415_D1_S 16 1071 #define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 1072 #define ADI_MASK8B1415_M0_S 8 1073 #define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - 1074 // only bits selected by mask M0 1075 // will be affected by access 1076 #define ADI_MASK8B1415_D0_S 0 1077 //***************************************************************************** 1078 // 1079 // The following are defines for the bit fields in the 1080 // ADI_O_MASK16B01 register. 1081 // 1082 //***************************************************************************** 1083 #define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 1084 #define ADI_MASK16B01_M_S 16 1085 #define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at 1086 // offsets 0 and 1, - only bits 1087 // selected by mask M will be 1088 // affected by access 1089 #define ADI_MASK16B01_D_S 0 1090 //***************************************************************************** 1091 // 1092 // The following are defines for the bit fields in the 1093 // ADI_O_MASK16B23 register. 1094 // 1095 //***************************************************************************** 1096 #define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 1097 #define ADI_MASK16B23_M_S 16 1098 #define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at 1099 // offsets 2 and 3, - only bits 1100 // selected by mask M will be 1101 // affected by access 1102 #define ADI_MASK16B23_D_S 0 1103 //***************************************************************************** 1104 // 1105 // The following are defines for the bit fields in the 1106 // ADI_O_MASK16B45 register. 1107 // 1108 //***************************************************************************** 1109 #define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 1110 #define ADI_MASK16B45_M_S 16 1111 #define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at 1112 // offsets 4 and 5, - only bits 1113 // selected by mask M will be 1114 // affected by access 1115 #define ADI_MASK16B45_D_S 0 1116 //***************************************************************************** 1117 // 1118 // The following are defines for the bit fields in the 1119 // ADI_O_MASK16B67 register. 1120 // 1121 //***************************************************************************** 1122 #define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 1123 #define ADI_MASK16B67_M_S 16 1124 #define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at 1125 // offsets 6 and 7, - only bits 1126 // selected by mask M will be 1127 // affected by access 1128 #define ADI_MASK16B67_D_S 0 1129 //***************************************************************************** 1130 // 1131 // The following are defines for the bit fields in the 1132 // ADI_O_MASK16B89 register. 1133 // 1134 //***************************************************************************** 1135 #define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 1136 #define ADI_MASK16B89_M_S 16 1137 #define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at 1138 // offsets 8 and 9, - only bits 1139 // selected by mask M will be 1140 // affected by access 1141 #define ADI_MASK16B89_D_S 0 1142 //***************************************************************************** 1143 // 1144 // The following are defines for the bit fields in the 1145 // ADI_O_MASK16B1011 register. 1146 // 1147 //***************************************************************************** 1148 #define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 1149 #define ADI_MASK16B1011_M_S 16 1150 #define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at 1151 // offsets 10 and 11, - only bits 1152 // selected by mask M will be 1153 // affected by access 1154 #define ADI_MASK16B1011_D_S 0 1155 //***************************************************************************** 1156 // 1157 // The following are defines for the bit fields in the 1158 // ADI_O_MASK16B1213 register. 1159 // 1160 //***************************************************************************** 1161 #define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 1162 #define ADI_MASK16B1213_M_S 16 1163 #define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at 1164 // offsets 12 and 13, - only bits 1165 // selected by mask M will be 1166 // affected by access 1167 #define ADI_MASK16B1213_D_S 0 1168 //***************************************************************************** 1169 // 1170 // The following are defines for the bit fields in the 1171 // ADI_O_MASK16B1415 register. 1172 // 1173 //***************************************************************************** 1174 #define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 1175 #define ADI_MASK16B1415_M_S 16 1176 #define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at 1177 // offsets 14 and 15, - only bits 1178 // selected by mask M will be 1179 // affected by access 1180 #define ADI_MASK16B1415_D_S 0 1181 1182 #endif // __HW_ADI_H__ 1183