1 /****************************************************************************** 2 * Filename: hw_aon_rtc_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_RTC_H__ 38 #define __HW_AON_RTC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_RTC component 44 // 45 //***************************************************************************** 46 // Control 47 #define AON_RTC_O_CTL 0x00000000 48 49 // Event Flags, RTC Status 50 #define AON_RTC_O_EVFLAGS 0x00000004 51 52 // Second Counter Value, Integer Part 53 #define AON_RTC_O_SEC 0x00000008 54 55 // Second Counter Value, Fractional Part 56 #define AON_RTC_O_SUBSEC 0x0000000C 57 58 // Subseconds Increment 59 #define AON_RTC_O_SUBSECINC 0x00000010 60 61 // Channel Configuration 62 #define AON_RTC_O_CHCTL 0x00000014 63 64 // Channel 0 Compare Value 65 #define AON_RTC_O_CH0CMP 0x00000018 66 67 // Channel 1 Compare Value 68 #define AON_RTC_O_CH1CMP 0x0000001C 69 70 // Channel 2 Compare Value 71 #define AON_RTC_O_CH2CMP 0x00000020 72 73 // Channel 2 Compare Value Auto-increment 74 #define AON_RTC_O_CH2CMPINC 0x00000024 75 76 // Channel 1 Capture Value 77 #define AON_RTC_O_CH1CAPT 0x00000028 78 79 // AON Synchronization 80 #define AON_RTC_O_SYNC 0x0000002C 81 82 //***************************************************************************** 83 // 84 // Register: AON_RTC_O_CTL 85 // 86 //***************************************************************************** 87 // Field: [18:16] COMB_EV_MASK 88 // 89 // Eventmask selecting which delayed events that form the combined event. 90 // ENUMs: 91 // CH2 Use Channel 2 delayed event in combined event 92 // CH1 Use Channel 1 delayed event in combined event 93 // CH0 Use Channel 0 delayed event in combined event 94 // NONE No event is selected for combined event. 95 #define AON_RTC_CTL_COMB_EV_MASK_W 3 96 #define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 97 #define AON_RTC_CTL_COMB_EV_MASK_S 16 98 #define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 99 #define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 100 #define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 101 #define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 102 103 // Field: [11:8] EV_DELAY 104 // 105 // Number of SCLK_LF clock cycles waited before generating delayed events. 106 // (Common setting for all RTC cannels) the delayed event is delayed 107 // ENUMs: 108 // D144 Delay by 144 clock cycles 109 // D128 Delay by 128 clock cycles 110 // D112 Delay by 112 clock cycles 111 // D96 Delay by 96 clock cycles 112 // D80 Delay by 80 clock cycles 113 // D64 Delay by 64 clock cycles 114 // D48 Delay by 48 clock cycles 115 // D32 Delay by 32 clock cycles 116 // D16 Delay by 16 clock cycles 117 // D8 Delay by 8 clock cycles 118 // D4 Delay by 4 clock cycles 119 // D2 Delay by 2 clock cycles 120 // D1 Delay by 1 clock cycles 121 // D0 No delay on delayed event 122 #define AON_RTC_CTL_EV_DELAY_W 4 123 #define AON_RTC_CTL_EV_DELAY_M 0x00000F00 124 #define AON_RTC_CTL_EV_DELAY_S 8 125 #define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 126 #define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 127 #define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 128 #define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 129 #define AON_RTC_CTL_EV_DELAY_D80 0x00000900 130 #define AON_RTC_CTL_EV_DELAY_D64 0x00000800 131 #define AON_RTC_CTL_EV_DELAY_D48 0x00000700 132 #define AON_RTC_CTL_EV_DELAY_D32 0x00000600 133 #define AON_RTC_CTL_EV_DELAY_D16 0x00000500 134 #define AON_RTC_CTL_EV_DELAY_D8 0x00000400 135 #define AON_RTC_CTL_EV_DELAY_D4 0x00000300 136 #define AON_RTC_CTL_EV_DELAY_D2 0x00000200 137 #define AON_RTC_CTL_EV_DELAY_D1 0x00000100 138 #define AON_RTC_CTL_EV_DELAY_D0 0x00000000 139 140 // Field: [7] RESET 141 // 142 // RTC Counter reset. 143 // 144 // Writing 1 to this bit will reset the RTC counter. 145 // 146 // This bit is cleared when reset takes effect 147 #define AON_RTC_CTL_RESET 0x00000080 148 #define AON_RTC_CTL_RESET_BITN 7 149 #define AON_RTC_CTL_RESET_M 0x00000080 150 #define AON_RTC_CTL_RESET_S 7 151 152 // Field: [2] RTC_4KHZ_EN 153 // 154 // RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 155 // which is used by AUX timer. 156 // 157 // 0: RTC_4KHZ signal is forced to 0 158 // 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) 159 #define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 160 #define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 161 #define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 162 #define AON_RTC_CTL_RTC_4KHZ_EN_S 2 163 164 // Field: [1] RTC_UPD_EN 165 // 166 // RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is 167 // SCLK_LF divided by 2 168 // 169 // 0: RTC_UPD signal is forced to 0 170 // 1: RTC_UPD signal is toggling @16 kHz 171 #define AON_RTC_CTL_RTC_UPD_EN 0x00000002 172 #define AON_RTC_CTL_RTC_UPD_EN_BITN 1 173 #define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 174 #define AON_RTC_CTL_RTC_UPD_EN_S 1 175 176 // Field: [0] EN 177 // 178 // Enable RTC counter 179 // 180 // 0: Halted (frozen) 181 // 1: Running 182 #define AON_RTC_CTL_EN 0x00000001 183 #define AON_RTC_CTL_EN_BITN 0 184 #define AON_RTC_CTL_EN_M 0x00000001 185 #define AON_RTC_CTL_EN_S 0 186 187 //***************************************************************************** 188 // 189 // Register: AON_RTC_O_EVFLAGS 190 // 191 //***************************************************************************** 192 // Field: [16] CH2 193 // 194 // Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or 195 // passes the CH2CMP value. 196 // 197 // An event will be scheduled to occur as soon as possible when writing to 198 // CH2CMP provided that the channel is enabled and the new value matches any 199 // time between next RTC value and 1 second in the past 200 // 201 // Writing 1 clears this flag. Note that a new event can not occur on this 202 // channel in first 2 SCLK_LF cycles after a clearance. 203 // 204 // AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it 205 // using AUX_WUC:WUEVCLR.AON_RTC_CH2. 206 #define AON_RTC_EVFLAGS_CH2 0x00010000 207 #define AON_RTC_EVFLAGS_CH2_BITN 16 208 #define AON_RTC_EVFLAGS_CH2_M 0x00010000 209 #define AON_RTC_EVFLAGS_CH2_S 16 210 211 // Field: [8] CH1 212 // 213 // Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: 214 // - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP 215 // value. 216 // - CHCTL.CH1_CAPT_EN = 1 and capture occurs. 217 // 218 // An event will be scheduled to occur as soon as possible when writing to 219 // CH1CMP provided that the channel is enabled, in compare mode and the new 220 // value matches any time between next RTC value and 1 second in the past. 221 // 222 // Writing 1 clears this flag. Note that a new event can not occur on this 223 // channel in first 2 SCLK_LF cycles after a clearance. 224 #define AON_RTC_EVFLAGS_CH1 0x00000100 225 #define AON_RTC_EVFLAGS_CH1_BITN 8 226 #define AON_RTC_EVFLAGS_CH1_M 0x00000100 227 #define AON_RTC_EVFLAGS_CH1_S 8 228 229 // Field: [0] CH0 230 // 231 // Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or 232 // passes the CH0CMP value. 233 // 234 // An event will be scheduled to occur as soon as possible when writing to 235 // CH0CMP provided that the channels is enabled and the new value matches any 236 // time between next RTC value and 1 second in the past. 237 // 238 // Writing 1 clears this flag. Note that a new event can not occur on this 239 // channel in first 2 SCLK_LF cycles after a clearance. 240 #define AON_RTC_EVFLAGS_CH0 0x00000001 241 #define AON_RTC_EVFLAGS_CH0_BITN 0 242 #define AON_RTC_EVFLAGS_CH0_M 0x00000001 243 #define AON_RTC_EVFLAGS_CH0_S 0 244 245 //***************************************************************************** 246 // 247 // Register: AON_RTC_O_SEC 248 // 249 //***************************************************************************** 250 // Field: [31:0] VALUE 251 // 252 // Unsigned integer representing Real Time Clock in seconds. 253 // 254 // When reading this register the content of SUBSEC.VALUE is simultaneously 255 // latched. A consistent reading of the combined Real Time Clock can be 256 // obtained by first reading this register, then reading SUBSEC register. 257 #define AON_RTC_SEC_VALUE_W 32 258 #define AON_RTC_SEC_VALUE_M 0xFFFFFFFF 259 #define AON_RTC_SEC_VALUE_S 0 260 261 //***************************************************************************** 262 // 263 // Register: AON_RTC_O_SUBSEC 264 // 265 //***************************************************************************** 266 // Field: [31:0] VALUE 267 // 268 // Unsigned integer representing Real Time Clock in fractions of a second 269 // (VALUE/2^32 seconds) at the time when SEC register was read. 270 // 271 // Examples : 272 // - 0x0000_0000 = 0.0 sec 273 // - 0x4000_0000 = 0.25 sec 274 // - 0x8000_0000 = 0.5 sec 275 // - 0xC000_0000 = 0.75 sec 276 #define AON_RTC_SUBSEC_VALUE_W 32 277 #define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF 278 #define AON_RTC_SUBSEC_VALUE_S 0 279 280 //***************************************************************************** 281 // 282 // Register: AON_RTC_O_SUBSECINC 283 // 284 //***************************************************************************** 285 // Field: [23:0] VALUEINC 286 // 287 // This value compensates for a SCLK_LF clock which has an offset from 32768 288 // Hz. 289 // 290 // The compensation value can be found as 2^38 / freq, where freq is SCLK_LF 291 // clock frequency in Hertz 292 // 293 // This value is added to SUBSEC.VALUE on every cycle, and carry of this is 294 // added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with 295 // SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a 296 // hidden 6-bit register that generates a carry into the above mentioned 297 // addition on overflow. 298 // The default value corresponds to incrementing by precisely 1/32768 of a 299 // second. 300 // 301 // NOTE: This register is read only. Modification of the register value must be 302 // done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and 303 // AUX_WUC:RTCSUBSECINCCTL 304 #define AON_RTC_SUBSECINC_VALUEINC_W 24 305 #define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF 306 #define AON_RTC_SUBSECINC_VALUEINC_S 0 307 308 //***************************************************************************** 309 // 310 // Register: AON_RTC_O_CHCTL 311 // 312 //***************************************************************************** 313 // Field: [18] CH2_CONT_EN 314 // 315 // Set to enable continuous operation of Channel 2 316 #define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 317 #define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 318 #define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 319 #define AON_RTC_CHCTL_CH2_CONT_EN_S 18 320 321 // Field: [16] CH2_EN 322 // 323 // RTC Channel 2 Enable 324 // 325 // 0: Disable RTC Channel 2 326 // 1: Enable RTC Channel 2 327 #define AON_RTC_CHCTL_CH2_EN 0x00010000 328 #define AON_RTC_CHCTL_CH2_EN_BITN 16 329 #define AON_RTC_CHCTL_CH2_EN_M 0x00010000 330 #define AON_RTC_CHCTL_CH2_EN_S 16 331 332 // Field: [9] CH1_CAPT_EN 333 // 334 // Set Channel 1 mode 335 // 336 // 0: Compare mode (default) 337 // 1: Capture mode 338 #define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 339 #define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 340 #define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 341 #define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 342 343 // Field: [8] CH1_EN 344 // 345 // RTC Channel 1 Enable 346 // 347 // 0: Disable RTC Channel 1 348 // 1: Enable RTC Channel 1 349 #define AON_RTC_CHCTL_CH1_EN 0x00000100 350 #define AON_RTC_CHCTL_CH1_EN_BITN 8 351 #define AON_RTC_CHCTL_CH1_EN_M 0x00000100 352 #define AON_RTC_CHCTL_CH1_EN_S 8 353 354 // Field: [0] CH0_EN 355 // 356 // RTC Channel 0 Enable 357 // 358 // 0: Disable RTC Channel 0 359 // 1: Enable RTC Channel 0 360 #define AON_RTC_CHCTL_CH0_EN 0x00000001 361 #define AON_RTC_CHCTL_CH0_EN_BITN 0 362 #define AON_RTC_CHCTL_CH0_EN_M 0x00000001 363 #define AON_RTC_CHCTL_CH0_EN_S 0 364 365 //***************************************************************************** 366 // 367 // Register: AON_RTC_O_CH0CMP 368 // 369 //***************************************************************************** 370 // Field: [31:0] VALUE 371 // 372 // RTC Channel 0 compare value. 373 // 374 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 375 // the compare value. 376 // 377 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 378 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 379 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 380 // exciting the compare value. 381 // 382 // Writing to this register can trigger an immediate*) event in case the new 383 // compare value matches a Real Time Clock value from 1 second in the past up 384 // till current Real Time Clock value. 385 // 386 // Example: 387 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 388 // 389 // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to 390 // synchronization. 391 #define AON_RTC_CH0CMP_VALUE_W 32 392 #define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF 393 #define AON_RTC_CH0CMP_VALUE_S 0 394 395 //***************************************************************************** 396 // 397 // Register: AON_RTC_O_CH1CMP 398 // 399 //***************************************************************************** 400 // Field: [31:0] VALUE 401 // 402 // RTC Channel 1 compare value. 403 // 404 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 405 // the compare value. 406 // 407 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 408 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 409 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 410 // exciting the compare value. 411 // 412 // Writing to this register can trigger an immediate*) event in case the new 413 // compare value matches a Real Time Clock value from 1 second in the past up 414 // till current Real Time Clock value. 415 // 416 // Example: 417 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 418 // 419 // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to 420 // synchronization. 421 #define AON_RTC_CH1CMP_VALUE_W 32 422 #define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF 423 #define AON_RTC_CH1CMP_VALUE_S 0 424 425 //***************************************************************************** 426 // 427 // Register: AON_RTC_O_CH2CMP 428 // 429 //***************************************************************************** 430 // Field: [31:0] VALUE 431 // 432 // RTC Channel 2 compare value. 433 // 434 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 435 // the compare value. 436 // 437 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 438 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 439 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 440 // exciting the compare value. 441 // 442 // Writing to this register can trigger an immediate*) event in case the new 443 // compare value matches a Real Time Clock value from 1 second in the past up 444 // till current Real Time Clock value. 445 // 446 // Example: 447 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 448 // 449 // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to 450 // synchronization. 451 #define AON_RTC_CH2CMP_VALUE_W 32 452 #define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF 453 #define AON_RTC_CH2CMP_VALUE_S 0 454 455 //***************************************************************************** 456 // 457 // Register: AON_RTC_O_CH2CMPINC 458 // 459 //***************************************************************************** 460 // Field: [31:0] VALUE 461 // 462 // If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every 463 // channel 2 compare event. 464 #define AON_RTC_CH2CMPINC_VALUE_W 32 465 #define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF 466 #define AON_RTC_CH2CMPINC_VALUE_S 0 467 468 //***************************************************************************** 469 // 470 // Register: AON_RTC_O_CH1CAPT 471 // 472 //***************************************************************************** 473 // Field: [31:16] SEC 474 // 475 // Value of SEC.VALUE bits 15:0 at capture time. 476 #define AON_RTC_CH1CAPT_SEC_W 16 477 #define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 478 #define AON_RTC_CH1CAPT_SEC_S 16 479 480 // Field: [15:0] SUBSEC 481 // 482 // Value of SUBSEC.VALUE bits 31:16 at capture time. 483 #define AON_RTC_CH1CAPT_SUBSEC_W 16 484 #define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF 485 #define AON_RTC_CH1CAPT_SUBSEC_S 0 486 487 //***************************************************************************** 488 // 489 // Register: AON_RTC_O_SYNC 490 // 491 //***************************************************************************** 492 // Field: [0] WBUSY 493 // 494 // This register will always return 0,- however it will not return the value 495 // until there are no outstanding write requests between MCU and AON 496 // 497 // Note: Writing to this register prior to reading will force a wait until next 498 // SCLK_LF edge. This is recommended for syncing read registers from AON when 499 // waking up from sleep 500 // Failure to do so may result in reading AON values from prior to going to 501 // sleep 502 #define AON_RTC_SYNC_WBUSY 0x00000001 503 #define AON_RTC_SYNC_WBUSY_BITN 0 504 #define AON_RTC_SYNC_WBUSY_M 0x00000001 505 #define AON_RTC_SYNC_WBUSY_S 0 506 507 508 #endif // __AON_RTC__ 509