1 /****************************************************************************** 2 * Filename: hw_aon_sysctl_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_SYSCTL_H__ 38 #define __HW_AON_SYSCTL_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_SYSCTL component 44 // 45 //***************************************************************************** 46 // Power Management 47 #define AON_SYSCTL_O_PWRCTL 0x00000000 48 49 // Reset Management 50 #define AON_SYSCTL_O_RESETCTL 0x00000004 51 52 // Sleep Mode 53 #define AON_SYSCTL_O_SLEEPCTL 0x00000008 54 55 //***************************************************************************** 56 // 57 // Register: AON_SYSCTL_O_PWRCTL 58 // 59 //***************************************************************************** 60 // Field: [2] DCDC_ACTIVE 61 // 62 // Select to use DCDC regulator for VDDR in active mode 63 // 64 // 0: Use GLDO for regulation of VDDRin active mode. 65 // 1: Use DCDC for regulation of VDDRin active mode. 66 #define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 67 #define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 68 #define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 69 #define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 70 71 // Field: [1] EXT_REG_MODE 72 // 73 // Status of source for VDDRsupply: 74 // 75 // 0: DCDC/GLDO are generating VDDR 76 // 1: DCDC/GLDO are bypassed, external regulator supplies VDDR 77 #define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 78 #define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 79 #define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 80 #define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 81 82 // Field: [0] DCDC_EN 83 // 84 // Select to use DCDC regulator during recharge of VDDR 85 // 86 // 0: Use GLDO for recharge of VDDR 87 // 1: Use DCDC for recharge of VDDR 88 // 89 // Note: This bitfield should be set to the same as DCDC_ACTIVE 90 #define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 91 #define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 92 #define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 93 #define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 94 95 //***************************************************************************** 96 // 97 // Register: AON_SYSCTL_O_RESETCTL 98 // 99 //***************************************************************************** 100 // Field: [31] SYSRESET 101 // 102 // Cold reset register. Writing 1 to this bitfield will reset the entire chip 103 // and cause boot code to run again. 104 // 105 // 0: No effect 106 // 1: Generate system reset. Appears as SYSRESET in RESET_SRC. 107 #define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 108 #define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 109 #define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 110 #define AON_SYSCTL_RESETCTL_SYSRESET_S 31 111 112 // Field: [25] BOOT_DET_1_CLR 113 // 114 // Internal. Only to be used through TI provided API. 115 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 116 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 117 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 118 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 119 120 // Field: [24] BOOT_DET_0_CLR 121 // 122 // Internal. Only to be used through TI provided API. 123 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 124 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 125 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 126 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 127 128 // Field: [17] BOOT_DET_1_SET 129 // 130 // Internal. Only to be used through TI provided API. 131 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 132 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 133 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 134 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 135 136 // Field: [16] BOOT_DET_0_SET 137 // 138 // Internal. Only to be used through TI provided API. 139 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 140 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 141 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 142 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 143 144 // Field: [15] WU_FROM_SD 145 // 146 // A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from 147 // SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin 148 // being forced low) 149 // 150 // Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup 151 // sources. 152 // 153 // 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 154 // 1: A wakeup has occurred from SHUTDOWN 155 // 156 // Note: This flag can not be cleared and will therefor remain valid untill 157 // poweroff/reset 158 #define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 159 #define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 160 #define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 161 #define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 162 163 // Field: [14] GPIO_WU_FROM_SD 164 // 165 // A wakeup from SHUTDOWN on an IO event has occurred 166 // 167 // Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup 168 // sources. 169 // 170 // 0: The wakeup did not occur from SHUTDOWN on an IO event 171 // 1: A wakeup from SHUTDOWN occurred from an IO event 172 // 173 // The case where WU_FROM_SD is asserted but this bitfield is not asserted will 174 // only occur in a debug session. The boot code will not proceed with wakeup 175 // from SHUTDOWN procedure until this bitfield is asserted as well. 176 // 177 // Note: This flag can not be cleared and will therefor remain valid untill 178 // poweroff/reset 179 #define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 180 #define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 181 #define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 182 #define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 183 184 // Field: [13] BOOT_DET_1 185 // 186 // Internal. Only to be used through TI provided API. 187 #define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 188 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 189 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 190 #define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 191 192 // Field: [12] BOOT_DET_0 193 // 194 // Internal. Only to be used through TI provided API. 195 #define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 196 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 197 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 198 #define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 199 200 // Field: [11] VDDS_LOSS_EN_OVR 201 // 202 // Override of VDDS_LOSS_EN 203 // 204 // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 205 // 1: Brown out detect of VDDS generates system reset (regardless of 206 // VDDS_LOSS_EN) 207 // 208 // This bit can be locked 209 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 210 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 211 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 212 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 213 214 // Field: [10] VDDR_LOSS_EN_OVR 215 // 216 // Override of VDDR_LOSS_EN 217 // 218 // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 219 // 1: Brown out detect of VDDR generates system reset (regardless of 220 // VDDR_LOSS_EN) 221 // 222 // This bit can be locked 223 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 224 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 225 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 226 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 227 228 // Field: [9] VDD_LOSS_EN_OVR 229 // 230 // Override of VDD_LOSS_EN 231 // 232 // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 233 // 1: Brown out detect of VDD generates system reset (regardless of 234 // VDD_LOSS_EN) 235 // 236 // This bit can be locked 237 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 238 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 239 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 240 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 241 242 // Field: [7] VDDS_LOSS_EN 243 // 244 // Controls reset generation in case VDDS is lost 245 // 246 // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 247 // 1: Brown out detect of VDDS generates system reset 248 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 249 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 250 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 251 #define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 252 253 // Field: [6] VDDR_LOSS_EN 254 // 255 // Controls reset generation in case VDDR is lost 256 // 257 // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 258 // 1: Brown out detect of VDDR generates system reset 259 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 260 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 261 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 262 #define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 263 264 // Field: [5] VDD_LOSS_EN 265 // 266 // Controls reset generation in case VDD is lost 267 // 268 // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 269 // 1: Brown out detect of VDD generates system reset 270 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 271 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 272 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 273 #define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 274 275 // Field: [4] CLK_LOSS_EN 276 // 277 // Controls reset generation in case SCLK_LF is lost. (provided that clock 278 // loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) 279 // 280 // Note: Clock loss reset generation must be disabled before SCLK_LF clock 281 // source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled 282 // untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do 283 // so may result in a spurious system reset. Clock loss reset generation can be 284 // disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN 285 // 286 // 0: Clock loss is ignored 287 // 1: Clock loss generates system reset 288 #define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 289 #define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 290 #define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 291 #define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 292 293 // Field: [3:1] RESET_SRC 294 // 295 // Shows the source of the last system reset: 296 // Occurrence of one of the reset sources may trigger several other reset 297 // sources as essential parts of the system are undergoing reset. This field 298 // will report the root cause of the reset (not the other resets that are 299 // consequence of the system reset). 300 // To support this feature the actual register is not captured before the reset 301 // source being released. If a new reset source is triggered, in a window of 302 // four 32 kHz periods after the previous has been released, this register 303 // may indicate Power on reset as source. 304 // ENUMs: 305 // WARMRESET Software reset via PRCM warm reset request 306 // SYSRESET Software reset via SYSRESET register 307 // CLK_LOSS Clock loss detect 308 // VDDR_LOSS Brown out detect on VDDR 309 // VDD_LOSS Brown out detect on VDD 310 // VDDS_LOSS Brown out detect on VDDS 311 // PIN_RESET Reset pin 312 // PWR_ON Power on reset 313 #define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 314 #define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E 315 #define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 316 #define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E 317 #define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C 318 #define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A 319 #define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 320 #define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 321 #define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 322 #define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 323 #define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 324 325 //***************************************************************************** 326 // 327 // Register: AON_SYSCTL_O_SLEEPCTL 328 // 329 //***************************************************************************** 330 // Field: [0] IO_PAD_SLEEP_DIS 331 // 332 // Controls the I/O pad sleep mode. The boot code will set this bitfield 333 // automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set 334 // ). 335 // 336 // 0: I/O pad sleep mode is enabled, ie all pads are latched and can not 337 // toggle. 338 // 1: I/O pad sleep mode is disabled 339 // 340 // Application software may want to reconfigure the state for all IO's before 341 // setting this bitfield upon waking up from a SHUTDOWN. 342 #define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 343 #define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 344 #define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 345 #define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 346 347 348 #endif // __AON_SYSCTL__ 349