1 /****************************************************************************** 2 * Filename: hw_aux_tdc_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_TDC_H__ 38 #define __HW_AUX_TDC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_TDC component 44 // 45 //***************************************************************************** 46 // Control 47 #define AUX_TDC_O_CTL 0x00000000 48 49 // Status 50 #define AUX_TDC_O_STAT 0x00000004 51 52 // Result 53 #define AUX_TDC_O_RESULT 0x00000008 54 55 // Saturation Configuration 56 #define AUX_TDC_O_SATCFG 0x0000000C 57 58 // Trigger Source 59 #define AUX_TDC_O_TRIGSRC 0x00000010 60 61 // Trigger Counter 62 #define AUX_TDC_O_TRIGCNT 0x00000014 63 64 // Trigger Counter Load 65 #define AUX_TDC_O_TRIGCNTLOAD 0x00000018 66 67 // Trigger Counter Configuration 68 #define AUX_TDC_O_TRIGCNTCFG 0x0000001C 69 70 // Prescaler Control 71 #define AUX_TDC_O_PRECTL 0x00000020 72 73 // Prescaler Counter 74 #define AUX_TDC_O_PRECNT 0x00000024 75 76 //***************************************************************************** 77 // 78 // Register: AUX_TDC_O_CTL 79 // 80 //***************************************************************************** 81 // Field: [1:0] CMD 82 // 83 // TDC command strobes 84 // ENUMs: 85 // ABORT This command forces the TDC back to IDLE state 86 // RUN This command makes the TDC FSM start and stop 87 // counting asynchronously. TDC measurement may 88 // start immediately if start is high and hence it 89 // may not give precise edge to edge measurements. 90 // Only recommended when start pulse is guaranteed 91 // to arrive at least 7 clock periods after the 92 // command 93 // RUN_SYNC_START This command makes the TDC FSM start counting 94 // synchronously to the first rising edge that 95 // follows a required falling edge of the start 96 // event. This guarantees an edge triggered start 97 // and is recommended for frequency measurements. 98 // A falling edge of the start event may be missed 99 // if the command is issued close to it in time, 100 // but the TDC will catch later falling edges and 101 // guarantee that a measurement starts 102 // synchronously to the rising edge of the start 103 // event 104 // CLR_RESULT This command clears STAT.SAT, STAT.DONE and 105 // results. Note: This is not needed as 106 // prerequisite for a measurement. Reliable clear 107 // is only guaranteed from IDLE state 108 #define AUX_TDC_CTL_CMD_W 2 109 #define AUX_TDC_CTL_CMD_M 0x00000003 110 #define AUX_TDC_CTL_CMD_S 0 111 #define AUX_TDC_CTL_CMD_ABORT 0x00000003 112 #define AUX_TDC_CTL_CMD_RUN 0x00000002 113 #define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 114 #define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 115 116 //***************************************************************************** 117 // 118 // Register: AUX_TDC_O_STAT 119 // 120 //***************************************************************************** 121 // Field: [7] SAT 122 // 123 // Saturation flag for TDC measurement 124 // 125 // 0: Conversion has not saturated 126 // 1: Conversion stopped due to saturation 127 // 128 // This field is cleared when starting new measurement or setting CTL.CMD to 129 // CLR_RESULT 130 #define AUX_TDC_STAT_SAT 0x00000080 131 #define AUX_TDC_STAT_SAT_BITN 7 132 #define AUX_TDC_STAT_SAT_M 0x00000080 133 #define AUX_TDC_STAT_SAT_S 7 134 135 // Field: [6] DONE 136 // 137 // Measurement complete flag 138 // 139 // 0: Measurement not yet complete 140 // 1: Measurement complete 141 // 142 // This field is cleared when starting new measurement or setting CTL.CMD to 143 // CLR_RESULT 144 #define AUX_TDC_STAT_DONE 0x00000040 145 #define AUX_TDC_STAT_DONE_BITN 6 146 #define AUX_TDC_STAT_DONE_M 0x00000040 147 #define AUX_TDC_STAT_DONE_S 6 148 149 // Field: [5:0] STATE 150 // 151 // TDC internal state machine status 152 // ENUMs: 153 // FORCE_STOP Current state is TDC_FORCESTOP 154 // START_FALL Current state is TDC_WAIT_STARTFALL 155 // WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE 156 // POR Current state is TDC_STATE_POR 157 // GET_RESULT Current state is TDC_STATE_GETRESULTS 158 // WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN 159 // WAIT_STOP Current state is TDC_STATE_WAIT_STOP 160 // CLR_CNT Current state is TDC_STATE_CLRCNT 161 // IDLE Current state is TDC_STATE_IDLE 162 // WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN 163 // WAIT_START Current state is TDC_STATE_WAIT_START 164 #define AUX_TDC_STAT_STATE_W 6 165 #define AUX_TDC_STAT_STATE_M 0x0000003F 166 #define AUX_TDC_STAT_STATE_S 0 167 #define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E 168 #define AUX_TDC_STAT_STATE_START_FALL 0x0000001E 169 #define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 170 #define AUX_TDC_STAT_STATE_POR 0x0000000F 171 #define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E 172 #define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C 173 #define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 174 #define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 175 #define AUX_TDC_STAT_STATE_IDLE 0x00000006 176 #define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 177 #define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 178 179 //***************************************************************************** 180 // 181 // Register: AUX_TDC_O_RESULT 182 // 183 //***************************************************************************** 184 // Field: [24:0] VALUE 185 // 186 // Result of the TDC conversion. The result is in clock edges of the clock 187 // selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges 188 // are counted. 189 // 190 // When saturating the result is slightly higher than the saturation limit, 191 // since it takes a non-zero time to stop the measurement. The highest 192 // saturation limit is 24 bits (see SATCFG.LIMIT) so maximum value of VALUE is 193 // hence slightly above 2^24. 194 #define AUX_TDC_RESULT_VALUE_W 25 195 #define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF 196 #define AUX_TDC_RESULT_VALUE_S 0 197 198 //***************************************************************************** 199 // 200 // Register: AUX_TDC_O_SATCFG 201 // 202 //***************************************************************************** 203 // Field: [3:0] LIMIT 204 // 205 // Select when the TDC times out. Values not enumerated are not supported 206 // ENUMs: 207 // R24 Result bit 24 : TDC saturates and stops when 208 // RESULT.VALUE[24] is set. The flag STAT.SAT is 209 // set when the timer saturates. 210 // R23 Result bit 23 : TDC saturates and stops when 211 // RESULT.VALUE[23] is set. The flag STAT.SAT is 212 // set when the timer saturates. 213 // R22 Result bit 22 : TDC saturates and stops when 214 // RESULT.VALUE[22] is set. The flag STAT.SAT is 215 // set when the timer saturates. 216 // R21 Result bit 21 : TDC saturates and stops when 217 // RESULT.VALUE[21] is set. The flag STAT.SAT is 218 // set when the timer saturates. 219 // R20 Result bit 20 : TDC saturates and stops when 220 // RESULT.VALUE[20] is set. The flag STAT.SAT is 221 // set when the timer saturates. 222 // R19 Result bit 19 : TDC saturates and stops when 223 // RESULT.VALUE[19] is set. The flag STAT.SAT is 224 // set when the timer saturates. 225 // R18 Result bit 18 : TDC saturates and stops when 226 // RESULT.VALUE[18] is set. The flag STAT.SAT is 227 // set when the timer saturates. 228 // R17 Result bit 17 : TDC saturates and stops when 229 // RESULT.VALUE[17] is set. The flag STAT.SAT is 230 // set when the timer saturates. 231 // R16 Result bit 16 : TDC saturates and stops when 232 // RESULT.VALUE[16] is set. The flag STAT.SAT is 233 // set when the timer saturates. 234 // R15 Result bit 15 : TDC saturates and stops when 235 // RESULT.VALUE[15] is set. The flag STAT.SAT is 236 // set when the timer saturates. 237 // R14 Result bit 14 : TDC saturates and stops when 238 // RESULT.VALUE[14] is set. The flag STAT.SAT is 239 // set when the timer saturates. 240 // R13 Result bit 13 : TDC saturates and stops when 241 // RESULT.VALUE[13] is set. The flag STAT.SAT is 242 // set when the timer saturates. 243 // R12 Result bit 12 : TDC saturates and stops when 244 // RESULT.VALUE[12] is set. The flag STAT.SAT is 245 // set when the timer saturates. 246 #define AUX_TDC_SATCFG_LIMIT_W 4 247 #define AUX_TDC_SATCFG_LIMIT_M 0x0000000F 248 #define AUX_TDC_SATCFG_LIMIT_S 0 249 #define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F 250 #define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E 251 #define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D 252 #define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C 253 #define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B 254 #define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A 255 #define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 256 #define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 257 #define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 258 #define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 259 #define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 260 #define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 261 #define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 262 263 //***************************************************************************** 264 // 265 // Register: AUX_TDC_O_TRIGSRC 266 // 267 //***************************************************************************** 268 // Field: [13] STOP_POL 269 // 270 // Polarity of stop signal. Note! Must not be changed if STAT.STATE is not 271 // IDLE 272 // ENUMs: 273 // LOW TDC stops when low level is detected 274 // HIGH TDC stops when high level is detected 275 #define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 276 #define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 277 #define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 278 #define AUX_TDC_TRIGSRC_STOP_POL_S 13 279 #define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 280 #define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 281 282 // Field: [12:8] STOP_SRC 283 // 284 // Selects the asynchronous stop signal Note! Must not be changed if 285 // STAT.STATE is not IDLE 286 // ENUMs: 287 // TDC_PRE Selects TDC_PRE 288 // MCU_EV Selects MCU_EV 289 // ACLK_REF Selects ACLK_REF 290 // AUXIO15 Selects AUXIO15 291 // AUXIO14 Selects AUXIO14 292 // AUXIO13 Selects AUXIO13 293 // AUXIO12 Selects AUXIO12 294 // AUXIO11 Selects AUXIO11 295 // AUXIO10 Selects AUXIO10 296 // AUXIO9 Selects AUXIO9 297 // AUXIO8 Selects AUXIO8 298 // AUXIO7 Selects AUXIO7 299 // AUXIO6 Selects AUXIO6 300 // AUXIO5 Selects AUXIO5 301 // AUXIO4 Selects AUXIO4 302 // AUXIO3 Selects AUXIO3 303 // AUXIO2 Selects AUXIO2 304 // AUXIO1 Selects AUXIO1 305 // AUXIO0 Selects AUXIO0 306 // AON_PROG_WU Selects AON_PROG_WU 307 // AON_SW Selects AON_SW 308 // OBSMUX1 Selects OBSMUX1 309 // OBSMUX0 Selects OBSMUX0 310 // ADC_FIFO_ALMOST_FULL Selects ADC_FIFO_ALMOST_FULL 311 // ADC_DONE Selects ADC_DONE 312 // SMPH_AUTOTAKE_DONE Selects SMPH_AUTOTAKE_DONE 313 // TIMER1_EV Selects TIMER1_EV 314 // TIMER0_EV Selects TIMER0_EV 315 // ISRC_RESET Selects ISRC_RESET 316 // AUX_COMPB Selects AUX_COMPB 317 // AUX_COMPA Selects AUX_COMPA 318 // AON_RTC_CH2 Selects AON_RTC_CH2 319 #define AUX_TDC_TRIGSRC_STOP_SRC_W 5 320 #define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 321 #define AUX_TDC_TRIGSRC_STOP_SRC_S 8 322 #define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 323 #define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 324 #define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 325 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 326 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 327 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 328 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 329 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 330 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 331 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 332 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 333 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 334 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 335 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 336 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 337 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 338 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 339 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 340 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 341 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 342 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 343 #define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 344 #define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 345 #define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 346 #define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 347 #define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 348 #define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 349 #define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 350 #define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 351 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 352 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 353 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 354 355 // Field: [5] START_POL 356 // 357 // Polarity of start signal. Note! Must not be changed if STAT.STATE is not 358 // IDLE 359 // ENUMs: 360 // LOW TDC starts when low level is detected 361 // HIGH TDC starts when high level is detected 362 #define AUX_TDC_TRIGSRC_START_POL 0x00000020 363 #define AUX_TDC_TRIGSRC_START_POL_BITN 5 364 #define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 365 #define AUX_TDC_TRIGSRC_START_POL_S 5 366 #define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 367 #define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 368 369 // Field: [4:0] START_SRC 370 // 371 // Selects the asynchronous start signal Note! Must not be changed if 372 // STAT.STATE is not IDLE 373 // ENUMs: 374 // TDC_PRE Selects TDC_PRE 375 // MCU_EV Selects MCU_EV 376 // ACLK_REF Selects ACLK_REF 377 // AUXIO15 Selects AUXIO15 378 // AUXIO14 Selects AUXIO14 379 // AUXIO13 Selects AUXIO13 380 // AUXIO12 Selects AUXIO12 381 // AUXIO11 Selects AUXIO11 382 // AUXIO10 Selects AUXIO10 383 // AUXIO9 Selects AUXIO9 384 // AUXIO8 Selects AUXIO8 385 // AUXIO7 Selects AUXIO7 386 // AUXIO6 Selects AUXIO6 387 // AUXIO5 Selects AUXIO5 388 // AUXIO4 Selects AUXIO4 389 // AUXIO3 Selects AUXIO3 390 // AUXIO2 Selects AUXIO2 391 // AUXIO1 Selects AUXIO1 392 // AUXIO0 Selects AUXIO0 393 // AON_PROG_WU Selects AON_PROG_WU 394 // AON_SW Selects AON_SW 395 // OBSMUX1 Selects OBSMUX1 396 // OBSMUX0 Selects OBSMUX0 397 // ADC_FIFO_ALMOST_FULL Selects ADC_FIFO_ALMOST_FULL 398 // ADC_DONE Selects ADC_DONE 399 // SMPH_AUTOTAKE_DONE Selects SMPH_AUTOTAKE_DONE 400 // TIMER1_EV Selects TIMER1_EV 401 // TIMER0_EV Selects TIMER0_EV 402 // ISRC_RESET Selects ISRC_RESET 403 // AUX_COMPB Selects AUX_COMPB 404 // AUX_COMPA Selects AUX_COMPA 405 // AON_RTC_CH2 Selects AON_RTC_CH2 406 #define AUX_TDC_TRIGSRC_START_SRC_W 5 407 #define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F 408 #define AUX_TDC_TRIGSRC_START_SRC_S 0 409 #define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F 410 #define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E 411 #define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D 412 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C 413 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B 414 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A 415 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 416 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 417 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 418 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 419 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 420 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 421 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 422 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 423 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 424 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 425 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F 426 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E 427 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D 428 #define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C 429 #define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B 430 #define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A 431 #define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 432 #define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 433 #define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 434 #define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 435 #define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 436 #define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 437 #define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 438 #define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 439 #define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 440 #define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 441 442 //***************************************************************************** 443 // 444 // Register: AUX_TDC_O_TRIGCNT 445 // 446 //***************************************************************************** 447 // Field: [15:0] CNT 448 // 449 // Remaining number of stop events that will be ignored. Writing to this 450 // register updates the value. The CNT will be loaded with the value of 451 // TRIGCNTLOAD.CNT at the start of every measurement. 452 // 453 // When the stop counter is enabled the first CNT-1 stop events is ignored 454 // after which the TDC will stop measurement on event number CNT 455 // 456 // Note! Must not be changed if STAT.STATE is not IDLE 457 #define AUX_TDC_TRIGCNT_CNT_W 16 458 #define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF 459 #define AUX_TDC_TRIGCNT_CNT_S 0 460 461 //***************************************************************************** 462 // 463 // Register: AUX_TDC_O_TRIGCNTLOAD 464 // 465 //***************************************************************************** 466 // Field: [15:0] CNT 467 // 468 // Selects the number of stop events that will be ignored by the TDC. This can 469 // be used to measure multiple periods of a clock signal. The value written to 470 // this field is loaded into the stop counter at the start of each measurement. 471 // 472 // Note! Both values 0 and 1 will make the TDC stop on the first event after 473 // the start event 474 // 475 // Note! Must not be changed if STAT.STATE is not IDLE 476 #define AUX_TDC_TRIGCNTLOAD_CNT_W 16 477 #define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF 478 #define AUX_TDC_TRIGCNTLOAD_CNT_S 0 479 480 //***************************************************************************** 481 // 482 // Register: AUX_TDC_O_TRIGCNTCFG 483 // 484 //***************************************************************************** 485 // Field: [0] EN 486 // 487 // Stop counter enable 488 // 489 // 0: Stop counter is disabled 490 // 1: Stop counter is enabled 491 #define AUX_TDC_TRIGCNTCFG_EN 0x00000001 492 #define AUX_TDC_TRIGCNTCFG_EN_BITN 0 493 #define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 494 #define AUX_TDC_TRIGCNTCFG_EN_S 0 495 496 //***************************************************************************** 497 // 498 // Register: AUX_TDC_O_PRECTL 499 // 500 //***************************************************************************** 501 // Field: [7] RESET_N 502 // 503 // Prescaler reset control 504 // 505 // 0: Prescaler is held in reset 506 // 1: Prescaler is not held in reset 507 #define AUX_TDC_PRECTL_RESET_N 0x00000080 508 #define AUX_TDC_PRECTL_RESET_N_BITN 7 509 #define AUX_TDC_PRECTL_RESET_N_M 0x00000080 510 #define AUX_TDC_PRECTL_RESET_N_S 7 511 512 // Field: [6] RATIO 513 // 514 // Prescaler ratio. This controls how often an event is generated on the 515 // TDC_PRE line. After the prescaler is reset the event output TDC_PRE is 0. 516 // ENUMs: 517 // DIV64 Prescaler divides by 64. A rising edge on the 518 // output is generated for every 64 rising edges 519 // of the input (the output toggles on every 32th 520 // rising edge of the input). . 521 // DIV16 Prescaler divides by 16. A rising edge on the 522 // output is generated for every 16 rising edges 523 // of the input (the output toggles on every 8th 524 // rising edge of the input). 525 #define AUX_TDC_PRECTL_RATIO 0x00000040 526 #define AUX_TDC_PRECTL_RATIO_BITN 6 527 #define AUX_TDC_PRECTL_RATIO_M 0x00000040 528 #define AUX_TDC_PRECTL_RATIO_S 6 529 #define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 530 #define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 531 532 // Field: [4:0] SRC 533 // 534 // Selects event for prescaler to use as input 535 // Note! Only change when prescaler is in reset 536 // ENUMs: 537 // ADC_IRQ 538 // MCU_EV 539 // ACLK_REF 540 // AUXIO15 541 // AUXIO14 542 // AUXIO13 543 // AUXIO12 544 // AUXIO11 545 // AUXIO10 546 // AUXIO9 547 // AUXIO8 548 // AUXIO7 549 // AUXIO6 550 // AUXIO5 551 // AUXIO4 552 // AUXIO3 553 // AUXIO2 554 // AUXIO1 555 // AUXIO0 556 // AON_PROG_WU 557 // AON_SW 558 // OBSMUX1 559 // OBSMUX0 560 // ADC_FIFO_ALMOST_FULL 561 // ADC_DONE 562 // SMPH_AUTOTAKE_DONE 563 // TIMER1_EV 564 // TIMER0_EV 565 // ISRC_RESET 566 // AUX_COMPB 567 // AUX_COMPA 568 // AON_RTC_CH2 569 #define AUX_TDC_PRECTL_SRC_W 5 570 #define AUX_TDC_PRECTL_SRC_M 0x0000001F 571 #define AUX_TDC_PRECTL_SRC_S 0 572 #define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F 573 #define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E 574 #define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D 575 #define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C 576 #define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B 577 #define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A 578 #define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 579 #define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 580 #define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 581 #define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 582 #define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 583 #define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 584 #define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 585 #define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 586 #define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 587 #define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 588 #define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F 589 #define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E 590 #define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D 591 #define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C 592 #define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B 593 #define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A 594 #define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 595 #define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 596 #define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 597 #define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 598 #define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 599 #define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 600 #define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 601 #define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 602 #define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 603 #define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 604 605 //***************************************************************************** 606 // 607 // Register: AUX_TDC_O_PRECNT 608 // 609 //***************************************************************************** 610 // Field: [15:0] CNT 611 // 612 // Writing to this register will latch the contents of the 16 bit prescaler 613 // counter (The value written is don't care). 614 // 615 // Reading will return the latched value. 616 #define AUX_TDC_PRECNT_CNT_W 16 617 #define AUX_TDC_PRECNT_CNT_M 0x0000FFFF 618 #define AUX_TDC_PRECNT_CNT_S 0 619 620 621 #endif // __AUX_TDC__ 622