Searched refs:BASE_CLK_SEL (Results 1 – 7 of 7) sorted by relevance
| /lk-master/platform/lpc43xx/ |
| A D | init.c | 32 writel(BASE_CLK_SEL(CLK_IRC) | BASE_AUTOBLOCK, BASE_M4_CLK); in platform_early_init()
55 writel(BASE_CLK_SEL(CLK_PLL1) | BASE_AUTOBLOCK, BASE_M4_CLK); in platform_early_init()
78 writel(BASE_CLK_SEL(CLK_IDIVE), BASE_OUT_CLK); in platform_early_init()
84 writel(BASE_CLK_SEL(CLK_IDIVA), BASE_OUT_CLK); in platform_early_init()
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| A D | debug.c | 85 writel(BASE_CLK_SEL(CLK_IRC), base_uart_clk[TARGET_DEBUG_UART - 1]); in lpc43xx_debug_early_init()
92 writel(BASE_CLK_SEL(__lpc43xx_main_clock_sel), in lpc43xx_debug_early_init()
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| /lk-master/platform/lpc43xx/include/platform/ |
| A D | lpc43xx-clocks.h | 61 #define BASE_CLK_SEL(n) ((n) << 24) macro
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| /lk-master/app/mdebug/ |
| A D | jtag.c | 71 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in jtag_init()
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| A D | swo-uart1.c | 123 writel(BASE_CLK_SEL(__lpc43xx_main_clock_sel), BASE_UART_CLK); in swo_config()
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| A D | swd-m0sub.c | 98 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in swd_init()
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| A D | swd-sgpio.c | 110 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in sgpio_init()
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Completed in 11 milliseconds