Searched refs:CLK_CTRL_DIVISOR1 (Results 1 – 3 of 3) sorted by relevance
| /lk-master/target/uzed/ |
| A D | target.c | 147 .dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(35) | CLK_CTRL_DIVISOR1(3),
148 .gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
154 .fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
155 .fpga1_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
156 .fpga2_clk = CLK_CTRL_DIVISOR0(30) | CLK_CTRL_DIVISOR1(1),
157 .fpga3_clk = CLK_CTRL_DIVISOR0(20) | CLK_CTRL_DIVISOR1(1),
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| /lk-master/target/zybo/ |
| A D | target.c | 151 .dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(52) | CLK_CTRL_DIVISOR1(2),
152 .gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
158 .fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
159 .fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
160 .fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
161 .fpga3_clk = CLK_CTRL_DIVISOR1(1),
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| /lk-master/platform/zynq/include/platform/ |
| A D | zynq.h | 406 #define CLK_CTRL_DIVISOR1(x) ((x & BIT_MASK(6)) << 20) macro
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