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Searched refs:CSR_OFFSET (Results 1 – 8 of 8) sorted by relevance

/lk-master/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_bkp.c63 #define CSR_OFFSET (BKP_OFFSET + 0x34) macro
65 #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
69 #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
73 #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
A Dstm32f10x_cec.c64 #define CSR_OFFSET (CEC_OFFSET + 0x10) macro
66 #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
70 #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
A Dstm32f10x_pwr.c63 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A Dstm32f10x_rcc.c100 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
102 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/lk-master/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_pwr.c105 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
107 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
112 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
114 #define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
116 #define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
121 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
A Dstm32f4xx_rcc.c110 #define CSR_OFFSET (RCC_OFFSET + 0x74) macro
112 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/lk-master/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dstm32f2xx_pwr.c73 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
75 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
79 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
A Dstm32f2xx_rcc.c108 #define CSR_OFFSET (RCC_OFFSET + 0x74) macro
110 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

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