1 /* 2 * Copyright (c) 2015 Brian Swetland 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 9 #pragma once 10 11 #define SPIFI_CTRL 0x40003000 // Control 12 #define SPIFI_CMD 0x40003004 // Command 13 #define SPIFI_ADDR 0x40003008 // Address 14 #define SPIFI_IDATA 0x4000300C // Intermediate Data 15 #define SPIFI_CLIMIT 0x40003010 // Cache Limit 16 #define SPIFI_DATA 0x40003014 // Data 17 #define SPIFI_MCMD 0x40003018 // Memory Command 18 #define SPIFI_STAT 0x4000301C // Status 19 20 #define CTRL_TIMEOUT(n) ((n) & 0xFFFF) 21 #define CTRL_CSHIGH(n) (((n) & 0xF) << 16) // Minimum /CS high time (serclks - 1) 22 #define CTRL_D_PRFTCH_DIS (1 << 21) // Disable Prefetch of Data 23 #define CTRL_INTEN (1 << 22) // Enable IRQ on end of command 24 #define CTRL_MODE3 (1 << 23) // 0=SCK low after +edge of last bit, 1=high 25 #define CTRL_PRFTCH_DIS (1 << 27) // Disable Prefetch 26 #define CTRL_DUAL (1 << 28) // 0=Quad 1=Dual (bits in "wide" ops) 27 #define CTRL_QUAD (0 << 28) 28 #define CTRL_RFCLK (1 << 29) // 1=sample read data on -edge clock 29 #define CTRL_FBCLK (1 << 30) // use feedback clock from SCK pin for sampling 30 #define CTRL_DMAEN (1 << 31) // enable DMA request output 31 32 #define CMD_DATALEN(n) ((n) & 0x3FFF) 33 #define CMD_POLL (1 << 14) // if set, read byte repeatedly until condition 34 #define CMD_POLLBIT(n) ((n) & 7) // which bit# to check 35 #define CMD_POLLSET (1 << 3) // condition is bit# set 36 #define CMD_POLLCLR (0 << 3) // condition is bit# clear 37 #define CMD_DOUT (1 << 15) // 1=data phase output, 0=data phase input 38 #define CMD_DIN (0 << 15) 39 #define CMD_INTLEN(n) (((n) & 7) << 16) // count of intermediate bytes 40 #define CMD_FF_SERIAL (0 << 19) // all command fields serial 41 #define CMD_FF_WIDE_DATA (1 << 19) // data is wide, all other fields serial 42 #define CMD_FF_SERIAL_OPCODE (2 << 19) // opcode is serial, all other fields wide 43 #define CMD_FF_WIDE (3 << 19) // all command fields wide 44 #define CMD_FR_OP (1 << 21) // frame format: opcode only 45 #define CMD_FR_OP_1B (2 << 21) // opcode, lsb addr 46 #define CMD_FR_OP_2B (3 << 21) // opcode, 2 lsb addr 47 #define CMD_FR_OP_3B (4 << 21) // opcode, 3 lsb addr 48 #define CMD_FR_OP_4B (5 << 21) // opcode, 4b address 49 #define CMD_FR_3B (6 << 21) // 3 lsb addr 50 #define CMD_FR_4B (7 << 21) // 4 lsb addr 51 #define CMD_OPCODE(n) ((n) << 24) 52 53 // MCMD register defines CMD for automatic reads 54 // Similar to CMD, but 55 // DATALEN, POLL, DOUT must be 0 56 57 #define STAT_MCINIT (1 << 0) // set on sw write to MCMD, clear on RST, wr(0) 58 #define STAT_CMD (1 << 1) // set when CMD written, clear on CS, RST 59 #define STAT_RESET (1 << 4) // write 1 to abort current txn or memory mode 60 #define STAT_INTRQ (1 << 5) // read IRQ status, wr(1) to clear 61 62 // 1. Write ADDR 63 // 2. Write CMD 64 // 3. Read/Write DATA necessary number of times to transfer DATALEN bytes 65 // (byte/half/word ops move 1/2/4 bytes at a time) 66 67