1 /****************************************************************************** 2 * Filename: hw_ddi_0_osc_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_DDI_0_OSC_H__ 38 #define __HW_DDI_0_OSC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // DDI_0_OSC component 44 // 45 //***************************************************************************** 46 // Control 0 47 #define DDI_0_OSC_O_CTL0 0x00000000 48 49 // Control 1 50 #define DDI_0_OSC_O_CTL1 0x00000004 51 52 // RADC External Configuration 53 #define DDI_0_OSC_O_RADCEXTCFG 0x00000008 54 55 // Amplitude Compensation Control 56 #define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C 57 58 // Amplitude Compensation Threashold 1 59 #define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 60 61 // Amplitude Compensation Threashold 2 62 #define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 63 64 // Analog Bypass Values 1 65 #define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 66 67 // Internal 68 #define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C 69 70 // Analog Test Control 71 #define DDI_0_OSC_O_ATESTCTL 0x00000020 72 73 // ADC Doubler Nanoamp Control 74 #define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 75 76 // XOSCHF Control 77 #define DDI_0_OSC_O_XOSCHFCTL 0x00000028 78 79 // Low Frequency Oscillator Control 80 #define DDI_0_OSC_O_LFOSCCTL 0x0000002C 81 82 // RCOSCHF Control 83 #define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 84 85 // Status 0 86 #define DDI_0_OSC_O_STAT0 0x00000034 87 88 // Status 1 89 #define DDI_0_OSC_O_STAT1 0x00000038 90 91 // Status 2 92 #define DDI_0_OSC_O_STAT2 0x0000003C 93 94 //***************************************************************************** 95 // 96 // Register: DDI_0_OSC_O_CTL0 97 // 98 //***************************************************************************** 99 // Field: [31] XTAL_IS_24M 100 // 101 // Set based on the accurate high frequency XTAL. 102 // ENUMs: 103 // 24M Internal. Only to be used through TI provided API. 104 // 48M Internal. Only to be used through TI provided API. 105 #define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 106 #define DDI_0_OSC_CTL0_XTAL_IS_24M_BITN 31 107 #define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 108 #define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 109 #define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 110 #define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 111 112 // Field: [29] BYPASS_XOSC_LF_CLK_QUAL 113 // 114 // Internal. Only to be used through TI provided API. 115 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 116 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_BITN 29 117 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 118 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 119 120 // Field: [28] BYPASS_RCOSC_LF_CLK_QUAL 121 // 122 // Internal. Only to be used through TI provided API. 123 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 124 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_BITN 28 125 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 126 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 127 128 // Field: [27:26] DOUBLER_START_DURATION 129 // 130 // Internal. Only to be used through TI provided API. 131 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 132 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 133 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 134 135 // Field: [25] DOUBLER_RESET_DURATION 136 // 137 // Internal. Only to be used through TI provided API. 138 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 139 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_BITN 25 140 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 141 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 142 143 // Field: [22] FORCE_KICKSTART_EN 144 // 145 // Internal. Only to be used through TI provided API. 146 #define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 147 #define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_BITN 22 148 #define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 149 #define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 150 151 // Field: [16] ALLOW_SCLK_HF_SWITCHING 152 // 153 // 0: Default - Switching of HF clock source is disabled . 154 // 1: Allows swtiching of sclk_hf source. 155 // 156 // Provided to prevent switching of the SCLK_HF source when running from flash 157 // (a long period during switching could corrupt flash). When sclk_hf 158 // switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is 159 // changed, but the switch will not occur until this bit is set. This bit 160 // should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING 161 // indicates the new HF clock is ready. When switching completes (also 162 // indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be 163 // disabled to prevent flash corruption. Switching should not be enabled when 164 // running from flash. 165 #define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 166 #define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_BITN 16 167 #define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 168 #define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 169 170 // Field: [14] HPOSC_MODE_EN 171 // 172 // 0: HPOSC mode is not enabled. The high frequency crystal is assumed to be 173 // used as the synth reference clock. 174 // 1: Enables 'HPOSC' mode. When used the high frequency crystal clock is 175 // assumed to be replaced with a HPOSC resonator. The synth reference clock 176 // will come from the HPOSC. **note, FW should set this bit** 177 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 178 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN_BITN 14 179 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 180 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 181 182 // Field: [12] RCOSC_LF_TRIMMED 183 // 184 // Internal. Only to be used through TI provided API. 185 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 186 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_BITN 12 187 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 188 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 189 190 // Field: [11] XOSC_HF_POWER_MODE 191 // 192 // Internal. Only to be used through TI provided API. 193 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 194 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_BITN 11 195 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 196 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 197 198 // Field: [10] XOSC_LF_DIG_BYPASS 199 // 200 // Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf 201 // clock.. 202 // 203 // 0: Use 32kHz XOSC as xosc_lf clock source 204 // 1: Use digital input (from AON) as xosc_lf clock source. 205 // 206 // This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf 207 // as the sclk_lf source. The muxing performed by this bit is not glitch free. 208 // The following procedure should be followed when changing this field to avoid 209 // glitches on sclk_lf.. 210 // 211 // 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock 212 // source. 213 // 2) Set or clear this bit to bypass or not bypass the xosc_lf. 214 // 3) Set SCLK_LF_SRC_SEL to use xosc_lf. 215 // 216 // It is recommended that either the rcosc_hf or xosc_hf (whichever is 217 // currently active) be selected as the source in step 1 above. This provides a 218 // faster clock change. 219 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 220 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_BITN 10 221 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 222 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 223 224 // Field: [9] CLK_LOSS_EN 225 // 226 // Enable clock loss circuit and hence the indicators to system controller. 227 // Checks both SCLK_HF and SCLK_LF clock loss indicators. 228 // 229 // 0: Disable 230 // 1: Enable 231 // 232 // Clock loss detection should be disabled when changing the sclk_lf source. 233 // STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf 234 // source has completed. 235 #define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 236 #define DDI_0_OSC_CTL0_CLK_LOSS_EN_BITN 9 237 #define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 238 #define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 239 240 // Field: [8:7] ACLK_TDC_SRC_SEL 241 // 242 // Source select for aclk_tdc. 243 // 244 // 00: RCOSC_HF (48MHz) 245 // 01: RCOSC_HF (24MHz) 246 // 10: XOSC_HF (24MHz) 247 // 11: Not used 248 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 249 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 250 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 251 252 // Field: [6:5] ACLK_REF_SRC_SEL 253 // 254 // Source select for aclk_ref 255 // 256 // 00: RCOSC_HF desirved (31.25kHz) 257 // 01: XOSC_HF derived (31.25kHz) 258 // 10: RCOSC_LF (32kHz) 259 // 11: XOSC_LF (32.768kHz) 260 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 261 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 262 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 263 264 // Field: [3:2] SCLK_LF_SRC_SEL 265 // 266 // Source select for sclk_lf 267 // ENUMs: 268 // XOSCLF Low frequency XOSC 269 // RCOSCLF Low frequency RCOSC 270 // XOSCHFDLF Low frequency clock derived from High Frequency 271 // XOSC 272 // RCOSCHFDLF Low frequency clock derived from High Frequency 273 // RCOSC 274 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 275 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C 276 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 277 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C 278 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 279 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 280 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 281 282 // Field: [1] SCLK_MF_SRC_SEL 283 // 284 // Internal. Only to be used through TI provided API. 285 // ENUMs: 286 // XCOSCHFDMF Medium frequency clock derived from high frequency 287 // XOSC. 288 // RCOSCHFDMF Internal. Only to be used through TI provided API. 289 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 290 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_BITN 1 291 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 292 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 293 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 294 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 295 296 // Field: [0] SCLK_HF_SRC_SEL 297 // 298 // Source select for sclk_hf 299 // ENUMs: 300 // XOSC High frequency XOSC clk 301 // RCOSC High frequency RCOSC clk 302 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 303 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_BITN 0 304 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 305 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 306 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 307 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 308 309 //***************************************************************************** 310 // 311 // Register: DDI_0_OSC_O_CTL1 312 // 313 //***************************************************************************** 314 // Field: [22:18] RCOSCHFCTRIMFRACT 315 // 316 // Internal. Only to be used through TI provided API. 317 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 318 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 319 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 320 321 // Field: [17] RCOSCHFCTRIMFRACT_EN 322 // 323 // Internal. Only to be used through TI provided API. 324 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 325 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_BITN 17 326 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 327 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 328 329 // Field: [1:0] XOSC_HF_FAST_START 330 // 331 // Internal. Only to be used through TI provided API. 332 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 333 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 334 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 335 336 //***************************************************************************** 337 // 338 // Register: DDI_0_OSC_O_RADCEXTCFG 339 // 340 //***************************************************************************** 341 // Field: [31:22] HPM_IBIAS_WAIT_CNT 342 // 343 // Internal. Only to be used through TI provided API. 344 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 345 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 346 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 347 348 // Field: [21:16] LPM_IBIAS_WAIT_CNT 349 // 350 // Internal. Only to be used through TI provided API. 351 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 352 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 353 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 354 355 // Field: [15:12] IDAC_STEP 356 // 357 // Internal. Only to be used through TI provided API. 358 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 359 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 360 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 361 362 // Field: [11:6] RADC_DAC_TH 363 // 364 // Internal. Only to be used through TI provided API. 365 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 366 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 367 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 368 369 // Field: [5] RADC_MODE_IS_SAR 370 // 371 // Internal. Only to be used through TI provided API. 372 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 373 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_BITN 5 374 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 375 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 376 377 //***************************************************************************** 378 // 379 // Register: DDI_0_OSC_O_AMPCOMPCTL 380 // 381 //***************************************************************************** 382 // Field: [30] AMPCOMP_REQ_MODE 383 // 384 // Internal. Only to be used through TI provided API. 385 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 386 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_BITN 30 387 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 388 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 389 390 // Field: [29:28] AMPCOMP_FSM_UPDATE_RATE 391 // 392 // Internal. Only to be used through TI provided API. 393 // ENUMs: 394 // 250KHZ Internal. Only to be used through TI provided API. 395 // 500KHZ Internal. Only to be used through TI provided API. 396 // 1MHZ Internal. Only to be used through TI provided API. 397 // 2MHZ Internal. Only to be used through TI provided API. 398 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 399 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 400 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 401 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 402 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 403 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 404 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 405 406 // Field: [27] AMPCOMP_SW_CTRL 407 // 408 // Internal. Only to be used through TI provided API. 409 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 410 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_BITN 27 411 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 412 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 413 414 // Field: [26] AMPCOMP_SW_EN 415 // 416 // Internal. Only to be used through TI provided API. 417 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 418 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_BITN 26 419 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 420 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 421 422 // Field: [23:20] IBIAS_OFFSET 423 // 424 // Internal. Only to be used through TI provided API. 425 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 426 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 427 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 428 429 // Field: [19:16] IBIAS_INIT 430 // 431 // Internal. Only to be used through TI provided API. 432 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 433 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 434 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 435 436 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL 437 // 438 // Internal. Only to be used through TI provided API. 439 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 440 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 441 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 442 443 // Field: [7:4] CAP_STEP 444 // 445 // Internal. Only to be used through TI provided API. 446 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 447 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 448 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 449 450 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT 451 // 452 // Internal. Only to be used through TI provided API. 453 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 454 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F 455 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 456 457 //***************************************************************************** 458 // 459 // Register: DDI_0_OSC_O_AMPCOMPTH1 460 // 461 //***************************************************************************** 462 // Field: [23:18] HPMRAMP3_LTH 463 // 464 // Internal. Only to be used through TI provided API. 465 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 466 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 467 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 468 469 // Field: [15:10] HPMRAMP3_HTH 470 // 471 // Internal. Only to be used through TI provided API. 472 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 473 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 474 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 475 476 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT 477 // 478 // Internal. Only to be used through TI provided API. 479 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 480 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 481 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 482 483 // Field: [5:0] HPMRAMP1_TH 484 // 485 // Internal. Only to be used through TI provided API. 486 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 487 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F 488 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 489 490 //***************************************************************************** 491 // 492 // Register: DDI_0_OSC_O_AMPCOMPTH2 493 // 494 //***************************************************************************** 495 // Field: [31:26] LPMUPDATE_LTH 496 // 497 // Internal. Only to be used through TI provided API. 498 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 499 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 500 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 501 502 // Field: [23:18] LPMUPDATE_HTH 503 // 504 // Internal. Only to be used through TI provided API. 505 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 506 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 507 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 508 509 // Field: [15:10] ADC_COMP_AMPTH_LPM 510 // 511 // Internal. Only to be used through TI provided API. 512 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 513 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 514 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 515 516 // Field: [7:2] ADC_COMP_AMPTH_HPM 517 // 518 // Internal. Only to be used through TI provided API. 519 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 520 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC 521 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 522 523 //***************************************************************************** 524 // 525 // Register: DDI_0_OSC_O_ANABYPASSVAL1 526 // 527 //***************************************************************************** 528 // Field: [19:16] XOSC_HF_ROW_Q12 529 // 530 // Internal. Only to be used through TI provided API. 531 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 532 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 533 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 534 535 // Field: [15:0] XOSC_HF_COLUMN_Q12 536 // 537 // Internal. Only to be used through TI provided API. 538 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 539 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF 540 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 541 542 //***************************************************************************** 543 // 544 // Register: DDI_0_OSC_O_ANABYPASSVAL2 545 // 546 //***************************************************************************** 547 // Field: [13:0] XOSC_HF_IBIASTHERM 548 // 549 // Internal. Only to be used through TI provided API. 550 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 551 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF 552 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 553 554 //***************************************************************************** 555 // 556 // Register: DDI_0_OSC_O_ATESTCTL 557 // 558 //***************************************************************************** 559 // Field: [29] SCLK_LF_AUX_EN 560 // 561 // Enable 32 kHz clock to AUX_COMPB. 562 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 563 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_BITN 29 564 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 565 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 566 567 //***************************************************************************** 568 // 569 // Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 570 // 571 //***************************************************************************** 572 // Field: [24] NANOAMP_BIAS_ENABLE 573 // 574 // Internal. Only to be used through TI provided API. 575 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 576 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_BITN 24 577 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 578 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 579 580 // Field: [23] SPARE23 581 // 582 // Software should not rely on the value of a reserved. Writing any other value 583 // than the reset value may result in undefined behavior 584 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 585 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_BITN 23 586 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 587 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 588 589 // Field: [5] ADC_SH_MODE_EN 590 // 591 // Internal. Only to be used through TI provided API. 592 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 593 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_BITN 5 594 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 595 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 596 597 // Field: [4] ADC_SH_VBUF_EN 598 // 599 // Internal. Only to be used through TI provided API. 600 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 601 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_BITN 4 602 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 603 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 604 605 // Field: [1:0] ADC_IREF_CTRL 606 // 607 // Internal. Only to be used through TI provided API. 608 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 609 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 610 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 611 612 //***************************************************************************** 613 // 614 // Register: DDI_0_OSC_O_XOSCHFCTL 615 // 616 //***************************************************************************** 617 // Field: [9:8] PEAK_DET_ITRIM 618 // 619 // Internal. Only to be used through TI provided API. 620 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 621 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 622 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 623 624 // Field: [6] BYPASS 625 // 626 // Internal. Only to be used through TI provided API. 627 #define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 628 #define DDI_0_OSC_XOSCHFCTL_BYPASS_BITN 6 629 #define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 630 #define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 631 632 // Field: [4:2] HP_BUF_ITRIM 633 // 634 // Internal. Only to be used through TI provided API. 635 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 636 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C 637 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 638 639 // Field: [1:0] LP_BUF_ITRIM 640 // 641 // Internal. Only to be used through TI provided API. 642 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 643 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 644 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 645 646 //***************************************************************************** 647 // 648 // Register: DDI_0_OSC_O_LFOSCCTL 649 // 650 //***************************************************************************** 651 // Field: [23:22] XOSCLF_REGULATOR_TRIM 652 // 653 // Internal. Only to be used through TI provided API. 654 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 655 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 656 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 657 658 // Field: [21:18] XOSCLF_CMIRRWR_RATIO 659 // 660 // Internal. Only to be used through TI provided API. 661 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 662 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 663 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 664 665 // Field: [9:8] RCOSCLF_RTUNE_TRIM 666 // 667 // Internal. Only to be used through TI provided API. 668 // ENUMs: 669 // 6P0MEG Internal. Only to be used through TI provided API. 670 // 6P5MEG Internal. Only to be used through TI provided API. 671 // 7P0MEG Internal. Only to be used through TI provided API. 672 // 7P5MEG Internal. Only to be used through TI provided API. 673 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 674 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 675 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 676 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 677 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 678 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 679 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 680 681 // Field: [7:0] RCOSCLF_CTUNE_TRIM 682 // 683 // Internal. Only to be used through TI provided API. 684 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 685 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF 686 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 687 688 //***************************************************************************** 689 // 690 // Register: DDI_0_OSC_O_RCOSCHFCTL 691 // 692 //***************************************************************************** 693 // Field: [15:8] RCOSCHF_CTRIM 694 // 695 // Internal. Only to be used through TI provided API. 696 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 697 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 698 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 699 700 //***************************************************************************** 701 // 702 // Register: DDI_0_OSC_O_STAT0 703 // 704 //***************************************************************************** 705 // Field: [30:29] SCLK_LF_SRC 706 // 707 // Indicates source for the sclk_lf 708 // ENUMs: 709 // XOSCLF Low frequency XOSC 710 // RCOSCLF Low frequency RCOSC 711 // XOSCHFDLF Low frequency clock derived from High Frequency 712 // XOSC 713 // RCOSCHFDLF Low frequency clock derived from High Frequency 714 // RCOSC 715 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 716 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 717 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 718 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 719 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 720 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 721 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 722 723 // Field: [28] SCLK_HF_SRC 724 // 725 // Indicates source for the sclk_hf 726 // ENUMs: 727 // XOSC High frequency XOSC 728 // RCOSC High frequency RCOSC clk 729 #define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 730 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_BITN 28 731 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 732 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 733 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 734 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 735 736 // Field: [22] RCOSC_HF_EN 737 // 738 // RCOSC_HF_EN 739 #define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 740 #define DDI_0_OSC_STAT0_RCOSC_HF_EN_BITN 22 741 #define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 742 #define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 743 744 // Field: [21] RCOSC_LF_EN 745 // 746 // RCOSC_LF_EN 747 #define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 748 #define DDI_0_OSC_STAT0_RCOSC_LF_EN_BITN 21 749 #define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 750 #define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 751 752 // Field: [20] XOSC_LF_EN 753 // 754 // XOSC_LF_EN 755 #define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 756 #define DDI_0_OSC_STAT0_XOSC_LF_EN_BITN 20 757 #define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 758 #define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 759 760 // Field: [19] CLK_DCDC_RDY 761 // 762 // CLK_DCDC_RDY 763 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 764 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_BITN 19 765 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 766 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 767 768 // Field: [18] CLK_DCDC_RDY_ACK 769 // 770 // CLK_DCDC_RDY_ACK 771 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 772 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_BITN 18 773 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 774 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 775 776 // Field: [17] SCLK_HF_LOSS 777 // 778 // Indicates sclk_hf is lost 779 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 780 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS_BITN 17 781 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 782 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 783 784 // Field: [16] SCLK_LF_LOSS 785 // 786 // Indicates sclk_lf is lost 787 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 788 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS_BITN 16 789 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 790 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 791 792 // Field: [15] XOSC_HF_EN 793 // 794 // Indicates that XOSC_HF is enabled. 795 #define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 796 #define DDI_0_OSC_STAT0_XOSC_HF_EN_BITN 15 797 #define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 798 #define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 799 800 // Field: [13] XB_48M_CLK_EN 801 // 802 // Indicates that the 48MHz clock from the DOUBLER is enabled. 803 // 804 // It will be enabled if 24 or 48 MHz chrystal is used (enabled in doulbler 805 // bypass for the 48MHz chrystal). 806 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 807 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN_BITN 13 808 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 809 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 810 811 // Field: [11] XOSC_HF_LP_BUF_EN 812 // 813 // XOSC_HF_LP_BUF_EN 814 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 815 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_BITN 11 816 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 817 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 818 819 // Field: [10] XOSC_HF_HP_BUF_EN 820 // 821 // XOSC_HF_HP_BUF_EN 822 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 823 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_BITN 10 824 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 825 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 826 827 // Field: [8] ADC_THMET 828 // 829 // ADC_THMET 830 #define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 831 #define DDI_0_OSC_STAT0_ADC_THMET_BITN 8 832 #define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 833 #define DDI_0_OSC_STAT0_ADC_THMET_S 8 834 835 // Field: [7] ADC_DATA_READY 836 // 837 // indicates when adc_data is ready. 838 #define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 839 #define DDI_0_OSC_STAT0_ADC_DATA_READY_BITN 7 840 #define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 841 #define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 842 843 // Field: [6:1] ADC_DATA 844 // 845 // adc_data 846 #define DDI_0_OSC_STAT0_ADC_DATA_W 6 847 #define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E 848 #define DDI_0_OSC_STAT0_ADC_DATA_S 1 849 850 // Field: [0] PENDINGSCLKHFSWITCHING 851 // 852 // Indicates when sclk_hf is ready to be swtiched 853 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 854 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_BITN 0 855 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 856 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 857 858 //***************************************************************************** 859 // 860 // Register: DDI_0_OSC_O_STAT1 861 // 862 //***************************************************************************** 863 // Field: [31:28] RAMPSTATE 864 // 865 // AMPCOMP FSM State 866 // ENUMs: 867 // FAST_START_SETTLE FAST_START_SETTLE 868 // FAST_START FAST_START 869 // DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 870 // IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE 871 // IBIAS_INC IBIAS_INCREMENT 872 // LPM_UPDATE LPM_UPDATE 873 // IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE 874 // IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE 875 // IDAC_INCREMENT IDAC_INCREMENT 876 // HPM_UPDATE HPM_UPDATE 877 // HPM_RAMP3 HPM_RAMP3 878 // HPM_RAMP2 HPM_RAMP2 879 // HPM_RAMP1 HPM_RAMP1 880 // INITIALIZATION INITIALIZATION 881 // RESET RESET 882 #define DDI_0_OSC_STAT1_RAMPSTATE_W 4 883 #define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 884 #define DDI_0_OSC_STAT1_RAMPSTATE_S 28 885 #define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 886 #define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 887 #define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 888 #define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 889 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 890 #define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 891 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 892 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 893 #define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 894 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 895 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 896 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 897 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 898 #define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 899 #define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 900 901 // Field: [27:22] HMP_UPDATE_AMP 902 // 903 // OSC amplitude during HPM_UPDATE state. 904 // The vaue is an unsigned interger. It is used for debug only. 905 #define DDI_0_OSC_STAT1_HMP_UPDATE_AMP_W 6 906 #define DDI_0_OSC_STAT1_HMP_UPDATE_AMP_M 0x0FC00000 907 #define DDI_0_OSC_STAT1_HMP_UPDATE_AMP_S 22 908 909 // Field: [21:16] LPM_UPDATE_AMP 910 // 911 // OSC amplitude during LPM_UPDATE state 912 // The vaue is an unsigned interger. It is used for debug only. 913 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 914 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 915 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 916 917 // Field: [15] FORCE_RCOSC_HF 918 // 919 // force_rcosc_hf 920 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 921 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_BITN 15 922 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 923 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 924 925 // Field: [14] SCLK_HF_EN 926 // 927 // SCLK_HF_EN 928 #define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 929 #define DDI_0_OSC_STAT1_SCLK_HF_EN_BITN 14 930 #define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 931 #define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 932 933 // Field: [13] SCLK_MF_EN 934 // 935 // SCLK_MF_EN 936 #define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 937 #define DDI_0_OSC_STAT1_SCLK_MF_EN_BITN 13 938 #define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 939 #define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 940 941 // Field: [12] ACLK_ADC_EN 942 // 943 // ACLK_ADC_EN 944 #define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 945 #define DDI_0_OSC_STAT1_ACLK_ADC_EN_BITN 12 946 #define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 947 #define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 948 949 // Field: [11] ACLK_TDC_EN 950 // 951 // ACLK_TDC_EN 952 #define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 953 #define DDI_0_OSC_STAT1_ACLK_TDC_EN_BITN 11 954 #define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 955 #define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 956 957 // Field: [10] ACLK_REF_EN 958 // 959 // ACLK_REF_EN 960 #define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 961 #define DDI_0_OSC_STAT1_ACLK_REF_EN_BITN 10 962 #define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 963 #define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 964 965 // Field: [9] CLK_CHP_EN 966 // 967 // CLK_CHP_EN 968 #define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 969 #define DDI_0_OSC_STAT1_CLK_CHP_EN_BITN 9 970 #define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 971 #define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 972 973 // Field: [8] CLK_DCDC_EN 974 // 975 // CLK_DCDC_EN 976 #define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 977 #define DDI_0_OSC_STAT1_CLK_DCDC_EN_BITN 8 978 #define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 979 #define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 980 981 // Field: [7] SCLK_HF_GOOD 982 // 983 // SCLK_HF_GOOD 984 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 985 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD_BITN 7 986 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 987 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 988 989 // Field: [6] SCLK_MF_GOOD 990 // 991 // SCLK_MF_GOOD 992 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 993 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD_BITN 6 994 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 995 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 996 997 // Field: [5] SCLK_LF_GOOD 998 // 999 // SCLK_LF_GOOD 1000 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 1001 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD_BITN 5 1002 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 1003 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 1004 1005 // Field: [4] ACLK_ADC_GOOD 1006 // 1007 // ACLK_ADC_GOOD 1008 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 1009 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_BITN 4 1010 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 1011 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 1012 1013 // Field: [3] ACLK_TDC_GOOD 1014 // 1015 // ACLK_TDC_GOOD 1016 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 1017 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_BITN 3 1018 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 1019 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 1020 1021 // Field: [2] ACLK_REF_GOOD 1022 // 1023 // ACLK_REF_GOOD 1024 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 1025 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD_BITN 2 1026 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 1027 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 1028 1029 // Field: [1] CLK_CHP_GOOD 1030 // 1031 // CLK_CHP_GOOD 1032 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 1033 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD_BITN 1 1034 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 1035 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 1036 1037 // Field: [0] CLK_DCDC_GOOD 1038 // 1039 // CLK_DCDC_GOOD 1040 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 1041 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_BITN 0 1042 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 1043 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 1044 1045 //***************************************************************************** 1046 // 1047 // Register: DDI_0_OSC_O_STAT2 1048 // 1049 //***************************************************************************** 1050 // Field: [31:26] ADC_DCBIAS 1051 // 1052 // DC Bias read by RADC during SAR mode 1053 // The vaue is an unsigned interger. It is used for debug only. 1054 #define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 1055 #define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 1056 #define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 1057 1058 // Field: [25] HPM_RAMP1_THMET 1059 // 1060 // Indication of threshhold is met for hpm_ramp1 1061 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 1062 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_BITN 25 1063 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 1064 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 1065 1066 // Field: [24] HPM_RAMP2_THMET 1067 // 1068 // Indication of threshhold is met for hpm_ramp2 1069 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 1070 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_BITN 24 1071 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 1072 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 1073 1074 // Field: [23] HPM_RAMP3_THMET 1075 // 1076 // Indication of threshhold is met for hpm_ramp3 1077 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 1078 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_BITN 23 1079 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 1080 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 1081 1082 // Field: [15:12] RAMPSTATE 1083 // 1084 // xosc_hf amplitude compensation FSM 1085 // 1086 // This is identical to STAT1.RAMPSTATE. See that description for encoding. 1087 #define DDI_0_OSC_STAT2_RAMPSTATE_W 4 1088 #define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 1089 #define DDI_0_OSC_STAT2_RAMPSTATE_S 12 1090 1091 // Field: [3] AMPCOMP_REQ 1092 // 1093 // ampcomp_req 1094 #define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 1095 #define DDI_0_OSC_STAT2_AMPCOMP_REQ_BITN 3 1096 #define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 1097 #define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 1098 1099 // Field: [2] XOSC_HF_AMPGOOD 1100 // 1101 // amplitude of xosc_hf is within the required threshold (set by DDI). Not used 1102 // for anything just for debug/status 1103 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 1104 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_BITN 2 1105 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 1106 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 1107 1108 // Field: [1] XOSC_HF_FREQGOOD 1109 // 1110 // frequency of xosc_hf is good to use for the digital clocks 1111 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 1112 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_BITN 1 1113 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 1114 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 1115 1116 // Field: [0] XOSC_HF_RF_FREQGOOD 1117 // 1118 // frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio 1119 // operations. Used for SW to start synthesizer. 1120 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 1121 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_BITN 0 1122 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 1123 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 1124 1125 1126 #endif // __DDI_0_OSC__ 1127