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Searched refs:DDR_CLK_CTRL (Results 1 – 2 of 2) sorted by relevance

/lk-master/platform/zynq/
A Dplatform.c90 SLCR_REG(DDR_CLK_CTRL) = zynq_clk_cfg.ddr_clk; in zynq_pll_init()
93 SLCR_REG(DDR_CLK_CTRL) = 0; in zynq_pll_init()
/lk-master/platform/zynq/include/platform/
A Dzynq.h174 uint32_t DDR_CLK_CTRL; // DDR Clock Control member

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