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Searched refs:DDR_PLL_CTRL (Results 1 – 3 of 3) sorted by relevance

/lk-master/platform/zynq/
A Dplatform.c82 SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET; in zynq_pll_init()
83 SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET; in zynq_pll_init()
89 SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE; in zynq_pll_init()
94 SLCR_REG(DDR_PLL_CTRL) |= PLL_PWRDOWN; in zynq_pll_init()
A Dclocks.c33 LTRACEF("DDR_PLL_CTRL 0x%x\n", SLCR_REG(DDR_PLL_CTRL)); in get_ddr_pll_freq()
37 uint32_t fdiv = BITS_SHIFT(SLCR_REG(DDR_PLL_CTRL), 18, 12); in get_ddr_pll_freq()
/lk-master/platform/zynq/include/platform/
A Dzynq.h166 uint32_t DDR_PLL_CTRL; // DDR PLL Control member

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