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Searched refs:ENABLE (Results 1 – 25 of 125) sorted by relevance

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/lk-master/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_gpio.c134 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); in GPIO_DeInit()
139 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); in GPIO_DeInit()
144 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); in GPIO_DeInit()
149 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); in GPIO_DeInit()
154 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); in GPIO_DeInit()
159 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); in GPIO_DeInit()
164 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); in GPIO_DeInit()
169 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); in GPIO_DeInit()
175 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); in GPIO_DeInit()
180 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); in GPIO_DeInit()
[all …]
A Dstm32f4xx_cryp_aes.c186 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
223 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
388 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
426 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
597 CRYP_Cmd(ENABLE); in CRYP_AES_CTR()
775 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
899 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
952 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
1076 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
1332 CRYP_Cmd(ENABLE); in CRYP_AES_CCM()
[all …]
A Dstm32f4xx_pwr.c166 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); in PWR_DeInit()
547 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE; in PWR_MainRegulatorUnderDriveCmd()
571 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE; in PWR_LowRegulatorUnderDriveCmd()
597 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; in PWR_MainRegulatorLowVoltageCmd()
621 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; in PWR_LowRegulatorLowVoltageCmd()
A Dstm32f4xx_usart.c194 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); in USART_DeInit()
199 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); in USART_DeInit()
204 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); in USART_DeInit()
209 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); in USART_DeInit()
214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); in USART_DeInit()
219 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); in USART_DeInit()
224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); in USART_DeInit()
231 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); in USART_DeInit()
A Dstm32f4xx_wwdg.c140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
198 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f4xx_spi.c232 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); in SPI_I2S_DeInit()
239 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); in SPI_I2S_DeInit()
246 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); in SPI_I2S_DeInit()
253 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); in SPI_I2S_DeInit()
260 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); in SPI_I2S_DeInit()
269 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); in SPI_I2S_DeInit()
A Dstm32f4xx_can.c174 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
181 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
234 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
244 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
254 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
264 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
274 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
284 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
410 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) in CAN_FilterInit()
/lk-master/platform/stm32f1xx/
A Duart.c66 USART_Cmd(usart, ENABLE); in usart_init1_early()
71 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_init1()
73 USART_Cmd(usart, ENABLE); in usart_init1()
78 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); in uart_init_early()
81 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); in uart_init_early()
84 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); in uart_init_early()
162 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_getc()
A Dgpio.c40 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA << port, ENABLE); in enable_port()
44 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); in stm32_gpio_early_init()
/lk-master/platform/stm32f2xx/
A Duart.c66 USART_Cmd(usart, ENABLE); in usart_init1_early()
71 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_init1()
73 USART_Cmd(usart, ENABLE); in usart_init1()
78 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); in uart_init_early()
81 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); in uart_init_early()
84 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); in uart_init_early()
159 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_getc()
/lk-master/platform/stm32f4xx/
A Duart.c88 USART_Cmd(usart, ENABLE); in usart_init1_early()
93 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_init1()
95 USART_Cmd(usart, ENABLE); in usart_init1()
100 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); in uart_init_early()
104 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); in uart_init_early()
108 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); in uart_init_early()
112 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); in uart_init_early()
187 USART_ITConfig(usart, USART_IT_RXNE, ENABLE); in usart_getc()
/lk-master/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dstm32f2xx_gpio.c133 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); in GPIO_DeInit()
138 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); in GPIO_DeInit()
143 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); in GPIO_DeInit()
148 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); in GPIO_DeInit()
153 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); in GPIO_DeInit()
158 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); in GPIO_DeInit()
163 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); in GPIO_DeInit()
168 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); in GPIO_DeInit()
175 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); in GPIO_DeInit()
A Dstm32f2xx_wwdg.c142 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
200 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f2xx_usart.c191 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); in USART_DeInit()
196 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); in USART_DeInit()
201 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); in USART_DeInit()
206 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); in USART_DeInit()
211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); in USART_DeInit()
218 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); in USART_DeInit()
A Dstm32f2xx_can.c176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
183 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
236 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
246 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
256 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
266 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
276 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
286 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
412 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) in CAN_FilterInit()
/lk-master/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_gpio.c114 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); in GPIO_DeInit()
119 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); in GPIO_DeInit()
124 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); in GPIO_DeInit()
129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); in GPIO_DeInit()
134 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); in GPIO_DeInit()
139 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); in GPIO_DeInit()
146 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); in GPIO_DeInit()
160 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); in GPIO_AFIODeInit()
A Dstm32f10x_wwdg.c103 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
160 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f10x_can.c122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
182 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
192 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
202 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
212 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
222 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
232 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
356 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) in CAN_FilterInit()
A Dstm32f10x_tim.c128 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); in TIM_DeInit()
133 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); in TIM_DeInit()
138 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); in TIM_DeInit()
143 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); in TIM_DeInit()
148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); in TIM_DeInit()
153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); in TIM_DeInit()
158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); in TIM_DeInit()
163 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); in TIM_DeInit()
168 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); in TIM_DeInit()
173 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); in TIM_DeInit()
[all …]
/lk-master/external/platform/nrfx/hal/
A Dnrf_lpcomp.h312 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_configure()
336 uint32_t lpcomp_enable_state = p_reg->ENABLE; in nrf_lpcomp_input_select()
338 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_input_select()
341 p_reg->ENABLE = lpcomp_enable_state; in nrf_lpcomp_input_select()
346 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_enable()
355 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_disable()
A Dnrf_adc.h318 p_reg->ENABLE = (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos); in nrf_adc_enable()
323 p_reg->ENABLE = (ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos); in nrf_adc_disable()
328 return (p_reg->ENABLE == (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos)); in nrf_adc_enable_check()
/lk-master/target/qemu-m4/
A Dm4display.c66 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE); in setup_pins()
81 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE); in setup_pins()
101 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI6, ENABLE); in setup_pins()
121 SPI_Cmd(SPI6, ENABLE); // enable SPI6 in init_display()
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/CMSIS/
A Dstm32f7xx.h140 ENABLE = !DISABLE enumerator
142 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dlpc_types.h68 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; enumerator
69 #define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/lk-master/external/platform/stm32f0xx/CMSIS/inc/
A Dstm32f0xx.h192 ENABLE = !DISABLE enumerator
194 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

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