1 /****************************************************************************** 2 * Filename: hw_event_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_EVENT_H__ 38 #define __HW_EVENT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // EVENT component 44 // 45 //***************************************************************************** 46 // Output Selection for CPU Interrupt 0 47 #define EVENT_O_CPUIRQSEL0 0x00000000 48 49 // Output Selection for CPU Interrupt 1 50 #define EVENT_O_CPUIRQSEL1 0x00000004 51 52 // Output Selection for CPU Interrupt 2 53 #define EVENT_O_CPUIRQSEL2 0x00000008 54 55 // Output Selection for CPU Interrupt 3 56 #define EVENT_O_CPUIRQSEL3 0x0000000C 57 58 // Output Selection for CPU Interrupt 4 59 #define EVENT_O_CPUIRQSEL4 0x00000010 60 61 // Output Selection for CPU Interrupt 5 62 #define EVENT_O_CPUIRQSEL5 0x00000014 63 64 // Output Selection for CPU Interrupt 6 65 #define EVENT_O_CPUIRQSEL6 0x00000018 66 67 // Output Selection for CPU Interrupt 7 68 #define EVENT_O_CPUIRQSEL7 0x0000001C 69 70 // Output Selection for CPU Interrupt 8 71 #define EVENT_O_CPUIRQSEL8 0x00000020 72 73 // Output Selection for CPU Interrupt 9 74 #define EVENT_O_CPUIRQSEL9 0x00000024 75 76 // Output Selection for CPU Interrupt 10 77 #define EVENT_O_CPUIRQSEL10 0x00000028 78 79 // Output Selection for CPU Interrupt 11 80 #define EVENT_O_CPUIRQSEL11 0x0000002C 81 82 // Output Selection for CPU Interrupt 12 83 #define EVENT_O_CPUIRQSEL12 0x00000030 84 85 // Output Selection for CPU Interrupt 13 86 #define EVENT_O_CPUIRQSEL13 0x00000034 87 88 // Output Selection for CPU Interrupt 14 89 #define EVENT_O_CPUIRQSEL14 0x00000038 90 91 // Output Selection for CPU Interrupt 15 92 #define EVENT_O_CPUIRQSEL15 0x0000003C 93 94 // Output Selection for CPU Interrupt 16 95 #define EVENT_O_CPUIRQSEL16 0x00000040 96 97 // Output Selection for CPU Interrupt 17 98 #define EVENT_O_CPUIRQSEL17 0x00000044 99 100 // Output Selection for CPU Interrupt 18 101 #define EVENT_O_CPUIRQSEL18 0x00000048 102 103 // Output Selection for CPU Interrupt 19 104 #define EVENT_O_CPUIRQSEL19 0x0000004C 105 106 // Output Selection for CPU Interrupt 20 107 #define EVENT_O_CPUIRQSEL20 0x00000050 108 109 // Output Selection for CPU Interrupt 21 110 #define EVENT_O_CPUIRQSEL21 0x00000054 111 112 // Output Selection for CPU Interrupt 22 113 #define EVENT_O_CPUIRQSEL22 0x00000058 114 115 // Output Selection for CPU Interrupt 23 116 #define EVENT_O_CPUIRQSEL23 0x0000005C 117 118 // Output Selection for CPU Interrupt 24 119 #define EVENT_O_CPUIRQSEL24 0x00000060 120 121 // Output Selection for CPU Interrupt 25 122 #define EVENT_O_CPUIRQSEL25 0x00000064 123 124 // Output Selection for CPU Interrupt 26 125 #define EVENT_O_CPUIRQSEL26 0x00000068 126 127 // Output Selection for CPU Interrupt 27 128 #define EVENT_O_CPUIRQSEL27 0x0000006C 129 130 // Output Selection for CPU Interrupt 28 131 #define EVENT_O_CPUIRQSEL28 0x00000070 132 133 // Output Selection for CPU Interrupt 29 134 #define EVENT_O_CPUIRQSEL29 0x00000074 135 136 // Output Selection for CPU Interrupt 30 137 #define EVENT_O_CPUIRQSEL30 0x00000078 138 139 // Output Selection for CPU Interrupt 31 140 #define EVENT_O_CPUIRQSEL31 0x0000007C 141 142 // Output Selection for CPU Interrupt 32 143 #define EVENT_O_CPUIRQSEL32 0x00000080 144 145 // Output Selection for CPU Interrupt 33 146 #define EVENT_O_CPUIRQSEL33 0x00000084 147 148 // Output Selection for RFC Event 0 149 #define EVENT_O_RFCSEL0 0x00000100 150 151 // Output Selection for RFC Event 1 152 #define EVENT_O_RFCSEL1 0x00000104 153 154 // Output Selection for RFC Event 2 155 #define EVENT_O_RFCSEL2 0x00000108 156 157 // Output Selection for RFC Event 3 158 #define EVENT_O_RFCSEL3 0x0000010C 159 160 // Output Selection for RFC Event 4 161 #define EVENT_O_RFCSEL4 0x00000110 162 163 // Output Selection for RFC Event 5 164 #define EVENT_O_RFCSEL5 0x00000114 165 166 // Output Selection for RFC Event 6 167 #define EVENT_O_RFCSEL6 0x00000118 168 169 // Output Selection for RFC Event 7 170 #define EVENT_O_RFCSEL7 0x0000011C 171 172 // Output Selection for RFC Event 8 173 #define EVENT_O_RFCSEL8 0x00000120 174 175 // Output Selection for RFC Event 9 176 #define EVENT_O_RFCSEL9 0x00000124 177 178 // Output Selection for GPT0 0 179 #define EVENT_O_GPT0ACAPTSEL 0x00000200 180 181 // Output Selection for GPT0 1 182 #define EVENT_O_GPT0BCAPTSEL 0x00000204 183 184 // Output Selection for GPT1 0 185 #define EVENT_O_GPT1ACAPTSEL 0x00000300 186 187 // Output Selection for GPT1 1 188 #define EVENT_O_GPT1BCAPTSEL 0x00000304 189 190 // Output Selection for GPT2 0 191 #define EVENT_O_GPT2ACAPTSEL 0x00000400 192 193 // Output Selection for GPT2 1 194 #define EVENT_O_GPT2BCAPTSEL 0x00000404 195 196 // Output Selection for DMA Channel 1 SREQ 197 #define EVENT_O_UDMACH1SSEL 0x00000508 198 199 // Output Selection for DMA Channel 1 REQ 200 #define EVENT_O_UDMACH1BSEL 0x0000050C 201 202 // Output Selection for DMA Channel 2 SREQ 203 #define EVENT_O_UDMACH2SSEL 0x00000510 204 205 // Output Selection for DMA Channel 2 REQ 206 #define EVENT_O_UDMACH2BSEL 0x00000514 207 208 // Output Selection for DMA Channel 3 SREQ 209 #define EVENT_O_UDMACH3SSEL 0x00000518 210 211 // Output Selection for DMA Channel 3 REQ 212 #define EVENT_O_UDMACH3BSEL 0x0000051C 213 214 // Output Selection for DMA Channel 4 SREQ 215 #define EVENT_O_UDMACH4SSEL 0x00000520 216 217 // Output Selection for DMA Channel 4 REQ 218 #define EVENT_O_UDMACH4BSEL 0x00000524 219 220 // Output Selection for DMA Channel 5 SREQ 221 #define EVENT_O_UDMACH5SSEL 0x00000528 222 223 // Output Selection for DMA Channel 5 REQ 224 #define EVENT_O_UDMACH5BSEL 0x0000052C 225 226 // Output Selection for DMA Channel 6 SREQ 227 #define EVENT_O_UDMACH6SSEL 0x00000530 228 229 // Output Selection for DMA Channel 6 REQ 230 #define EVENT_O_UDMACH6BSEL 0x00000534 231 232 // Output Selection for DMA Channel 7 SREQ 233 #define EVENT_O_UDMACH7SSEL 0x00000538 234 235 // Output Selection for DMA Channel 7 REQ 236 #define EVENT_O_UDMACH7BSEL 0x0000053C 237 238 // Output Selection for DMA Channel 8 SREQ 239 #define EVENT_O_UDMACH8SSEL 0x00000540 240 241 // Output Selection for DMA Channel 8 REQ 242 #define EVENT_O_UDMACH8BSEL 0x00000544 243 244 // Output Selection for DMA Channel 9 SREQ 245 #define EVENT_O_UDMACH9SSEL 0x00000548 246 247 // Output Selection for DMA Channel 9 REQ 248 #define EVENT_O_UDMACH9BSEL 0x0000054C 249 250 // Output Selection for DMA Channel 10 SREQ 251 #define EVENT_O_UDMACH10SSEL 0x00000550 252 253 // Output Selection for DMA Channel 10 REQ 254 #define EVENT_O_UDMACH10BSEL 0x00000554 255 256 // Output Selection for DMA Channel 11 SREQ 257 #define EVENT_O_UDMACH11SSEL 0x00000558 258 259 // Output Selection for DMA Channel 11 REQ 260 #define EVENT_O_UDMACH11BSEL 0x0000055C 261 262 // Output Selection for DMA Channel 12 SREQ 263 #define EVENT_O_UDMACH12SSEL 0x00000560 264 265 // Output Selection for DMA Channel 12 REQ 266 #define EVENT_O_UDMACH12BSEL 0x00000564 267 268 // Output Selection for DMA Channel 13 REQ 269 #define EVENT_O_UDMACH13BSEL 0x0000056C 270 271 // Output Selection for DMA Channel 14 REQ 272 #define EVENT_O_UDMACH14BSEL 0x00000574 273 274 // Output Selection for DMA Channel 15 REQ 275 #define EVENT_O_UDMACH15BSEL 0x0000057C 276 277 // Output Selection for DMA Channel 16 SREQ 278 #define EVENT_O_UDMACH16SSEL 0x00000580 279 280 // Output Selection for DMA Channel 16 REQ 281 #define EVENT_O_UDMACH16BSEL 0x00000584 282 283 // Output Selection for DMA Channel 17 SREQ 284 #define EVENT_O_UDMACH17SSEL 0x00000588 285 286 // Output Selection for DMA Channel 17 REQ 287 #define EVENT_O_UDMACH17BSEL 0x0000058C 288 289 // Output Selection for DMA Channel 21 SREQ 290 #define EVENT_O_UDMACH21SSEL 0x000005A8 291 292 // Output Selection for DMA Channel 21 REQ 293 #define EVENT_O_UDMACH21BSEL 0x000005AC 294 295 // Output Selection for DMA Channel 22 SREQ 296 #define EVENT_O_UDMACH22SSEL 0x000005B0 297 298 // Output Selection for DMA Channel 22 REQ 299 #define EVENT_O_UDMACH22BSEL 0x000005B4 300 301 // Output Selection for DMA Channel 23 SREQ 302 #define EVENT_O_UDMACH23SSEL 0x000005B8 303 304 // Output Selection for DMA Channel 23 REQ 305 #define EVENT_O_UDMACH23BSEL 0x000005BC 306 307 // Output Selection for DMA Channel 24 SREQ 308 #define EVENT_O_UDMACH24SSEL 0x000005C0 309 310 // Output Selection for DMA Channel 24 REQ 311 #define EVENT_O_UDMACH24BSEL 0x000005C4 312 313 // Output Selection for GPT3 0 314 #define EVENT_O_GPT3ACAPTSEL 0x00000600 315 316 // Output Selection for GPT3 1 317 #define EVENT_O_GPT3BCAPTSEL 0x00000604 318 319 // Output Selection for AUX Subscriber 0 320 #define EVENT_O_AUXSEL0 0x00000700 321 322 // Output Selection for NMI Subscriber 0 323 #define EVENT_O_CM3NMISEL0 0x00000800 324 325 // Output Selection for I2S Subscriber 0 326 #define EVENT_O_I2SSTMPSEL0 0x00000900 327 328 // Output Selection for FRZ Subscriber 0 329 #define EVENT_O_FRZSEL0 0x00000A00 330 331 // Set or Clear Software Events 332 #define EVENT_O_SWEV 0x00000F00 333 334 //***************************************************************************** 335 // 336 // Register: EVENT_O_CPUIRQSEL0 337 // 338 //***************************************************************************** 339 // Field: [6:0] EV 340 // 341 // Read only selection value 342 // ENUMs: 343 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 344 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 345 // settings 346 #define EVENT_CPUIRQSEL0_EV_W 7 347 #define EVENT_CPUIRQSEL0_EV_M 0x0000007F 348 #define EVENT_CPUIRQSEL0_EV_S 0 349 #define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 350 351 //***************************************************************************** 352 // 353 // Register: EVENT_O_CPUIRQSEL1 354 // 355 //***************************************************************************** 356 // Field: [6:0] EV 357 // 358 // Read only selection value 359 // ENUMs: 360 // I2C_IRQ Interrupt event from I2C 361 #define EVENT_CPUIRQSEL1_EV_W 7 362 #define EVENT_CPUIRQSEL1_EV_M 0x0000007F 363 #define EVENT_CPUIRQSEL1_EV_S 0 364 #define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 365 366 //***************************************************************************** 367 // 368 // Register: EVENT_O_CPUIRQSEL2 369 // 370 //***************************************************************************** 371 // Field: [6:0] EV 372 // 373 // Read only selection value 374 // ENUMs: 375 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 376 // Corresponding flags are here 377 // RFC_DBELL:RFCPEIFG. Only interrupts selected 378 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 379 // RFC_CPE_1 event 380 #define EVENT_CPUIRQSEL2_EV_W 7 381 #define EVENT_CPUIRQSEL2_EV_M 0x0000007F 382 #define EVENT_CPUIRQSEL2_EV_S 0 383 #define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E 384 385 //***************************************************************************** 386 // 387 // Register: EVENT_O_CPUIRQSEL3 388 // 389 //***************************************************************************** 390 //***************************************************************************** 391 // 392 // Register: EVENT_O_CPUIRQSEL4 393 // 394 //***************************************************************************** 395 // Field: [6:0] EV 396 // 397 // Read only selection value 398 // ENUMs: 399 // AON_RTC_COMB Event from AON_RTC, controlled by the 400 // AON_RTC:CTL.COMB_EV_MASK setting 401 #define EVENT_CPUIRQSEL4_EV_W 7 402 #define EVENT_CPUIRQSEL4_EV_M 0x0000007F 403 #define EVENT_CPUIRQSEL4_EV_S 0 404 #define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 405 406 //***************************************************************************** 407 // 408 // Register: EVENT_O_CPUIRQSEL5 409 // 410 //***************************************************************************** 411 // Field: [6:0] EV 412 // 413 // Read only selection value 414 // ENUMs: 415 // UART0_COMB UART0 combined interrupt, interrupt flags are 416 // found here UART0:MIS 417 #define EVENT_CPUIRQSEL5_EV_W 7 418 #define EVENT_CPUIRQSEL5_EV_M 0x0000007F 419 #define EVENT_CPUIRQSEL5_EV_S 0 420 #define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 421 422 //***************************************************************************** 423 // 424 // Register: EVENT_O_CPUIRQSEL6 425 // 426 //***************************************************************************** 427 // Field: [6:0] EV 428 // 429 // Read only selection value 430 // ENUMs: 431 // AUX_SWEV0 AUX software event 0, triggered by 432 // AUX_EVCTL:SWEVSET.SWEV0, also available as 433 // AUX_EVENT0 AON wake up event. 434 // MCU domain wakeup control 435 // AON_EVENT:MCUWUSEL 436 // AUX domain wakeup control 437 // AON_EVENT:AUXWUSEL 438 #define EVENT_CPUIRQSEL6_EV_W 7 439 #define EVENT_CPUIRQSEL6_EV_M 0x0000007F 440 #define EVENT_CPUIRQSEL6_EV_S 0 441 #define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C 442 443 //***************************************************************************** 444 // 445 // Register: EVENT_O_CPUIRQSEL7 446 // 447 //***************************************************************************** 448 // Field: [6:0] EV 449 // 450 // Read only selection value 451 // ENUMs: 452 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 453 // here SSI0:MIS 454 #define EVENT_CPUIRQSEL7_EV_W 7 455 #define EVENT_CPUIRQSEL7_EV_M 0x0000007F 456 #define EVENT_CPUIRQSEL7_EV_S 0 457 #define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 458 459 //***************************************************************************** 460 // 461 // Register: EVENT_O_CPUIRQSEL8 462 // 463 //***************************************************************************** 464 // Field: [6:0] EV 465 // 466 // Read only selection value 467 // ENUMs: 468 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 469 // here SSI1:MIS 470 #define EVENT_CPUIRQSEL8_EV_W 7 471 #define EVENT_CPUIRQSEL8_EV_M 0x0000007F 472 #define EVENT_CPUIRQSEL8_EV_S 0 473 #define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 474 475 //***************************************************************************** 476 // 477 // Register: EVENT_O_CPUIRQSEL9 478 // 479 //***************************************************************************** 480 // Field: [6:0] EV 481 // 482 // Read only selection value 483 // ENUMs: 484 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 485 // Corresponding flags are here 486 // RFC_DBELL:RFCPEIFG. Only interrupts selected 487 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 488 // RFC_CPE_0 event 489 #define EVENT_CPUIRQSEL9_EV_W 7 490 #define EVENT_CPUIRQSEL9_EV_M 0x0000007F 491 #define EVENT_CPUIRQSEL9_EV_S 0 492 #define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B 493 494 //***************************************************************************** 495 // 496 // Register: EVENT_O_CPUIRQSEL10 497 // 498 //***************************************************************************** 499 // Field: [6:0] EV 500 // 501 // Read only selection value 502 // ENUMs: 503 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 504 // flag is here RFC_DBELL:RFHWIFG 505 #define EVENT_CPUIRQSEL10_EV_W 7 506 #define EVENT_CPUIRQSEL10_EV_M 0x0000007F 507 #define EVENT_CPUIRQSEL10_EV_S 0 508 #define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A 509 510 //***************************************************************************** 511 // 512 // Register: EVENT_O_CPUIRQSEL11 513 // 514 //***************************************************************************** 515 // Field: [6:0] EV 516 // 517 // Read only selection value 518 // ENUMs: 519 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 520 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 521 #define EVENT_CPUIRQSEL11_EV_W 7 522 #define EVENT_CPUIRQSEL11_EV_M 0x0000007F 523 #define EVENT_CPUIRQSEL11_EV_S 0 524 #define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 525 526 //***************************************************************************** 527 // 528 // Register: EVENT_O_CPUIRQSEL12 529 // 530 //***************************************************************************** 531 // Field: [6:0] EV 532 // 533 // Read only selection value 534 // ENUMs: 535 // I2S_IRQ Interrupt event from I2S 536 #define EVENT_CPUIRQSEL12_EV_W 7 537 #define EVENT_CPUIRQSEL12_EV_M 0x0000007F 538 #define EVENT_CPUIRQSEL12_EV_S 0 539 #define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 540 541 //***************************************************************************** 542 // 543 // Register: EVENT_O_CPUIRQSEL13 544 // 545 //***************************************************************************** 546 // Field: [6:0] EV 547 // 548 // Read only selection value 549 // ENUMs: 550 // AUX_SWEV1 AUX software event 1, triggered by 551 // AUX_EVCTL:SWEVSET.SWEV1, also available as 552 // AUX_EVENT2 AON wake up event. 553 // MCU domain wakeup control 554 // AON_EVENT:MCUWUSEL 555 // AUX domain wakeup control 556 // AON_EVENT:AUXWUSEL 557 #define EVENT_CPUIRQSEL13_EV_W 7 558 #define EVENT_CPUIRQSEL13_EV_M 0x0000007F 559 #define EVENT_CPUIRQSEL13_EV_S 0 560 #define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D 561 562 //***************************************************************************** 563 // 564 // Register: EVENT_O_CPUIRQSEL14 565 // 566 //***************************************************************************** 567 // Field: [6:0] EV 568 // 569 // Read only selection value 570 // ENUMs: 571 // WDT_IRQ Watchdog interrupt event, controlled by 572 // WDT:CTL.INTEN 573 #define EVENT_CPUIRQSEL14_EV_W 7 574 #define EVENT_CPUIRQSEL14_EV_M 0x0000007F 575 #define EVENT_CPUIRQSEL14_EV_S 0 576 #define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 577 578 //***************************************************************************** 579 // 580 // Register: EVENT_O_CPUIRQSEL15 581 // 582 //***************************************************************************** 583 // Field: [6:0] EV 584 // 585 // Read only selection value 586 // ENUMs: 587 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 588 #define EVENT_CPUIRQSEL15_EV_W 7 589 #define EVENT_CPUIRQSEL15_EV_M 0x0000007F 590 #define EVENT_CPUIRQSEL15_EV_S 0 591 #define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 592 593 //***************************************************************************** 594 // 595 // Register: EVENT_O_CPUIRQSEL16 596 // 597 //***************************************************************************** 598 // Field: [6:0] EV 599 // 600 // Read only selection value 601 // ENUMs: 602 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 603 #define EVENT_CPUIRQSEL16_EV_W 7 604 #define EVENT_CPUIRQSEL16_EV_M 0x0000007F 605 #define EVENT_CPUIRQSEL16_EV_S 0 606 #define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 607 608 //***************************************************************************** 609 // 610 // Register: EVENT_O_CPUIRQSEL17 611 // 612 //***************************************************************************** 613 // Field: [6:0] EV 614 // 615 // Read only selection value 616 // ENUMs: 617 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 618 #define EVENT_CPUIRQSEL17_EV_W 7 619 #define EVENT_CPUIRQSEL17_EV_M 0x0000007F 620 #define EVENT_CPUIRQSEL17_EV_S 0 621 #define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 622 623 //***************************************************************************** 624 // 625 // Register: EVENT_O_CPUIRQSEL18 626 // 627 //***************************************************************************** 628 // Field: [6:0] EV 629 // 630 // Read only selection value 631 // ENUMs: 632 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 633 #define EVENT_CPUIRQSEL18_EV_W 7 634 #define EVENT_CPUIRQSEL18_EV_M 0x0000007F 635 #define EVENT_CPUIRQSEL18_EV_S 0 636 #define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 637 638 //***************************************************************************** 639 // 640 // Register: EVENT_O_CPUIRQSEL19 641 // 642 //***************************************************************************** 643 // Field: [6:0] EV 644 // 645 // Read only selection value 646 // ENUMs: 647 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 648 #define EVENT_CPUIRQSEL19_EV_W 7 649 #define EVENT_CPUIRQSEL19_EV_M 0x0000007F 650 #define EVENT_CPUIRQSEL19_EV_S 0 651 #define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C 652 653 //***************************************************************************** 654 // 655 // Register: EVENT_O_CPUIRQSEL20 656 // 657 //***************************************************************************** 658 // Field: [6:0] EV 659 // 660 // Read only selection value 661 // ENUMs: 662 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 663 #define EVENT_CPUIRQSEL20_EV_W 7 664 #define EVENT_CPUIRQSEL20_EV_M 0x0000007F 665 #define EVENT_CPUIRQSEL20_EV_S 0 666 #define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D 667 668 //***************************************************************************** 669 // 670 // Register: EVENT_O_CPUIRQSEL21 671 // 672 //***************************************************************************** 673 // Field: [6:0] EV 674 // 675 // Read only selection value 676 // ENUMs: 677 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 678 #define EVENT_CPUIRQSEL21_EV_W 7 679 #define EVENT_CPUIRQSEL21_EV_M 0x0000007F 680 #define EVENT_CPUIRQSEL21_EV_S 0 681 #define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E 682 683 //***************************************************************************** 684 // 685 // Register: EVENT_O_CPUIRQSEL22 686 // 687 //***************************************************************************** 688 // Field: [6:0] EV 689 // 690 // Read only selection value 691 // ENUMs: 692 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 693 #define EVENT_CPUIRQSEL22_EV_W 7 694 #define EVENT_CPUIRQSEL22_EV_M 0x0000007F 695 #define EVENT_CPUIRQSEL22_EV_S 0 696 #define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F 697 698 //***************************************************************************** 699 // 700 // Register: EVENT_O_CPUIRQSEL23 701 // 702 //***************************************************************************** 703 // Field: [6:0] EV 704 // 705 // Read only selection value 706 // ENUMs: 707 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 708 // corresponding flag is found here 709 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 710 // CRYPTO:IRQSTAT.RESULT_AVAIL 711 #define EVENT_CPUIRQSEL23_EV_W 7 712 #define EVENT_CPUIRQSEL23_EV_M 0x0000007F 713 #define EVENT_CPUIRQSEL23_EV_S 0 714 #define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 715 716 //***************************************************************************** 717 // 718 // Register: EVENT_O_CPUIRQSEL24 719 // 720 //***************************************************************************** 721 // Field: [6:0] EV 722 // 723 // Read only selection value 724 // ENUMs: 725 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 726 // UDMA0:REQDONE 727 #define EVENT_CPUIRQSEL24_EV_W 7 728 #define EVENT_CPUIRQSEL24_EV_M 0x0000007F 729 #define EVENT_CPUIRQSEL24_EV_S 0 730 #define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 731 732 //***************************************************************************** 733 // 734 // Register: EVENT_O_CPUIRQSEL25 735 // 736 //***************************************************************************** 737 // Field: [6:0] EV 738 // 739 // Read only selection value 740 // ENUMs: 741 // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS 742 #define EVENT_CPUIRQSEL25_EV_W 7 743 #define EVENT_CPUIRQSEL25_EV_M 0x0000007F 744 #define EVENT_CPUIRQSEL25_EV_S 0 745 #define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 746 747 //***************************************************************************** 748 // 749 // Register: EVENT_O_CPUIRQSEL26 750 // 751 //***************************************************************************** 752 // Field: [6:0] EV 753 // 754 // Read only selection value 755 // ENUMs: 756 // FLASH FLASH controller error event, the status flags 757 // are FLASH:FEDACSTAT.FSM_DONE and 758 // FLASH:FEDACSTAT.RVF_INT 759 #define EVENT_CPUIRQSEL26_EV_W 7 760 #define EVENT_CPUIRQSEL26_EV_M 0x0000007F 761 #define EVENT_CPUIRQSEL26_EV_S 0 762 #define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 763 764 //***************************************************************************** 765 // 766 // Register: EVENT_O_CPUIRQSEL27 767 // 768 //***************************************************************************** 769 // Field: [6:0] EV 770 // 771 // Read only selection value 772 // ENUMs: 773 // SWEV0 Software event 0, triggered by SWEV.SWEV0 774 #define EVENT_CPUIRQSEL27_EV_W 7 775 #define EVENT_CPUIRQSEL27_EV_M 0x0000007F 776 #define EVENT_CPUIRQSEL27_EV_S 0 777 #define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 778 779 //***************************************************************************** 780 // 781 // Register: EVENT_O_CPUIRQSEL28 782 // 783 //***************************************************************************** 784 // Field: [6:0] EV 785 // 786 // Read only selection value 787 // ENUMs: 788 // AUX_COMB AUX combined event, the corresponding flag 789 // register is here AUX_EVCTL:EVTOMCUFLAGS 790 #define EVENT_CPUIRQSEL28_EV_W 7 791 #define EVENT_CPUIRQSEL28_EV_M 0x0000007F 792 #define EVENT_CPUIRQSEL28_EV_S 0 793 #define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B 794 795 //***************************************************************************** 796 // 797 // Register: EVENT_O_CPUIRQSEL29 798 // 799 //***************************************************************************** 800 // Field: [6:0] EV 801 // 802 // Read only selection value 803 // ENUMs: 804 // AON_PROG0 AON programmable event 0. Event selected by 805 // AON_EVENT MCU event selector, 806 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 807 #define EVENT_CPUIRQSEL29_EV_W 7 808 #define EVENT_CPUIRQSEL29_EV_M 0x0000007F 809 #define EVENT_CPUIRQSEL29_EV_S 0 810 #define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 811 812 //***************************************************************************** 813 // 814 // Register: EVENT_O_CPUIRQSEL30 815 // 816 //***************************************************************************** 817 // Field: [6:0] EV 818 // 819 // Read/write selection value 820 // ENUMs: 821 // ALWAYS_ACTIVE Always asserted 822 // AON_RTC_UPD RTC periodic event controlled by 823 // AON_RTC:CTL.RTC_UPD_EN 824 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 825 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 826 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 827 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 828 // AUX_ADC_DONE AUX ADC done, corresponds to 829 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 830 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 831 // AUX_SMPH:AUTOTAKE 832 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 833 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 834 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 835 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 836 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 837 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 838 // AUX_TDC status AUX_TDC:STAT.DONE 839 // AUX_COMPB AUX Compare B event, corresponds to 840 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 841 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 842 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 843 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 844 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 845 // CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg 846 // flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled 847 // by CRYPTO:IRQEN.DMA_IN_DONE 848 // DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, 849 // see UDMA0:SOFTREQ 850 // DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see 851 // UDMA0:SOFTREQ 852 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 853 // I2S_IRQ Interrupt event from I2S 854 // AON_PROG2 AON programmable event 2. Event selected by 855 // AON_EVENT MCU event selector, 856 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 857 // AON_PROG1 AON programmable event 1. Event selected by 858 // AON_EVENT MCU event selector, 859 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 860 // NONE Always inactive 861 #define EVENT_CPUIRQSEL30_EV_W 7 862 #define EVENT_CPUIRQSEL30_EV_M 0x0000007F 863 #define EVENT_CPUIRQSEL30_EV_S 0 864 #define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 865 #define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 866 #define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 867 #define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 868 #define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 869 #define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 870 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E 871 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D 872 #define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C 873 #define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B 874 #define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 875 #define EVENT_CPUIRQSEL30_EV_RFC_IN_EV5 0x00000060 876 #define EVENT_CPUIRQSEL30_EV_RFC_IN_EV4 0x0000005F 877 #define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E 878 #define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 879 #define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 880 #define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A 881 #define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 882 #define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 883 #define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 884 #define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 885 886 //***************************************************************************** 887 // 888 // Register: EVENT_O_CPUIRQSEL31 889 // 890 //***************************************************************************** 891 // Field: [6:0] EV 892 // 893 // Read only selection value 894 // ENUMs: 895 // AUX_COMPA AUX Compare A event, corresponds to 896 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 897 #define EVENT_CPUIRQSEL31_EV_W 7 898 #define EVENT_CPUIRQSEL31_EV_M 0x0000007F 899 #define EVENT_CPUIRQSEL31_EV_S 0 900 #define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A 901 902 //***************************************************************************** 903 // 904 // Register: EVENT_O_CPUIRQSEL32 905 // 906 //***************************************************************************** 907 // Field: [6:0] EV 908 // 909 // Read only selection value 910 // ENUMs: 911 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 912 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 913 // are found here AUX_EVCTL:EVTOMCUFLAGS 914 #define EVENT_CPUIRQSEL32_EV_W 7 915 #define EVENT_CPUIRQSEL32_EV_M 0x0000007F 916 #define EVENT_CPUIRQSEL32_EV_S 0 917 #define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 918 919 //***************************************************************************** 920 // 921 // Register: EVENT_O_CPUIRQSEL33 922 // 923 //***************************************************************************** 924 // Field: [6:0] EV 925 // 926 // Read only selection value 927 // ENUMs: 928 // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN 929 #define EVENT_CPUIRQSEL33_EV_W 7 930 #define EVENT_CPUIRQSEL33_EV_M 0x0000007F 931 #define EVENT_CPUIRQSEL33_EV_S 0 932 #define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 933 934 //***************************************************************************** 935 // 936 // Register: EVENT_O_RFCSEL0 937 // 938 //***************************************************************************** 939 // Field: [6:0] EV 940 // 941 // Read only selection value 942 // ENUMs: 943 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 944 #define EVENT_RFCSEL0_EV_W 7 945 #define EVENT_RFCSEL0_EV_M 0x0000007F 946 #define EVENT_RFCSEL0_EV_S 0 947 #define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D 948 949 //***************************************************************************** 950 // 951 // Register: EVENT_O_RFCSEL1 952 // 953 //***************************************************************************** 954 // Field: [6:0] EV 955 // 956 // Read only selection value 957 // ENUMs: 958 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 959 #define EVENT_RFCSEL1_EV_W 7 960 #define EVENT_RFCSEL1_EV_M 0x0000007F 961 #define EVENT_RFCSEL1_EV_S 0 962 #define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E 963 964 //***************************************************************************** 965 // 966 // Register: EVENT_O_RFCSEL2 967 // 968 //***************************************************************************** 969 // Field: [6:0] EV 970 // 971 // Read only selection value 972 // ENUMs: 973 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 974 #define EVENT_RFCSEL2_EV_W 7 975 #define EVENT_RFCSEL2_EV_M 0x0000007F 976 #define EVENT_RFCSEL2_EV_S 0 977 #define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F 978 979 //***************************************************************************** 980 // 981 // Register: EVENT_O_RFCSEL3 982 // 983 //***************************************************************************** 984 // Field: [6:0] EV 985 // 986 // Read only selection value 987 // ENUMs: 988 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 989 #define EVENT_RFCSEL3_EV_W 7 990 #define EVENT_RFCSEL3_EV_M 0x0000007F 991 #define EVENT_RFCSEL3_EV_S 0 992 #define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 993 994 //***************************************************************************** 995 // 996 // Register: EVENT_O_RFCSEL4 997 // 998 //***************************************************************************** 999 // Field: [6:0] EV 1000 // 1001 // Read only selection value 1002 // ENUMs: 1003 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1004 #define EVENT_RFCSEL4_EV_W 7 1005 #define EVENT_RFCSEL4_EV_M 0x0000007F 1006 #define EVENT_RFCSEL4_EV_S 0 1007 #define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 1008 1009 //***************************************************************************** 1010 // 1011 // Register: EVENT_O_RFCSEL5 1012 // 1013 //***************************************************************************** 1014 // Field: [6:0] EV 1015 // 1016 // Read only selection value 1017 // ENUMs: 1018 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1019 #define EVENT_RFCSEL5_EV_W 7 1020 #define EVENT_RFCSEL5_EV_M 0x0000007F 1021 #define EVENT_RFCSEL5_EV_S 0 1022 #define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 1023 1024 //***************************************************************************** 1025 // 1026 // Register: EVENT_O_RFCSEL6 1027 // 1028 //***************************************************************************** 1029 // Field: [6:0] EV 1030 // 1031 // Read only selection value 1032 // ENUMs: 1033 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1034 #define EVENT_RFCSEL6_EV_W 7 1035 #define EVENT_RFCSEL6_EV_M 0x0000007F 1036 #define EVENT_RFCSEL6_EV_S 0 1037 #define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 1038 1039 //***************************************************************************** 1040 // 1041 // Register: EVENT_O_RFCSEL7 1042 // 1043 //***************************************************************************** 1044 // Field: [6:0] EV 1045 // 1046 // Read only selection value 1047 // ENUMs: 1048 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1049 #define EVENT_RFCSEL7_EV_W 7 1050 #define EVENT_RFCSEL7_EV_M 0x0000007F 1051 #define EVENT_RFCSEL7_EV_S 0 1052 #define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 1053 1054 //***************************************************************************** 1055 // 1056 // Register: EVENT_O_RFCSEL8 1057 // 1058 //***************************************************************************** 1059 // Field: [6:0] EV 1060 // 1061 // Read only selection value 1062 // ENUMs: 1063 // AON_RTC_UPD RTC periodic event controlled by 1064 // AON_RTC:CTL.RTC_UPD_EN 1065 #define EVENT_RFCSEL8_EV_W 7 1066 #define EVENT_RFCSEL8_EV_M 0x0000007F 1067 #define EVENT_RFCSEL8_EV_S 0 1068 #define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 1069 1070 //***************************************************************************** 1071 // 1072 // Register: EVENT_O_RFCSEL9 1073 // 1074 //***************************************************************************** 1075 // Field: [6:0] EV 1076 // 1077 // Read/write selection value 1078 // ENUMs: 1079 // ALWAYS_ACTIVE Always asserted 1080 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1081 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1082 // are found here AUX_EVCTL:EVTOMCUFLAGS 1083 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1084 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1085 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1086 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1087 // AUX_ADC_DONE AUX ADC done, corresponds to 1088 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1089 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1090 // AUX_SMPH:AUTOTAKE 1091 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1092 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1093 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1094 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1095 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1096 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1097 // AUX_TDC status AUX_TDC:STAT.DONE 1098 // AUX_COMPB AUX Compare B event, corresponds to 1099 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1100 // AUX_COMPA AUX Compare A event, corresponds to 1101 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1102 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1103 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1104 // SWEV1 Software event 1, triggered by SWEV.SWEV1 1105 // SWEV0 Software event 0, triggered by SWEV.SWEV0 1106 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 1107 // corresponding flag is found here 1108 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 1109 // CRYPTO:IRQSTAT.RESULT_AVAIL 1110 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 1111 // UDMA0:REQDONE 1112 // UART0_COMB UART0 combined interrupt, interrupt flags are 1113 // found here UART0:MIS 1114 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1115 // here SSI1:MIS 1116 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1117 // here SSI0:MIS 1118 // WDT_IRQ Watchdog interrupt event, controlled by 1119 // WDT:CTL.INTEN 1120 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 1121 // I2S_IRQ Interrupt event from I2S 1122 // AON_PROG1 AON programmable event 1. Event selected by 1123 // AON_EVENT MCU event selector, 1124 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 1125 // AON_PROG0 AON programmable event 0. Event selected by 1126 // AON_EVENT MCU event selector, 1127 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 1128 // NONE Always inactive 1129 #define EVENT_RFCSEL9_EV_W 7 1130 #define EVENT_RFCSEL9_EV_M 0x0000007F 1131 #define EVENT_RFCSEL9_EV_S 0 1132 #define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 1133 #define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 1134 #define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 1135 #define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1136 #define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 1137 #define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1138 #define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E 1139 #define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D 1140 #define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C 1141 #define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B 1142 #define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A 1143 #define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 1144 #define EVENT_RFCSEL9_EV_SWEV1 0x00000065 1145 #define EVENT_RFCSEL9_EV_SWEV0 0x00000064 1146 #define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 1147 #define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 1148 #define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 1149 #define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 1150 #define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 1151 #define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 1152 #define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A 1153 #define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 1154 #define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 1155 #define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 1156 #define EVENT_RFCSEL9_EV_NONE 0x00000000 1157 1158 //***************************************************************************** 1159 // 1160 // Register: EVENT_O_GPT0ACAPTSEL 1161 // 1162 //***************************************************************************** 1163 // Field: [6:0] EV 1164 // 1165 // Read/write selection value 1166 // ENUMs: 1167 // ALWAYS_ACTIVE Always asserted 1168 // AON_RTC_UPD RTC periodic event controlled by 1169 // AON_RTC:CTL.RTC_UPD_EN 1170 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1171 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1172 // are found here AUX_EVCTL:EVTOMCUFLAGS 1173 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1174 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1175 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1176 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1177 // AUX_ADC_DONE AUX ADC done, corresponds to 1178 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1179 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1180 // AUX_SMPH:AUTOTAKE 1181 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1182 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1183 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1184 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1185 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1186 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1187 // AUX_TDC status AUX_TDC:STAT.DONE 1188 // AUX_COMPB AUX Compare B event, corresponds to 1189 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1190 // AUX_COMPA AUX Compare A event, corresponds to 1191 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1192 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1193 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1194 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 1195 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 1196 // PORT_EVENT1 Port capture event from IOC, configured by 1197 // IOC:IOCFGn.PORT_ID. Events on ports configured 1198 // with ENUM PORT_EVENT1 wil be routed here. 1199 // PORT_EVENT0 Port capture event from IOC, configured by 1200 // IOC:IOCFGn.PORT_ID. Events on ports configured 1201 // with ENUM PORT_EVENT0 wil be routed here. 1202 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1203 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1204 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1205 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1206 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1207 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1208 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1209 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1210 // UART0_COMB UART0 combined interrupt, interrupt flags are 1211 // found here UART0:MIS 1212 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1213 // here SSI1:MIS 1214 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1215 // here SSI0:MIS 1216 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1217 // Corresponding flags are here 1218 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1219 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1220 // RFC_CPE_1 event 1221 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1222 // Corresponding flags are here 1223 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1224 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1225 // RFC_CPE_0 event 1226 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1227 // flag is here RFC_DBELL:RFHWIFG 1228 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1229 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1230 // FLASH FLASH controller error event, the status flags 1231 // are FLASH:FEDACSTAT.FSM_DONE and 1232 // FLASH:FEDACSTAT.RVF_INT 1233 // AUX_COMB AUX combined event, the corresponding flag 1234 // register is here AUX_EVCTL:EVTOMCUFLAGS 1235 // I2C_IRQ Interrupt event from I2C 1236 // AON_RTC_COMB Event from AON_RTC, controlled by the 1237 // AON_RTC:CTL.COMB_EV_MASK setting 1238 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1239 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1240 // settings 1241 // NONE Always inactive 1242 #define EVENT_GPT0ACAPTSEL_EV_W 7 1243 #define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F 1244 #define EVENT_GPT0ACAPTSEL_EV_S 0 1245 #define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1246 #define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1247 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1248 #define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1249 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1250 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1251 #define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1252 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1253 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1254 #define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1255 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B 1256 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A 1257 #define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1258 #define EVENT_GPT0ACAPTSEL_EV_RFC_IN_EV5 0x00000060 1259 #define EVENT_GPT0ACAPTSEL_EV_RFC_IN_EV4 0x0000005F 1260 #define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 1261 #define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 1262 #define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 1263 #define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 1264 #define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 1265 #define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 1266 #define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 1267 #define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1268 #define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1269 #define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1270 #define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 1271 #define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 1272 #define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 1273 #define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1274 #define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1275 #define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1276 #define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1277 #define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 1278 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B 1279 #define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 1280 #define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 1281 #define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1282 #define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 1283 1284 //***************************************************************************** 1285 // 1286 // Register: EVENT_O_GPT0BCAPTSEL 1287 // 1288 //***************************************************************************** 1289 // Field: [6:0] EV 1290 // 1291 // Read/write selection value 1292 // ENUMs: 1293 // ALWAYS_ACTIVE Always asserted 1294 // AON_RTC_UPD RTC periodic event controlled by 1295 // AON_RTC:CTL.RTC_UPD_EN 1296 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1297 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1298 // are found here AUX_EVCTL:EVTOMCUFLAGS 1299 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1300 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1301 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1302 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1303 // AUX_ADC_DONE AUX ADC done, corresponds to 1304 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1305 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1306 // AUX_SMPH:AUTOTAKE 1307 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1308 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1309 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1310 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1311 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1312 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1313 // AUX_TDC status AUX_TDC:STAT.DONE 1314 // AUX_COMPB AUX Compare B event, corresponds to 1315 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1316 // AUX_COMPA AUX Compare A event, corresponds to 1317 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1318 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1319 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1320 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 1321 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 1322 // PORT_EVENT1 Port capture event from IOC, configured by 1323 // IOC:IOCFGn.PORT_ID. Events on ports configured 1324 // with ENUM PORT_EVENT1 wil be routed here. 1325 // PORT_EVENT0 Port capture event from IOC, configured by 1326 // IOC:IOCFGn.PORT_ID. Events on ports configured 1327 // with ENUM PORT_EVENT0 wil be routed here. 1328 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1329 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1330 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1331 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1332 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1333 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1334 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1335 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1336 // UART0_COMB UART0 combined interrupt, interrupt flags are 1337 // found here UART0:MIS 1338 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1339 // here SSI1:MIS 1340 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1341 // here SSI0:MIS 1342 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1343 // Corresponding flags are here 1344 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1345 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1346 // RFC_CPE_1 event 1347 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1348 // Corresponding flags are here 1349 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1350 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1351 // RFC_CPE_0 event 1352 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1353 // flag is here RFC_DBELL:RFHWIFG 1354 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1355 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1356 // FLASH FLASH controller error event, the status flags 1357 // are FLASH:FEDACSTAT.FSM_DONE and 1358 // FLASH:FEDACSTAT.RVF_INT 1359 // AUX_COMB AUX combined event, the corresponding flag 1360 // register is here AUX_EVCTL:EVTOMCUFLAGS 1361 // I2C_IRQ Interrupt event from I2C 1362 // AON_RTC_COMB Event from AON_RTC, controlled by the 1363 // AON_RTC:CTL.COMB_EV_MASK setting 1364 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1365 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1366 // settings 1367 // NONE Always inactive 1368 #define EVENT_GPT0BCAPTSEL_EV_W 7 1369 #define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F 1370 #define EVENT_GPT0BCAPTSEL_EV_S 0 1371 #define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1372 #define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 1373 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1374 #define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 1375 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1376 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 1377 #define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1378 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1379 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1380 #define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1381 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B 1382 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A 1383 #define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1384 #define EVENT_GPT0BCAPTSEL_EV_RFC_IN_EV5 0x00000060 1385 #define EVENT_GPT0BCAPTSEL_EV_RFC_IN_EV4 0x0000005F 1386 #define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 1387 #define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 1388 #define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 1389 #define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 1390 #define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 1391 #define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 1392 #define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 1393 #define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F 1394 #define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E 1395 #define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D 1396 #define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 1397 #define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 1398 #define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 1399 #define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E 1400 #define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B 1401 #define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 1402 #define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 1403 #define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 1404 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B 1405 #define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 1406 #define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 1407 #define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1408 #define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 1409 1410 //***************************************************************************** 1411 // 1412 // Register: EVENT_O_GPT1ACAPTSEL 1413 // 1414 //***************************************************************************** 1415 // Field: [6:0] EV 1416 // 1417 // Read/write selection value 1418 // ENUMs: 1419 // ALWAYS_ACTIVE Always asserted 1420 // AON_RTC_UPD RTC periodic event controlled by 1421 // AON_RTC:CTL.RTC_UPD_EN 1422 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1423 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1424 // are found here AUX_EVCTL:EVTOMCUFLAGS 1425 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1426 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1427 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1428 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1429 // AUX_ADC_DONE AUX ADC done, corresponds to 1430 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1431 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1432 // AUX_SMPH:AUTOTAKE 1433 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1434 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1435 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1436 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1437 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1438 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1439 // AUX_TDC status AUX_TDC:STAT.DONE 1440 // AUX_COMPB AUX Compare B event, corresponds to 1441 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1442 // AUX_COMPA AUX Compare A event, corresponds to 1443 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1444 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1445 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1446 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 1447 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 1448 // PORT_EVENT3 Port capture event from IOC, configured by 1449 // IOC:IOCFGn.PORT_ID. Events on ports configured 1450 // with ENUM PORT_EVENT3 wil be routed here. 1451 // PORT_EVENT2 Port capture event from IOC, configured by 1452 // IOC:IOCFGn.PORT_ID. Events on ports configured 1453 // with ENUM PORT_EVENT2 wil be routed here. 1454 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1455 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1456 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1457 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1458 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1459 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1460 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1461 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1462 // UART0_COMB UART0 combined interrupt, interrupt flags are 1463 // found here UART0:MIS 1464 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1465 // here SSI1:MIS 1466 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1467 // here SSI0:MIS 1468 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1469 // Corresponding flags are here 1470 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1471 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1472 // RFC_CPE_1 event 1473 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1474 // Corresponding flags are here 1475 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1476 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1477 // RFC_CPE_0 event 1478 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1479 // flag is here RFC_DBELL:RFHWIFG 1480 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1481 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1482 // FLASH FLASH controller error event, the status flags 1483 // are FLASH:FEDACSTAT.FSM_DONE and 1484 // FLASH:FEDACSTAT.RVF_INT 1485 // AUX_COMB AUX combined event, the corresponding flag 1486 // register is here AUX_EVCTL:EVTOMCUFLAGS 1487 // I2C_IRQ Interrupt event from I2C 1488 // AON_RTC_COMB Event from AON_RTC, controlled by the 1489 // AON_RTC:CTL.COMB_EV_MASK setting 1490 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1491 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1492 // settings 1493 // NONE Always inactive 1494 #define EVENT_GPT1ACAPTSEL_EV_W 7 1495 #define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F 1496 #define EVENT_GPT1ACAPTSEL_EV_S 0 1497 #define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1498 #define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1499 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1500 #define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1501 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1502 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1503 #define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1504 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1505 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1506 #define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1507 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B 1508 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A 1509 #define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1510 #define EVENT_GPT1ACAPTSEL_EV_RFC_IN_EV5 0x00000060 1511 #define EVENT_GPT1ACAPTSEL_EV_RFC_IN_EV4 0x0000005F 1512 #define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 1513 #define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 1514 #define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 1515 #define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 1516 #define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 1517 #define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 1518 #define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 1519 #define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1520 #define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1521 #define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1522 #define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 1523 #define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 1524 #define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 1525 #define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1526 #define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1527 #define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1528 #define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1529 #define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 1530 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B 1531 #define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 1532 #define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 1533 #define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1534 #define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 1535 1536 //***************************************************************************** 1537 // 1538 // Register: EVENT_O_GPT1BCAPTSEL 1539 // 1540 //***************************************************************************** 1541 // Field: [6:0] EV 1542 // 1543 // Read/write selection value 1544 // ENUMs: 1545 // ALWAYS_ACTIVE Always asserted 1546 // AON_RTC_UPD RTC periodic event controlled by 1547 // AON_RTC:CTL.RTC_UPD_EN 1548 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1549 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1550 // are found here AUX_EVCTL:EVTOMCUFLAGS 1551 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1552 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1553 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1554 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1555 // AUX_ADC_DONE AUX ADC done, corresponds to 1556 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1557 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1558 // AUX_SMPH:AUTOTAKE 1559 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1560 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1561 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1562 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1563 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1564 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1565 // AUX_TDC status AUX_TDC:STAT.DONE 1566 // AUX_COMPB AUX Compare B event, corresponds to 1567 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1568 // AUX_COMPA AUX Compare A event, corresponds to 1569 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1570 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1571 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1572 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 1573 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 1574 // PORT_EVENT3 Port capture event from IOC, configured by 1575 // IOC:IOCFGn.PORT_ID. Events on ports configured 1576 // with ENUM PORT_EVENT3 wil be routed here. 1577 // PORT_EVENT2 Port capture event from IOC, configured by 1578 // IOC:IOCFGn.PORT_ID. Events on ports configured 1579 // with ENUM PORT_EVENT2 wil be routed here. 1580 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1581 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1582 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1583 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1584 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1585 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1586 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1587 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1588 // UART0_COMB UART0 combined interrupt, interrupt flags are 1589 // found here UART0:MIS 1590 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1591 // here SSI1:MIS 1592 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1593 // here SSI0:MIS 1594 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1595 // Corresponding flags are here 1596 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1597 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1598 // RFC_CPE_1 event 1599 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1600 // Corresponding flags are here 1601 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1602 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1603 // RFC_CPE_0 event 1604 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1605 // flag is here RFC_DBELL:RFHWIFG 1606 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1607 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1608 // FLASH FLASH controller error event, the status flags 1609 // are FLASH:FEDACSTAT.FSM_DONE and 1610 // FLASH:FEDACSTAT.RVF_INT 1611 // AUX_COMB AUX combined event, the corresponding flag 1612 // register is here AUX_EVCTL:EVTOMCUFLAGS 1613 // I2C_IRQ Interrupt event from I2C 1614 // AON_RTC_COMB Event from AON_RTC, controlled by the 1615 // AON_RTC:CTL.COMB_EV_MASK setting 1616 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1617 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1618 // settings 1619 // NONE Always inactive 1620 #define EVENT_GPT1BCAPTSEL_EV_W 7 1621 #define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F 1622 #define EVENT_GPT1BCAPTSEL_EV_S 0 1623 #define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1624 #define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 1625 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1626 #define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 1627 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1628 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 1629 #define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1630 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1631 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1632 #define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1633 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B 1634 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A 1635 #define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1636 #define EVENT_GPT1BCAPTSEL_EV_RFC_IN_EV5 0x00000060 1637 #define EVENT_GPT1BCAPTSEL_EV_RFC_IN_EV4 0x0000005F 1638 #define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 1639 #define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 1640 #define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 1641 #define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 1642 #define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 1643 #define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 1644 #define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 1645 #define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F 1646 #define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E 1647 #define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D 1648 #define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 1649 #define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 1650 #define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 1651 #define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E 1652 #define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B 1653 #define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 1654 #define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 1655 #define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 1656 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B 1657 #define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 1658 #define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 1659 #define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1660 #define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 1661 1662 //***************************************************************************** 1663 // 1664 // Register: EVENT_O_GPT2ACAPTSEL 1665 // 1666 //***************************************************************************** 1667 // Field: [6:0] EV 1668 // 1669 // Read/write selection value 1670 // ENUMs: 1671 // ALWAYS_ACTIVE Always asserted 1672 // AON_RTC_UPD RTC periodic event controlled by 1673 // AON_RTC:CTL.RTC_UPD_EN 1674 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1675 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1676 // are found here AUX_EVCTL:EVTOMCUFLAGS 1677 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1678 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1679 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1680 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1681 // AUX_ADC_DONE AUX ADC done, corresponds to 1682 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1683 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1684 // AUX_SMPH:AUTOTAKE 1685 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1686 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1687 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1688 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1689 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1690 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1691 // AUX_TDC status AUX_TDC:STAT.DONE 1692 // AUX_COMPB AUX Compare B event, corresponds to 1693 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1694 // AUX_COMPA AUX Compare A event, corresponds to 1695 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1696 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1697 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1698 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 1699 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 1700 // PORT_EVENT5 Port capture event from IOC, configured by 1701 // IOC:IOCFGn.PORT_ID. Events on ports configured 1702 // with ENUM PORT_EVENT4 wil be routed here. 1703 // PORT_EVENT4 Port capture event from IOC, configured by 1704 // IOC:IOCFGn.PORT_ID. Events on ports configured 1705 // with ENUM PORT_EVENT4 wil be routed here. 1706 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1707 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1708 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1709 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1710 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1711 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1712 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1713 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1714 // UART0_COMB UART0 combined interrupt, interrupt flags are 1715 // found here UART0:MIS 1716 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1717 // here SSI1:MIS 1718 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1719 // here SSI0:MIS 1720 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1721 // Corresponding flags are here 1722 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1723 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1724 // RFC_CPE_1 event 1725 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1726 // Corresponding flags are here 1727 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1728 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1729 // RFC_CPE_0 event 1730 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1731 // flag is here RFC_DBELL:RFHWIFG 1732 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1733 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1734 // FLASH FLASH controller error event, the status flags 1735 // are FLASH:FEDACSTAT.FSM_DONE and 1736 // FLASH:FEDACSTAT.RVF_INT 1737 // AUX_COMB AUX combined event, the corresponding flag 1738 // register is here AUX_EVCTL:EVTOMCUFLAGS 1739 // I2C_IRQ Interrupt event from I2C 1740 // AON_RTC_COMB Event from AON_RTC, controlled by the 1741 // AON_RTC:CTL.COMB_EV_MASK setting 1742 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1743 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1744 // settings 1745 // NONE Always inactive 1746 #define EVENT_GPT2ACAPTSEL_EV_W 7 1747 #define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F 1748 #define EVENT_GPT2ACAPTSEL_EV_S 0 1749 #define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1750 #define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1751 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1752 #define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1753 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1754 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1755 #define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1756 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1757 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1758 #define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1759 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B 1760 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A 1761 #define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1762 #define EVENT_GPT2ACAPTSEL_EV_RFC_IN_EV7 0x00000062 1763 #define EVENT_GPT2ACAPTSEL_EV_RFC_IN_EV6 0x00000061 1764 #define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A 1765 #define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 1766 #define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 1767 #define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 1768 #define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 1769 #define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 1770 #define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 1771 #define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1772 #define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1773 #define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1774 #define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 1775 #define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 1776 #define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 1777 #define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1778 #define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1779 #define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1780 #define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1781 #define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 1782 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B 1783 #define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 1784 #define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 1785 #define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1786 #define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 1787 1788 //***************************************************************************** 1789 // 1790 // Register: EVENT_O_GPT2BCAPTSEL 1791 // 1792 //***************************************************************************** 1793 // Field: [6:0] EV 1794 // 1795 // Read/write selection value 1796 // ENUMs: 1797 // ALWAYS_ACTIVE Always asserted 1798 // AON_RTC_UPD RTC periodic event controlled by 1799 // AON_RTC:CTL.RTC_UPD_EN 1800 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1801 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 1802 // are found here AUX_EVCTL:EVTOMCUFLAGS 1803 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1804 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 1805 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1806 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 1807 // AUX_ADC_DONE AUX ADC done, corresponds to 1808 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 1809 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1810 // AUX_SMPH:AUTOTAKE 1811 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1812 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 1813 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1814 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 1815 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1816 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 1817 // AUX_TDC status AUX_TDC:STAT.DONE 1818 // AUX_COMPB AUX Compare B event, corresponds to 1819 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1820 // AUX_COMPA AUX Compare A event, corresponds to 1821 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1822 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 1823 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 1824 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 1825 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 1826 // PORT_EVENT5 Port capture event from IOC, configured by 1827 // IOC:IOCFGn.PORT_ID. Events on ports configured 1828 // with ENUM PORT_EVENT4 wil be routed here. 1829 // PORT_EVENT4 Port capture event from IOC, configured by 1830 // IOC:IOCFGn.PORT_ID. Events on ports configured 1831 // with ENUM PORT_EVENT4 wil be routed here. 1832 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1833 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1834 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1835 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1836 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1837 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1838 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1839 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1840 // UART0_COMB UART0 combined interrupt, interrupt flags are 1841 // found here UART0:MIS 1842 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 1843 // here SSI1:MIS 1844 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1845 // here SSI0:MIS 1846 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1847 // Corresponding flags are here 1848 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1849 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1850 // RFC_CPE_1 event 1851 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1852 // Corresponding flags are here 1853 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1854 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1855 // RFC_CPE_0 event 1856 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 1857 // flag is here RFC_DBELL:RFHWIFG 1858 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1859 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1860 // FLASH FLASH controller error event, the status flags 1861 // are FLASH:FEDACSTAT.FSM_DONE and 1862 // FLASH:FEDACSTAT.RVF_INT 1863 // AUX_COMB AUX combined event, the corresponding flag 1864 // register is here AUX_EVCTL:EVTOMCUFLAGS 1865 // I2C_IRQ Interrupt event from I2C 1866 // AON_RTC_COMB Event from AON_RTC, controlled by the 1867 // AON_RTC:CTL.COMB_EV_MASK setting 1868 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1869 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1870 // settings 1871 // NONE Always inactive 1872 #define EVENT_GPT2BCAPTSEL_EV_W 7 1873 #define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F 1874 #define EVENT_GPT2BCAPTSEL_EV_S 0 1875 #define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1876 #define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 1877 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1878 #define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 1879 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1880 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 1881 #define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1882 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1883 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1884 #define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1885 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B 1886 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A 1887 #define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1888 #define EVENT_GPT2BCAPTSEL_EV_RFC_IN_EV7 0x00000062 1889 #define EVENT_GPT2BCAPTSEL_EV_RFC_IN_EV6 0x00000061 1890 #define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A 1891 #define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 1892 #define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 1893 #define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 1894 #define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 1895 #define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 1896 #define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 1897 #define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F 1898 #define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E 1899 #define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D 1900 #define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 1901 #define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 1902 #define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 1903 #define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E 1904 #define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B 1905 #define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 1906 #define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 1907 #define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 1908 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B 1909 #define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 1910 #define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 1911 #define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1912 #define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 1913 1914 //***************************************************************************** 1915 // 1916 // Register: EVENT_O_UDMACH1SSEL 1917 // 1918 //***************************************************************************** 1919 // Field: [6:0] EV 1920 // 1921 // Read only selection value 1922 // ENUMs: 1923 // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by 1924 // UART0:DMACTL.RXDMAE 1925 #define EVENT_UDMACH1SSEL_EV_W 7 1926 #define EVENT_UDMACH1SSEL_EV_M 0x0000007F 1927 #define EVENT_UDMACH1SSEL_EV_S 0 1928 #define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 1929 1930 //***************************************************************************** 1931 // 1932 // Register: EVENT_O_UDMACH1BSEL 1933 // 1934 //***************************************************************************** 1935 // Field: [6:0] EV 1936 // 1937 // Read only selection value 1938 // ENUMs: 1939 // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by 1940 // UART0:DMACTL.RXDMAE 1941 #define EVENT_UDMACH1BSEL_EV_W 7 1942 #define EVENT_UDMACH1BSEL_EV_M 0x0000007F 1943 #define EVENT_UDMACH1BSEL_EV_S 0 1944 #define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 1945 1946 //***************************************************************************** 1947 // 1948 // Register: EVENT_O_UDMACH2SSEL 1949 // 1950 //***************************************************************************** 1951 // Field: [6:0] EV 1952 // 1953 // Read only selection value 1954 // ENUMs: 1955 // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by 1956 // UART0:DMACTL.TXDMAE 1957 #define EVENT_UDMACH2SSEL_EV_W 7 1958 #define EVENT_UDMACH2SSEL_EV_M 0x0000007F 1959 #define EVENT_UDMACH2SSEL_EV_S 0 1960 #define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 1961 1962 //***************************************************************************** 1963 // 1964 // Register: EVENT_O_UDMACH2BSEL 1965 // 1966 //***************************************************************************** 1967 // Field: [6:0] EV 1968 // 1969 // Read only selection value 1970 // ENUMs: 1971 // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by 1972 // UART0:DMACTL.TXDMAE 1973 #define EVENT_UDMACH2BSEL_EV_W 7 1974 #define EVENT_UDMACH2BSEL_EV_M 0x0000007F 1975 #define EVENT_UDMACH2BSEL_EV_S 0 1976 #define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 1977 1978 //***************************************************************************** 1979 // 1980 // Register: EVENT_O_UDMACH3SSEL 1981 // 1982 //***************************************************************************** 1983 // Field: [6:0] EV 1984 // 1985 // Read only selection value 1986 // ENUMs: 1987 // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by 1988 // SSI0:DMACR.RXDMAE 1989 #define EVENT_UDMACH3SSEL_EV_W 7 1990 #define EVENT_UDMACH3SSEL_EV_M 0x0000007F 1991 #define EVENT_UDMACH3SSEL_EV_S 0 1992 #define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 1993 1994 //***************************************************************************** 1995 // 1996 // Register: EVENT_O_UDMACH3BSEL 1997 // 1998 //***************************************************************************** 1999 // Field: [6:0] EV 2000 // 2001 // Read only selection value 2002 // ENUMs: 2003 // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by 2004 // SSI0:DMACR.RXDMAE 2005 #define EVENT_UDMACH3BSEL_EV_W 7 2006 #define EVENT_UDMACH3BSEL_EV_M 0x0000007F 2007 #define EVENT_UDMACH3BSEL_EV_S 0 2008 #define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 2009 2010 //***************************************************************************** 2011 // 2012 // Register: EVENT_O_UDMACH4SSEL 2013 // 2014 //***************************************************************************** 2015 // Field: [6:0] EV 2016 // 2017 // Read only selection value 2018 // ENUMs: 2019 // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by 2020 // SSI0:DMACR.TXDMAE 2021 #define EVENT_UDMACH4SSEL_EV_W 7 2022 #define EVENT_UDMACH4SSEL_EV_M 0x0000007F 2023 #define EVENT_UDMACH4SSEL_EV_S 0 2024 #define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B 2025 2026 //***************************************************************************** 2027 // 2028 // Register: EVENT_O_UDMACH4BSEL 2029 // 2030 //***************************************************************************** 2031 // Field: [6:0] EV 2032 // 2033 // Read only selection value 2034 // ENUMs: 2035 // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by 2036 // SSI0:DMACR.TXDMAE 2037 #define EVENT_UDMACH4BSEL_EV_W 7 2038 #define EVENT_UDMACH4BSEL_EV_M 0x0000007F 2039 #define EVENT_UDMACH4BSEL_EV_S 0 2040 #define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A 2041 2042 //***************************************************************************** 2043 // 2044 // Register: EVENT_O_UDMACH5SSEL 2045 // 2046 //***************************************************************************** 2047 //***************************************************************************** 2048 // 2049 // Register: EVENT_O_UDMACH5BSEL 2050 // 2051 //***************************************************************************** 2052 //***************************************************************************** 2053 // 2054 // Register: EVENT_O_UDMACH6SSEL 2055 // 2056 //***************************************************************************** 2057 //***************************************************************************** 2058 // 2059 // Register: EVENT_O_UDMACH6BSEL 2060 // 2061 //***************************************************************************** 2062 //***************************************************************************** 2063 // 2064 // Register: EVENT_O_UDMACH7SSEL 2065 // 2066 //***************************************************************************** 2067 // Field: [6:0] EV 2068 // 2069 // Read only selection value 2070 // ENUMs: 2071 // AUX_DMASREQ DMA single request event from AUX, configured by 2072 // AUX_EVCTL:DMACTL 2073 #define EVENT_UDMACH7SSEL_EV_W 7 2074 #define EVENT_UDMACH7SSEL_EV_M 0x0000007F 2075 #define EVENT_UDMACH7SSEL_EV_S 0 2076 #define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 2077 2078 //***************************************************************************** 2079 // 2080 // Register: EVENT_O_UDMACH7BSEL 2081 // 2082 //***************************************************************************** 2083 // Field: [6:0] EV 2084 // 2085 // Read only selection value 2086 // ENUMs: 2087 // AUX_DMABREQ DMA burst request event from AUX, configured by 2088 // AUX_EVCTL:DMACTL 2089 #define EVENT_UDMACH7BSEL_EV_W 7 2090 #define EVENT_UDMACH7BSEL_EV_M 0x0000007F 2091 #define EVENT_UDMACH7BSEL_EV_S 0 2092 #define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 2093 2094 //***************************************************************************** 2095 // 2096 // Register: EVENT_O_UDMACH8SSEL 2097 // 2098 //***************************************************************************** 2099 // Field: [6:0] EV 2100 // 2101 // Read only selection value 2102 // ENUMs: 2103 // AUX_SW_DMABREQ AUX observation loopback 2104 #define EVENT_UDMACH8SSEL_EV_W 7 2105 #define EVENT_UDMACH8SSEL_EV_M 0x0000007F 2106 #define EVENT_UDMACH8SSEL_EV_S 0 2107 #define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 2108 2109 //***************************************************************************** 2110 // 2111 // Register: EVENT_O_UDMACH8BSEL 2112 // 2113 //***************************************************************************** 2114 // Field: [6:0] EV 2115 // 2116 // Read only selection value 2117 // ENUMs: 2118 // AUX_SW_DMABREQ AUX observation loopback 2119 #define EVENT_UDMACH8BSEL_EV_W 7 2120 #define EVENT_UDMACH8BSEL_EV_M 0x0000007F 2121 #define EVENT_UDMACH8BSEL_EV_S 0 2122 #define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 2123 2124 //***************************************************************************** 2125 // 2126 // Register: EVENT_O_UDMACH9SSEL 2127 // 2128 //***************************************************************************** 2129 // Field: [6:0] EV 2130 // 2131 // Read/write selection value 2132 // ENUMs: 2133 // ALWAYS_ACTIVE Always asserted 2134 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2135 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2136 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2137 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2138 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2139 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2140 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2141 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2142 // TIE_LOW Not used tied to 0 2143 // NONE Always inactive 2144 #define EVENT_UDMACH9SSEL_EV_W 7 2145 #define EVENT_UDMACH9SSEL_EV_M 0x0000007F 2146 #define EVENT_UDMACH9SSEL_EV_S 0 2147 #define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 2148 #define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 2149 #define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 2150 #define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 2151 #define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 2152 #define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 2153 #define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F 2154 #define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E 2155 #define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D 2156 #define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 2157 #define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 2158 2159 //***************************************************************************** 2160 // 2161 // Register: EVENT_O_UDMACH9BSEL 2162 // 2163 //***************************************************************************** 2164 // Field: [6:0] EV 2165 // 2166 // Read/write selection value 2167 // ENUMs: 2168 // ALWAYS_ACTIVE Always asserted 2169 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2170 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2171 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2172 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2173 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2174 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2175 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2176 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2177 // NONE Always inactive 2178 #define EVENT_UDMACH9BSEL_EV_W 7 2179 #define EVENT_UDMACH9BSEL_EV_M 0x0000007F 2180 #define EVENT_UDMACH9BSEL_EV_S 0 2181 #define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 2182 #define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 2183 #define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 2184 #define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 2185 #define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 2186 #define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 2187 #define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F 2188 #define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E 2189 #define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D 2190 #define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 2191 2192 //***************************************************************************** 2193 // 2194 // Register: EVENT_O_UDMACH10SSEL 2195 // 2196 //***************************************************************************** 2197 // Field: [6:0] EV 2198 // 2199 // Read/write selection value 2200 // ENUMs: 2201 // ALWAYS_ACTIVE Always asserted 2202 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2203 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2204 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2205 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2206 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2207 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2208 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2209 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2210 // TIE_LOW Not used tied to 0 2211 // NONE Always inactive 2212 #define EVENT_UDMACH10SSEL_EV_W 7 2213 #define EVENT_UDMACH10SSEL_EV_M 0x0000007F 2214 #define EVENT_UDMACH10SSEL_EV_S 0 2215 #define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 2216 #define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 2217 #define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 2218 #define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 2219 #define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 2220 #define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 2221 #define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F 2222 #define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E 2223 #define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D 2224 #define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 2225 #define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 2226 2227 //***************************************************************************** 2228 // 2229 // Register: EVENT_O_UDMACH10BSEL 2230 // 2231 //***************************************************************************** 2232 // Field: [6:0] EV 2233 // 2234 // Read/write selection value 2235 // ENUMs: 2236 // ALWAYS_ACTIVE Always asserted 2237 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2238 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2239 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2240 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2241 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2242 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2243 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2244 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2245 // NONE Always inactive 2246 #define EVENT_UDMACH10BSEL_EV_W 7 2247 #define EVENT_UDMACH10BSEL_EV_M 0x0000007F 2248 #define EVENT_UDMACH10BSEL_EV_S 0 2249 #define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 2250 #define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 2251 #define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 2252 #define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 2253 #define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 2254 #define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 2255 #define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F 2256 #define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E 2257 #define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D 2258 #define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 2259 2260 //***************************************************************************** 2261 // 2262 // Register: EVENT_O_UDMACH11SSEL 2263 // 2264 //***************************************************************************** 2265 // Field: [6:0] EV 2266 // 2267 // Read/write selection value 2268 // ENUMs: 2269 // ALWAYS_ACTIVE Always asserted 2270 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2271 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2272 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2273 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2274 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2275 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2276 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2277 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2278 // TIE_LOW Not used tied to 0 2279 // NONE Always inactive 2280 #define EVENT_UDMACH11SSEL_EV_W 7 2281 #define EVENT_UDMACH11SSEL_EV_M 0x0000007F 2282 #define EVENT_UDMACH11SSEL_EV_S 0 2283 #define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 2284 #define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 2285 #define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 2286 #define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 2287 #define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 2288 #define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 2289 #define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F 2290 #define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E 2291 #define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D 2292 #define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 2293 #define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 2294 2295 //***************************************************************************** 2296 // 2297 // Register: EVENT_O_UDMACH11BSEL 2298 // 2299 //***************************************************************************** 2300 // Field: [6:0] EV 2301 // 2302 // Read/write selection value 2303 // ENUMs: 2304 // ALWAYS_ACTIVE Always asserted 2305 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2306 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2307 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2308 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2309 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2310 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2311 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2312 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2313 // NONE Always inactive 2314 #define EVENT_UDMACH11BSEL_EV_W 7 2315 #define EVENT_UDMACH11BSEL_EV_M 0x0000007F 2316 #define EVENT_UDMACH11BSEL_EV_S 0 2317 #define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 2318 #define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 2319 #define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 2320 #define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 2321 #define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 2322 #define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 2323 #define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F 2324 #define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E 2325 #define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D 2326 #define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 2327 2328 //***************************************************************************** 2329 // 2330 // Register: EVENT_O_UDMACH12SSEL 2331 // 2332 //***************************************************************************** 2333 // Field: [6:0] EV 2334 // 2335 // Read/write selection value 2336 // ENUMs: 2337 // ALWAYS_ACTIVE Always asserted 2338 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2339 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2340 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2341 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2342 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2343 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2344 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2345 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2346 // TIE_LOW Not used tied to 0 2347 // NONE Always inactive 2348 #define EVENT_UDMACH12SSEL_EV_W 7 2349 #define EVENT_UDMACH12SSEL_EV_M 0x0000007F 2350 #define EVENT_UDMACH12SSEL_EV_S 0 2351 #define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 2352 #define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 2353 #define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 2354 #define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 2355 #define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 2356 #define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 2357 #define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F 2358 #define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E 2359 #define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D 2360 #define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 2361 #define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 2362 2363 //***************************************************************************** 2364 // 2365 // Register: EVENT_O_UDMACH12BSEL 2366 // 2367 //***************************************************************************** 2368 // Field: [6:0] EV 2369 // 2370 // Read/write selection value 2371 // ENUMs: 2372 // ALWAYS_ACTIVE Always asserted 2373 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2374 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2375 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2376 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2377 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2378 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2379 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2380 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2381 // NONE Always inactive 2382 #define EVENT_UDMACH12BSEL_EV_W 7 2383 #define EVENT_UDMACH12BSEL_EV_M 0x0000007F 2384 #define EVENT_UDMACH12BSEL_EV_S 0 2385 #define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 2386 #define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 2387 #define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 2388 #define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 2389 #define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 2390 #define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 2391 #define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F 2392 #define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E 2393 #define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D 2394 #define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 2395 2396 //***************************************************************************** 2397 // 2398 // Register: EVENT_O_UDMACH13BSEL 2399 // 2400 //***************************************************************************** 2401 // Field: [6:0] EV 2402 // 2403 // Read only selection value 2404 // ENUMs: 2405 // AON_PROG2 AON programmable event 2. Event selected by 2406 // AON_EVENT MCU event selector, 2407 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 2408 #define EVENT_UDMACH13BSEL_EV_W 7 2409 #define EVENT_UDMACH13BSEL_EV_M 0x0000007F 2410 #define EVENT_UDMACH13BSEL_EV_S 0 2411 #define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 2412 2413 //***************************************************************************** 2414 // 2415 // Register: EVENT_O_UDMACH14BSEL 2416 // 2417 //***************************************************************************** 2418 // Field: [6:0] EV 2419 // 2420 // Read/write selection value 2421 // ENUMs: 2422 // ALWAYS_ACTIVE Always asserted 2423 // CPU_HALTED CPU halted 2424 // AON_RTC_UPD RTC periodic event controlled by 2425 // AON_RTC:CTL.RTC_UPD_EN 2426 // AUX_DMABREQ DMA burst request event from AUX, configured by 2427 // AUX_EVCTL:DMACTL 2428 // AUX_DMASREQ DMA single request event from AUX, configured by 2429 // AUX_EVCTL:DMACTL 2430 // AUX_SW_DMABREQ AUX observation loopback 2431 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 2432 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 2433 // are found here AUX_EVCTL:EVTOMCUFLAGS 2434 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 2435 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 2436 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 2437 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 2438 // AUX_ADC_DONE AUX ADC done, corresponds to 2439 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 2440 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 2441 // AUX_SMPH:AUTOTAKE 2442 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 2443 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 2444 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 2445 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 2446 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 2447 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 2448 // AUX_TDC status AUX_TDC:STAT.DONE 2449 // AUX_COMPB AUX Compare B event, corresponds to 2450 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 2451 // AUX_COMPA AUX Compare A event, corresponds to 2452 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 2453 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 2454 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 2455 // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN 2456 // SWEV3 Software event 3, triggered by SWEV.SWEV3 2457 // SWEV2 Software event 2, triggered by SWEV.SWEV2 2458 // SWEV1 Software event 1, triggered by SWEV.SWEV1 2459 // SWEV0 Software event 0, triggered by SWEV.SWEV0 2460 // WDT_NMI Watchdog non maskable interrupt event, controlled 2461 // by WDT:CTL.INTTYPE 2462 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 2463 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 2464 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 2465 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 2466 // CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg 2467 // flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled 2468 // by CRYPTO:IRQEN.DMA_IN_DONE 2469 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 2470 // corresponding flag is found here 2471 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 2472 // CRYPTO:IRQSTAT.RESULT_AVAIL 2473 // PORT_EVENT7 Port capture event from IOC, configured by 2474 // IOC:IOCFGn.PORT_ID. Events on ports configured 2475 // with ENUM PORT_EVENT7 wil be routed here. 2476 // PORT_EVENT6 Port capture event from IOC, configured by 2477 // IOC:IOCFGn.PORT_ID. Events on ports configured 2478 // with ENUM PORT_EVENT6 wil be routed here. 2479 // PORT_EVENT5 Port capture event from IOC, configured by 2480 // IOC:IOCFGn.PORT_ID. Events on ports configured 2481 // with ENUM PORT_EVENT4 wil be routed here. 2482 // PORT_EVENT4 Port capture event from IOC, configured by 2483 // IOC:IOCFGn.PORT_ID. Events on ports configured 2484 // with ENUM PORT_EVENT4 wil be routed here. 2485 // PORT_EVENT3 Port capture event from IOC, configured by 2486 // IOC:IOCFGn.PORT_ID. Events on ports configured 2487 // with ENUM PORT_EVENT3 wil be routed here. 2488 // PORT_EVENT2 Port capture event from IOC, configured by 2489 // IOC:IOCFGn.PORT_ID. Events on ports configured 2490 // with ENUM PORT_EVENT2 wil be routed here. 2491 // PORT_EVENT1 Port capture event from IOC, configured by 2492 // IOC:IOCFGn.PORT_ID. Events on ports configured 2493 // with ENUM PORT_EVENT1 wil be routed here. 2494 // PORT_EVENT0 Port capture event from IOC, configured by 2495 // IOC:IOCFGn.PORT_ID. Events on ports configured 2496 // with ENUM PORT_EVENT0 wil be routed here. 2497 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2498 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2499 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2500 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2501 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2502 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2503 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2504 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2505 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 2506 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 2507 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 2508 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 2509 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 2510 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 2511 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 2512 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 2513 // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by 2514 // UART0:DMACTL.TXDMAE 2515 // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by 2516 // UART0:DMACTL.TXDMAE 2517 // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by 2518 // UART0:DMACTL.RXDMAE 2519 // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by 2520 // UART0:DMACTL.RXDMAE 2521 // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by 2522 // SSI0:DMACR.TXDMAE 2523 // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by 2524 // SSI0:DMACR.TXDMAE 2525 // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by 2526 // SSI0:DMACR.RXDMAE 2527 // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by 2528 // SSI0:DMACR.RXDMAE 2529 // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by 2530 // SSI0:DMACR.TXDMAE 2531 // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by 2532 // SSI0:DMACR.TXDMAE 2533 // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by 2534 // SSI0:DMACR.RXDMAE 2535 // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by 2536 // SSI0:DMACR.RXDMAE 2537 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 2538 // UDMA0:REQDONE 2539 // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS 2540 // UART0_COMB UART0 combined interrupt, interrupt flags are 2541 // found here UART0:MIS 2542 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 2543 // here SSI1:MIS 2544 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 2545 // here SSI0:MIS 2546 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 2547 // Corresponding flags are here 2548 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2549 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 2550 // RFC_CPE_1 event 2551 // AUX_SWEV1 AUX software event 1, triggered by 2552 // AUX_EVCTL:SWEVSET.SWEV1, also available as 2553 // AUX_EVENT2 AON wake up event. 2554 // MCU domain wakeup control 2555 // AON_EVENT:MCUWUSEL 2556 // AUX domain wakeup control 2557 // AON_EVENT:AUXWUSEL 2558 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 2559 // Corresponding flags are here 2560 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2561 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 2562 // RFC_CPE_0 event 2563 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 2564 // flag is here RFC_DBELL:RFHWIFG 2565 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 2566 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 2567 // WDT_IRQ Watchdog interrupt event, controlled by 2568 // WDT:CTL.INTEN 2569 // DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, 2570 // see UDMA0:SOFTREQ 2571 // FLASH FLASH controller error event, the status flags 2572 // are FLASH:FEDACSTAT.FSM_DONE and 2573 // FLASH:FEDACSTAT.RVF_INT 2574 // DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see 2575 // UDMA0:SOFTREQ 2576 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 2577 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 2578 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 2579 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 2580 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 2581 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 2582 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 2583 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 2584 // AUX_COMB AUX combined event, the corresponding flag 2585 // register is here AUX_EVCTL:EVTOMCUFLAGS 2586 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 2587 // I2C_IRQ Interrupt event from I2C 2588 // I2S_IRQ Interrupt event from I2S 2589 // AON_RTC_COMB Event from AON_RTC, controlled by the 2590 // AON_RTC:CTL.COMB_EV_MASK setting 2591 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 2592 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 2593 // settings 2594 // AON_PROG2 AON programmable event 2. Event selected by 2595 // AON_EVENT MCU event selector, 2596 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 2597 // AON_PROG1 AON programmable event 1. Event selected by 2598 // AON_EVENT MCU event selector, 2599 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 2600 // AON_PROG0 AON programmable event 0. Event selected by 2601 // AON_EVENT MCU event selector, 2602 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 2603 // NONE Always inactive 2604 #define EVENT_UDMACH14BSEL_EV_W 7 2605 #define EVENT_UDMACH14BSEL_EV_M 0x0000007F 2606 #define EVENT_UDMACH14BSEL_EV_S 0 2607 #define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 2608 #define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 2609 #define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 2610 #define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 2611 #define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 2612 #define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 2613 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 2614 #define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 2615 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 2616 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 2617 #define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 2618 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E 2619 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D 2620 #define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C 2621 #define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B 2622 #define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A 2623 #define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 2624 #define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 2625 #define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 2626 #define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 2627 #define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 2628 #define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 2629 #define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 2630 #define EVENT_UDMACH14BSEL_EV_RFC_IN_EV7 0x00000062 2631 #define EVENT_UDMACH14BSEL_EV_RFC_IN_EV6 0x00000061 2632 #define EVENT_UDMACH14BSEL_EV_RFC_IN_EV5 0x00000060 2633 #define EVENT_UDMACH14BSEL_EV_RFC_IN_EV4 0x0000005F 2634 #define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E 2635 #define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 2636 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C 2637 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B 2638 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A 2639 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 2640 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 2641 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 2642 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 2643 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 2644 #define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 2645 #define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 2646 #define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 2647 #define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 2648 #define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 2649 #define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F 2650 #define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E 2651 #define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D 2652 #define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 2653 #define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 2654 #define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 2655 #define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 2656 #define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 2657 #define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F 2658 #define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E 2659 #define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D 2660 #define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 2661 #define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 2662 #define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 2663 #define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 2664 #define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F 2665 #define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E 2666 #define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D 2667 #define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C 2668 #define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B 2669 #define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A 2670 #define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 2671 #define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 2672 #define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 2673 #define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 2674 #define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 2675 #define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 2676 #define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 2677 #define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E 2678 #define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D 2679 #define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B 2680 #define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A 2681 #define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 2682 #define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 2683 #define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 2684 #define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 2685 #define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 2686 #define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 2687 #define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 2688 #define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 2689 #define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 2690 #define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F 2691 #define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E 2692 #define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D 2693 #define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C 2694 #define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B 2695 #define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A 2696 #define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 2697 #define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 2698 #define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 2699 #define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 2700 #define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 2701 #define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 2702 #define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 2703 #define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 2704 2705 //***************************************************************************** 2706 // 2707 // Register: EVENT_O_UDMACH15BSEL 2708 // 2709 //***************************************************************************** 2710 // Field: [6:0] EV 2711 // 2712 // Read only selection value 2713 // ENUMs: 2714 // AON_RTC_COMB Event from AON_RTC, controlled by the 2715 // AON_RTC:CTL.COMB_EV_MASK setting 2716 #define EVENT_UDMACH15BSEL_EV_W 7 2717 #define EVENT_UDMACH15BSEL_EV_M 0x0000007F 2718 #define EVENT_UDMACH15BSEL_EV_S 0 2719 #define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 2720 2721 //***************************************************************************** 2722 // 2723 // Register: EVENT_O_UDMACH16SSEL 2724 // 2725 //***************************************************************************** 2726 // Field: [6:0] EV 2727 // 2728 // Read only selection value 2729 // ENUMs: 2730 // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by 2731 // SSI0:DMACR.RXDMAE 2732 #define EVENT_UDMACH16SSEL_EV_W 7 2733 #define EVENT_UDMACH16SSEL_EV_M 0x0000007F 2734 #define EVENT_UDMACH16SSEL_EV_S 0 2735 #define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D 2736 2737 //***************************************************************************** 2738 // 2739 // Register: EVENT_O_UDMACH16BSEL 2740 // 2741 //***************************************************************************** 2742 // Field: [6:0] EV 2743 // 2744 // Read only selection value 2745 // ENUMs: 2746 // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by 2747 // SSI0:DMACR.RXDMAE 2748 #define EVENT_UDMACH16BSEL_EV_W 7 2749 #define EVENT_UDMACH16BSEL_EV_M 0x0000007F 2750 #define EVENT_UDMACH16BSEL_EV_S 0 2751 #define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C 2752 2753 //***************************************************************************** 2754 // 2755 // Register: EVENT_O_UDMACH17SSEL 2756 // 2757 //***************************************************************************** 2758 // Field: [6:0] EV 2759 // 2760 // Read only selection value 2761 // ENUMs: 2762 // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by 2763 // SSI0:DMACR.TXDMAE 2764 #define EVENT_UDMACH17SSEL_EV_W 7 2765 #define EVENT_UDMACH17SSEL_EV_M 0x0000007F 2766 #define EVENT_UDMACH17SSEL_EV_S 0 2767 #define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F 2768 2769 //***************************************************************************** 2770 // 2771 // Register: EVENT_O_UDMACH17BSEL 2772 // 2773 //***************************************************************************** 2774 // Field: [6:0] EV 2775 // 2776 // Read only selection value 2777 // ENUMs: 2778 // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by 2779 // SSI0:DMACR.TXDMAE 2780 #define EVENT_UDMACH17BSEL_EV_W 7 2781 #define EVENT_UDMACH17BSEL_EV_M 0x0000007F 2782 #define EVENT_UDMACH17BSEL_EV_S 0 2783 #define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E 2784 2785 //***************************************************************************** 2786 // 2787 // Register: EVENT_O_UDMACH21SSEL 2788 // 2789 //***************************************************************************** 2790 // Field: [6:0] EV 2791 // 2792 // Read only selection value 2793 // ENUMs: 2794 // SWEV0 Software event 0, triggered by SWEV.SWEV0 2795 #define EVENT_UDMACH21SSEL_EV_W 7 2796 #define EVENT_UDMACH21SSEL_EV_M 0x0000007F 2797 #define EVENT_UDMACH21SSEL_EV_S 0 2798 #define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 2799 2800 //***************************************************************************** 2801 // 2802 // Register: EVENT_O_UDMACH21BSEL 2803 // 2804 //***************************************************************************** 2805 // Field: [6:0] EV 2806 // 2807 // Read only selection value 2808 // ENUMs: 2809 // SWEV0 Software event 0, triggered by SWEV.SWEV0 2810 #define EVENT_UDMACH21BSEL_EV_W 7 2811 #define EVENT_UDMACH21BSEL_EV_M 0x0000007F 2812 #define EVENT_UDMACH21BSEL_EV_S 0 2813 #define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 2814 2815 //***************************************************************************** 2816 // 2817 // Register: EVENT_O_UDMACH22SSEL 2818 // 2819 //***************************************************************************** 2820 // Field: [6:0] EV 2821 // 2822 // Read only selection value 2823 // ENUMs: 2824 // SWEV1 Software event 1, triggered by SWEV.SWEV1 2825 #define EVENT_UDMACH22SSEL_EV_W 7 2826 #define EVENT_UDMACH22SSEL_EV_M 0x0000007F 2827 #define EVENT_UDMACH22SSEL_EV_S 0 2828 #define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 2829 2830 //***************************************************************************** 2831 // 2832 // Register: EVENT_O_UDMACH22BSEL 2833 // 2834 //***************************************************************************** 2835 // Field: [6:0] EV 2836 // 2837 // Read only selection value 2838 // ENUMs: 2839 // SWEV1 Software event 1, triggered by SWEV.SWEV1 2840 #define EVENT_UDMACH22BSEL_EV_W 7 2841 #define EVENT_UDMACH22BSEL_EV_M 0x0000007F 2842 #define EVENT_UDMACH22BSEL_EV_S 0 2843 #define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 2844 2845 //***************************************************************************** 2846 // 2847 // Register: EVENT_O_UDMACH23SSEL 2848 // 2849 //***************************************************************************** 2850 // Field: [6:0] EV 2851 // 2852 // Read only selection value 2853 // ENUMs: 2854 // SWEV2 Software event 2, triggered by SWEV.SWEV2 2855 #define EVENT_UDMACH23SSEL_EV_W 7 2856 #define EVENT_UDMACH23SSEL_EV_M 0x0000007F 2857 #define EVENT_UDMACH23SSEL_EV_S 0 2858 #define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 2859 2860 //***************************************************************************** 2861 // 2862 // Register: EVENT_O_UDMACH23BSEL 2863 // 2864 //***************************************************************************** 2865 // Field: [6:0] EV 2866 // 2867 // Read only selection value 2868 // ENUMs: 2869 // SWEV2 Software event 2, triggered by SWEV.SWEV2 2870 #define EVENT_UDMACH23BSEL_EV_W 7 2871 #define EVENT_UDMACH23BSEL_EV_M 0x0000007F 2872 #define EVENT_UDMACH23BSEL_EV_S 0 2873 #define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 2874 2875 //***************************************************************************** 2876 // 2877 // Register: EVENT_O_UDMACH24SSEL 2878 // 2879 //***************************************************************************** 2880 // Field: [6:0] EV 2881 // 2882 // Read only selection value 2883 // ENUMs: 2884 // SWEV3 Software event 3, triggered by SWEV.SWEV3 2885 #define EVENT_UDMACH24SSEL_EV_W 7 2886 #define EVENT_UDMACH24SSEL_EV_M 0x0000007F 2887 #define EVENT_UDMACH24SSEL_EV_S 0 2888 #define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 2889 2890 //***************************************************************************** 2891 // 2892 // Register: EVENT_O_UDMACH24BSEL 2893 // 2894 //***************************************************************************** 2895 // Field: [6:0] EV 2896 // 2897 // Read only selection value 2898 // ENUMs: 2899 // SWEV3 Software event 3, triggered by SWEV.SWEV3 2900 #define EVENT_UDMACH24BSEL_EV_W 7 2901 #define EVENT_UDMACH24BSEL_EV_M 0x0000007F 2902 #define EVENT_UDMACH24BSEL_EV_S 0 2903 #define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 2904 2905 //***************************************************************************** 2906 // 2907 // Register: EVENT_O_GPT3ACAPTSEL 2908 // 2909 //***************************************************************************** 2910 // Field: [6:0] EV 2911 // 2912 // Read/write selection value 2913 // ENUMs: 2914 // ALWAYS_ACTIVE Always asserted 2915 // AON_RTC_UPD RTC periodic event controlled by 2916 // AON_RTC:CTL.RTC_UPD_EN 2917 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 2918 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 2919 // are found here AUX_EVCTL:EVTOMCUFLAGS 2920 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 2921 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 2922 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 2923 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 2924 // AUX_ADC_DONE AUX ADC done, corresponds to 2925 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 2926 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 2927 // AUX_SMPH:AUTOTAKE 2928 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 2929 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 2930 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 2931 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 2932 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 2933 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 2934 // AUX_TDC status AUX_TDC:STAT.DONE 2935 // AUX_COMPB AUX Compare B event, corresponds to 2936 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 2937 // AUX_COMPA AUX Compare A event, corresponds to 2938 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 2939 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 2940 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 2941 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 2942 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 2943 // PORT_EVENT7 Port capture event from IOC, configured by 2944 // IOC:IOCFGn.PORT_ID. Events on ports configured 2945 // with ENUM PORT_EVENT7 wil be routed here. 2946 // PORT_EVENT6 Port capture event from IOC, configured by 2947 // IOC:IOCFGn.PORT_ID. Events on ports configured 2948 // with ENUM PORT_EVENT6 wil be routed here. 2949 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 2950 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 2951 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 2952 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 2953 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 2954 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 2955 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 2956 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 2957 // UART0_COMB UART0 combined interrupt, interrupt flags are 2958 // found here UART0:MIS 2959 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 2960 // here SSI1:MIS 2961 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 2962 // here SSI0:MIS 2963 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 2964 // Corresponding flags are here 2965 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2966 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 2967 // RFC_CPE_1 event 2968 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 2969 // Corresponding flags are here 2970 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2971 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 2972 // RFC_CPE_0 event 2973 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 2974 // flag is here RFC_DBELL:RFHWIFG 2975 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 2976 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 2977 // FLASH FLASH controller error event, the status flags 2978 // are FLASH:FEDACSTAT.FSM_DONE and 2979 // FLASH:FEDACSTAT.RVF_INT 2980 // AUX_COMB AUX combined event, the corresponding flag 2981 // register is here AUX_EVCTL:EVTOMCUFLAGS 2982 // AON_RTC_COMB Event from AON_RTC, controlled by the 2983 // AON_RTC:CTL.COMB_EV_MASK setting 2984 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 2985 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 2986 // settings 2987 // NONE Always inactive 2988 #define EVENT_GPT3ACAPTSEL_EV_W 7 2989 #define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F 2990 #define EVENT_GPT3ACAPTSEL_EV_S 0 2991 #define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 2992 #define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 2993 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 2994 #define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 2995 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 2996 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 2997 #define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 2998 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 2999 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 3000 #define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 3001 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B 3002 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A 3003 #define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 3004 #define EVENT_GPT3ACAPTSEL_EV_RFC_IN_EV7 0x00000062 3005 #define EVENT_GPT3ACAPTSEL_EV_RFC_IN_EV6 0x00000061 3006 #define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C 3007 #define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B 3008 #define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 3009 #define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 3010 #define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 3011 #define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 3012 #define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 3013 #define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F 3014 #define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E 3015 #define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D 3016 #define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 3017 #define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 3018 #define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 3019 #define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E 3020 #define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B 3021 #define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 3022 #define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 3023 #define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 3024 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B 3025 #define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 3026 #define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 3027 #define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 3028 3029 //***************************************************************************** 3030 // 3031 // Register: EVENT_O_GPT3BCAPTSEL 3032 // 3033 //***************************************************************************** 3034 // Field: [6:0] EV 3035 // 3036 // Read/write selection value 3037 // ENUMs: 3038 // ALWAYS_ACTIVE Always asserted 3039 // AON_RTC_UPD RTC periodic event controlled by 3040 // AON_RTC:CTL.RTC_UPD_EN 3041 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 3042 // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags 3043 // are found here AUX_EVCTL:EVTOMCUFLAGS 3044 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 3045 // AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 3046 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 3047 // AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 3048 // AUX_ADC_DONE AUX ADC done, corresponds to 3049 // AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 3050 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 3051 // AUX_SMPH:AUTOTAKE 3052 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 3053 // AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 3054 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 3055 // AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 3056 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 3057 // flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the 3058 // AUX_TDC status AUX_TDC:STAT.DONE 3059 // AUX_COMPB AUX Compare B event, corresponds to 3060 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 3061 // AUX_COMPA AUX Compare A event, corresponds to 3062 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 3063 // AUX_AON_WU_EV AON wakeup event, corresponds flags are here 3064 // AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV 3065 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 3066 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 3067 // PORT_EVENT7 Port capture event from IOC, configured by 3068 // IOC:IOCFGn.PORT_ID. Events on ports configured 3069 // with ENUM PORT_EVENT7 wil be routed here. 3070 // PORT_EVENT6 Port capture event from IOC, configured by 3071 // IOC:IOCFGn.PORT_ID. Events on ports configured 3072 // with ENUM PORT_EVENT6 wil be routed here. 3073 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 3074 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 3075 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 3076 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 3077 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 3078 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 3079 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 3080 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 3081 // UART0_COMB UART0 combined interrupt, interrupt flags are 3082 // found here UART0:MIS 3083 // SSI1_COMB SSI0 combined interrupt, interrupt flags are found 3084 // here SSI1:MIS 3085 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 3086 // here SSI0:MIS 3087 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 3088 // Corresponding flags are here 3089 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3090 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 3091 // RFC_CPE_1 event 3092 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 3093 // Corresponding flags are here 3094 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3095 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 3096 // RFC_CPE_0 event 3097 // RFC_HW_COMB Combined RCF hardware interrupt, corresponding 3098 // flag is here RFC_DBELL:RFHWIFG 3099 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 3100 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 3101 // FLASH FLASH controller error event, the status flags 3102 // are FLASH:FEDACSTAT.FSM_DONE and 3103 // FLASH:FEDACSTAT.RVF_INT 3104 // AUX_COMB AUX combined event, the corresponding flag 3105 // register is here AUX_EVCTL:EVTOMCUFLAGS 3106 // AON_RTC_COMB Event from AON_RTC, controlled by the 3107 // AON_RTC:CTL.COMB_EV_MASK setting 3108 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 3109 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 3110 // settings 3111 // NONE Always inactive 3112 #define EVENT_GPT3BCAPTSEL_EV_W 7 3113 #define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F 3114 #define EVENT_GPT3BCAPTSEL_EV_S 0 3115 #define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 3116 #define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 3117 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 3118 #define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 3119 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 3120 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 3121 #define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 3122 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 3123 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 3124 #define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 3125 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B 3126 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A 3127 #define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 3128 #define EVENT_GPT3BCAPTSEL_EV_RFC_IN_EV7 0x00000062 3129 #define EVENT_GPT3BCAPTSEL_EV_RFC_IN_EV6 0x00000061 3130 #define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C 3131 #define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B 3132 #define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 3133 #define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 3134 #define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 3135 #define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 3136 #define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 3137 #define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F 3138 #define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E 3139 #define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D 3140 #define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 3141 #define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 3142 #define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 3143 #define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E 3144 #define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B 3145 #define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 3146 #define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 3147 #define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 3148 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B 3149 #define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 3150 #define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 3151 #define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 3152 3153 //***************************************************************************** 3154 // 3155 // Register: EVENT_O_AUXSEL0 3156 // 3157 //***************************************************************************** 3158 // Field: [6:0] EV 3159 // 3160 // Read/write selection value 3161 // ENUMs: 3162 // ALWAYS_ACTIVE Always asserted 3163 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 3164 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 3165 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 3166 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 3167 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 3168 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 3169 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 3170 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 3171 // NONE Always inactive 3172 #define EVENT_AUXSEL0_EV_W 7 3173 #define EVENT_AUXSEL0_EV_M 0x0000007F 3174 #define EVENT_AUXSEL0_EV_S 0 3175 #define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 3176 #define EVENT_AUXSEL0_EV_GPT1B 0x00000013 3177 #define EVENT_AUXSEL0_EV_GPT1A 0x00000012 3178 #define EVENT_AUXSEL0_EV_GPT0B 0x00000011 3179 #define EVENT_AUXSEL0_EV_GPT0A 0x00000010 3180 #define EVENT_AUXSEL0_EV_GPT3B 0x0000000F 3181 #define EVENT_AUXSEL0_EV_GPT3A 0x0000000E 3182 #define EVENT_AUXSEL0_EV_GPT2B 0x0000000D 3183 #define EVENT_AUXSEL0_EV_GPT2A 0x0000000C 3184 #define EVENT_AUXSEL0_EV_NONE 0x00000000 3185 3186 //***************************************************************************** 3187 // 3188 // Register: EVENT_O_CM3NMISEL0 3189 // 3190 //***************************************************************************** 3191 // Field: [6:0] EV 3192 // 3193 // Read only selection value 3194 // ENUMs: 3195 // WDT_NMI Watchdog non maskable interrupt event, controlled 3196 // by WDT:CTL.INTTYPE 3197 #define EVENT_CM3NMISEL0_EV_W 7 3198 #define EVENT_CM3NMISEL0_EV_M 0x0000007F 3199 #define EVENT_CM3NMISEL0_EV_S 0 3200 #define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 3201 3202 //***************************************************************************** 3203 // 3204 // Register: EVENT_O_I2SSTMPSEL0 3205 // 3206 //***************************************************************************** 3207 // Field: [6:0] EV 3208 // 3209 // Read/write selection value 3210 // ENUMs: 3211 // ALWAYS_ACTIVE Always asserted 3212 // RFC_IN_EV7 RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 3213 // RFC_IN_EV6 RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 3214 // RFC_IN_EV5 RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5 3215 // RFC_IN_EV4 RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4 3216 // NONE Always inactive 3217 #define EVENT_I2SSTMPSEL0_EV_W 7 3218 #define EVENT_I2SSTMPSEL0_EV_M 0x0000007F 3219 #define EVENT_I2SSTMPSEL0_EV_S 0 3220 #define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 3221 #define EVENT_I2SSTMPSEL0_EV_RFC_IN_EV7 0x00000062 3222 #define EVENT_I2SSTMPSEL0_EV_RFC_IN_EV6 0x00000061 3223 #define EVENT_I2SSTMPSEL0_EV_RFC_IN_EV5 0x00000060 3224 #define EVENT_I2SSTMPSEL0_EV_RFC_IN_EV4 0x0000005F 3225 #define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 3226 3227 //***************************************************************************** 3228 // 3229 // Register: EVENT_O_FRZSEL0 3230 // 3231 //***************************************************************************** 3232 // Field: [6:0] EV 3233 // 3234 // Read/write selection value 3235 // ENUMs: 3236 // ALWAYS_ACTIVE Always asserted 3237 // CPU_HALTED CPU halted 3238 // NONE Always inactive 3239 #define EVENT_FRZSEL0_EV_W 7 3240 #define EVENT_FRZSEL0_EV_M 0x0000007F 3241 #define EVENT_FRZSEL0_EV_S 0 3242 #define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 3243 #define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 3244 #define EVENT_FRZSEL0_EV_NONE 0x00000000 3245 3246 //***************************************************************************** 3247 // 3248 // Register: EVENT_O_SWEV 3249 // 3250 //***************************************************************************** 3251 // Field: [24] SWEV3 3252 // 3253 // Writing "1" to this bit when the value is "0" triggers the Software 3 event. 3254 #define EVENT_SWEV_SWEV3 0x01000000 3255 #define EVENT_SWEV_SWEV3_BITN 24 3256 #define EVENT_SWEV_SWEV3_M 0x01000000 3257 #define EVENT_SWEV_SWEV3_S 24 3258 3259 // Field: [16] SWEV2 3260 // 3261 // Writing "1" to this bit when the value is "0" triggers the Software 2 event. 3262 #define EVENT_SWEV_SWEV2 0x00010000 3263 #define EVENT_SWEV_SWEV2_BITN 16 3264 #define EVENT_SWEV_SWEV2_M 0x00010000 3265 #define EVENT_SWEV_SWEV2_S 16 3266 3267 // Field: [8] SWEV1 3268 // 3269 // Writing "1" to this bit when the value is "0" triggers the Software 1 event. 3270 #define EVENT_SWEV_SWEV1 0x00000100 3271 #define EVENT_SWEV_SWEV1_BITN 8 3272 #define EVENT_SWEV_SWEV1_M 0x00000100 3273 #define EVENT_SWEV_SWEV1_S 8 3274 3275 // Field: [0] SWEV0 3276 // 3277 // Writing "1" to this bit when the value is "0" triggers the Software 0 event. 3278 #define EVENT_SWEV_SWEV0 0x00000001 3279 #define EVENT_SWEV_SWEV0_BITN 0 3280 #define EVENT_SWEV_SWEV0_M 0x00000001 3281 #define EVENT_SWEV_SWEV0_S 0 3282 3283 3284 #endif // __EVENT__ 3285