Searched refs:FPGA0_CLK_CTRL (Results 1 – 3 of 3) sorted by relevance

/lk-master/platform/zynq/
A D	clocks.c	151 return (uintptr_t)&SLCR->FPGA0_CLK_CTRL; in periph_clk_ctrl_reg()
A D	platform.c	144 SLCR_REG(FPGA0_CLK_CTRL) = zynq_clk_cfg.fpga0_clk; in zynq_clk_init()
/lk-master/platform/zynq/include/platform/
A D	zynq.h	193 uint32_t FPGA0_CLK_CTRL; // PL Clock 0 Output control member

Completed in 11 milliseconds

Last Index update Sun Aug 20 00:18:20 CST 2023