Searched refs:FPGA1_CLK_CTRL (Results 1 – 3 of 3) sorted by relevance

/lk-master/platform/zynq/
A D	clocks.c	153 return (uintptr_t)&SLCR->FPGA1_CLK_CTRL; in periph_clk_ctrl_reg()
A D	platform.c	145 SLCR_REG(FPGA1_CLK_CTRL) = zynq_clk_cfg.fpga1_clk; in zynq_clk_init()
/lk-master/platform/zynq/include/platform/
A D	zynq.h	197 uint32_t FPGA1_CLK_CTRL; // PL Clock 1 Output control member

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Last Index update Sun Aug 20 00:18:20 CST 2023