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Searched refs:HWREG (Results 1 – 25 of 97) sorted by relevance

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/lk-master/external/platform/stellaris/ti-driverlib/driverlib/
A Deeprom.c104 HWREG(0x400FD0FC) = 3; in EEPROMSetSectorMask()
106 HWREG(0x400AE2C0) = ulMask; in EEPROMSetSectorMask()
108 HWREG(0x400FD0FC) = 0; in EEPROMSetSectorMask()
122 HWREG(0x400FD0FC) = 3; in EEPROMClearSectorMask()
124 HWREG(0x400AE2C0) = 0; in EEPROMClearSectorMask()
126 HWREG(0x400FD0FC) = 0; in EEPROMClearSectorMask()
487 return(HWREG(EEPROM_EEDONE)); in EEPROMProgram()
546 return(HWREG(EEPROM_EEDONE)); in EEPROMProgramNonBlocking()
605 return(HWREG(EEPROM_EEDONE)); in EEPROMMassErase()
640 return(HWREG(EEPROM_EEPROT)); in EEPROMBlockProtectGet()
[all …]
A Dflash.c100 return(HWREG(FLASH_USECRL) + 1); in FlashUsecGet()
123 HWREG(FLASH_USECRL) = ulClocks - 1; in FlashUsecSet()
159 HWREG(FLASH_FMA) = ulAddress; in FlashErase()
600 HWREG(FLASH_FMA) = ulTemp; in FlashProtectSave()
686 HWREG(FLASH_USERREG0) = ulUser0; in FlashUserSet()
687 HWREG(FLASH_USERREG1) = ulUser1; in FlashUserSet()
723 HWREG(FLASH_FMA) = 0x80000000; in FlashUserSave()
736 HWREG(FLASH_FMA) = 0x80000001; in FlashUserSave()
834 HWREG(FLASH_FCIM) |= ulIntFlags; in FlashIntEnable()
884 return(HWREG(FLASH_FCMISC)); in FlashIntStatus()
[all …]
A Dhibernate.c231 HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL); in HibernateClockSelect()
281 ulHIBCtl = HWREG(HIB_CTL); in HibernateClockConfig()
298 HWREG(HIB_CTL) = ulHIBCtl; in HibernateClockConfig()
618 return(HWREG(HIB_RTCC)); in HibernateRTCGet()
641 HWREG(HIB_RTCM0) = ulMatch; in HibernateRTCMatch0Set()
664 return(HWREG(HIB_RTCM0)); in HibernateRTCMatch0Get()
691 HWREG(HIB_RTCM1) = ulMatch; in HibernateRTCMatch1Set()
718 return(HWREG(HIB_RTCM1)); in HibernateRTCMatch1Get()
829 HWREG(HIB_RTCT) = ulTrim; in HibernateRTCTrimSet()
854 return(HWREG(HIB_RTCT)); in HibernateRTCTrimGet()
[all …]
A Di2s.c157 while(HWREG(ulBase + I2S_O_TXLEV) >= 16) in I2STxDataPut()
164 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPut()
210 if(HWREG(ulBase + I2S_O_TXLEV) < 16) in I2STxDataPutNonBlocking()
294 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxConfigSet()
362 return(HWREG(ulBase + I2S_O_TXLIMIT)); in I2STxFIFOLimitGet()
396 return(HWREG(ulBase + I2S_O_TXLEV)); in I2STxFIFOLevelGet()
552 if(HWREG(ulBase + I2S_O_RXLEV) != 0) in I2SRxDataGetNonBlocking()
607 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2SRxConfigSet()
741 return(HWREG(ulBase + I2S_O_RXLEV)); in I2SRxFIFOLevelGet()
857 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxRxConfigSet()
[all …]
A Dtimer.c201 HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & in TimerDisable()
303 HWREG(ulBase + TIMER_O_TBMR) = in TimerConfigure()
338 HWREG(ulBase + TIMER_O_CTL) = (bInvert ? in TimerControlLevel()
375 HWREG(ulBase + TIMER_O_CTL) = (bEnable ? in TimerControlTrigger()
412 HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | in TimerControlEvent()
448 HWREG(ulBase + TIMER_O_CTL) = (bStall ? in TimerControlStall()
654 HWREG(ulBase + TIMER_O_TBPR)); in TimerPrescaleGet()
747 HWREG(ulBase + TIMER_O_TBPMR)); in TimerPrescaleMatchGet()
830 HWREG(ulBase + TIMER_O_TBILR)); in TimerLoadGet()
937 HWREG(ulBase + TIMER_O_TBR)); in TimerValueGet()
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A Duart.c184 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet()
214 return(HWREG(ulBase + UART_O_LCRH) & in UARTParityModeGet()
293 ulTemp = HWREG(ulBase + UART_O_IFLS); in UARTFIFOLevelGet()
405 HWREG(ulBase + UART_O_FR) = 0; in UARTConfigSetExpClk()
460 ulInt = HWREG(ulBase + UART_O_IBRD); in UARTConfigGetExpClk()
947 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet()
1022 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet()
1195 return(HWREG(ulBase + UART_O_DR)); in UARTCharGet()
1312 HWREG(ulBase + UART_O_LCRH) = in UARTBreakCtl()
1712 HWREG(ulBase + UART_O_ECR) = 0; in UARTRxErrorClear()
[all …]
A Di2c.c227 HWREG(ulBase + I2C_O_MTPR) = ulTPR; in I2CMasterInitExpClk()
434 HWREG(ulBase + I2C_O_SCSR) = 0; in I2CSlaveDisable()
554 HWREG(ulBase + I2C_O_MIMR) = 1; in I2CMasterIntEnable()
679 HWREG(ulBase + I2C_O_MIMR) = 0; in I2CMasterIntDisable()
1276 HWREG(ulBase + I2C_O_MCS) = ulCmd; in I2CMasterControl()
1306 ulErr = HWREG(ulBase + I2C_O_MCS); in I2CMasterErr()
1353 HWREG(ulBase + I2C_O_MDR) = ucData; in I2CMasterDataPut()
1379 return(HWREG(ulBase + I2C_O_MDR)); in I2CMasterDataGet()
1530 return(HWREG(ulBase + I2C_O_SCSR)); in I2CSlaveStatus()
1556 HWREG(ulBase + I2C_O_SDR) = ucData; in I2CSlaveDataPut()
[all …]
A Dfpu.c70 HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & in FPUEnable()
91 HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & in FPUDisable()
124 HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; in FPUStackingEnable()
155 HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; in FPULazyStackingEnable()
177 HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); in FPUStackingDisable()
205 HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode; in FPUHalfPrecisionModeSet()
231 HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode; in FPUNaNModeSet()
259 HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode; in FPUFlushToZeroModeSet()
291 HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode; in FPURoundingModeSet()
A Dlpc.c116 ulTemp = HWREG(ulBase + LPC_O_CTL); in LPCConfigSet()
119 HWREG(ulBase + LPC_O_CTL) = ulTemp; in LPCConfigSet()
205 return(HWREG(ulBase + LPC_O_STSADDR)); in LPCStatusBlockAddressGet()
237 ulStatus = HWREG(ulBase + LPC_O_STS); in LPCStatusGet()
389 ulTemp = HWREG(ulBase + LPC_O_IRQCTL); in LPCIRQSet()
391 HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; in LPCIRQSet()
427 ulTemp = HWREG(ulBase + LPC_O_IRQCTL); in LPCIRQClear()
429 HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; in LPCIRQClear()
459 return(HWREG(ulBase + LPC_O_IRQST)); in LPCIRQGet()
947 ulTemp = HWREG(ulBase + LPC_O_DMACX); in LPCChannelConfigCOMxSet()
[all …]
A Dethernet.c175 ulTemp = HWREG(ulBase + MAC_O_TCTL); in EthernetConfigSet()
178 HWREG(ulBase + MAC_O_TCTL) = ulTemp; in EthernetConfigSet()
183 ulTemp = HWREG(ulBase + MAC_O_RCTL); in EthernetConfigSet()
186 HWREG(ulBase + MAC_O_RCTL) = ulTemp; in EthernetConfigSet()
191 ulTemp = HWREG(ulBase + MAC_O_TS); in EthernetConfigSet()
194 HWREG(ulBase + MAC_O_TS) = ulTemp; in EthernetConfigSet()
287 HWREG(ulBase + MAC_O_IA0) = ulTemp; in EthernetMACAddrSet()
291 HWREG(ulBase + MAC_O_IA1) = ulTemp; in EthernetMACAddrSet()
328 ulTemp = HWREG(ulBase + MAC_O_IA0); in EthernetMACAddrGet()
333 ulTemp = HWREG(ulBase + MAC_O_IA1); in EthernetMACAddrGet()
[all …]
A Dudma.c70 HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; in uDMAEnable()
89 HWREG(UDMA_CFG) = 0; in uDMADisable()
109 return(HWREG(UDMA_ERRCLR)); in uDMAErrorStatusGet()
129 HWREG(UDMA_ERRCLR) = 1; in uDMAErrorStatusClear()
609 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelControlSet()
721 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelTransferSet()
869 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelScatterGatherSet()
946 ASSERT(HWREG(UDMA_CTLBASE) != 0); in uDMAChannelSizeGet()
1279 return(HWREG(UDMA_CHIS)); in uDMAIntStatus()
1314 HWREG(UDMA_CHIS) = ulChanMask; in uDMAIntClear()
[all …]
A Dsysctl.c480 if(HWREG(SYSCTL_DC3) & ulPin) in SysCtlPinPresent()
1760 return(HWREG(SYSCTL_RESC)); in SysCtlResetCauseGet()
2089 ulRCC = HWREG(SYSCTL_RCC); in SysCtlClockSet()
2102 HWREG(SYSCTL_RCC) = ulRCC; in SysCtlClockSet()
2163 HWREG(SYSCTL_RCC) = ulRCC; in SysCtlClockSet()
2246 HWREG(SYSCTL_RCC) = ulRCC; in SysCtlClockSet()
2284 ulRCC = HWREG(SYSCTL_RCC); in SysCtlClockGet()
2640 HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & in SysCtlPWMClockSet()
2716 HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) | in SysCtlADCSpeedSet()
2718 HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) | in SysCtlADCSpeedSet()
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A Dinterrupt.c286 ulValue = HWREG(NVIC_VTABLE); in IntRegister()
383 ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; in IntPriorityGroupingGet()
442 ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); in IntPrioritySet()
445 HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; in IntPrioritySet()
526 HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; in IntEnable()
533 HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = in IntEnable()
588 HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); in IntDisable()
595 HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = in IntDisable()
702 HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; in IntPendSet()
709 HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; in IntPendSet()
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A Dgpio.c339 ulDir = HWREG(ulPort + GPIO_O_DIR); in GPIODirModeGet()
340 ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); in GPIODirModeGet()
449 ulIBE = HWREG(ulPort + GPIO_O_IBE); in GPIOIntTypeGet()
450 ulIS = HWREG(ulPort + GPIO_O_IS); in GPIOIntTypeGet()
451 ulIEV = HWREG(ulPort + GPIO_O_IEV); in GPIOIntTypeGet()
563 HWREG(ulPort + GPIO_O_AMSEL) = in GPIOPadConfigSet()
651 HWREG(ulPort + GPIO_O_IM) |= ucPins; in GPIOPinIntEnable()
681 HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); in GPIOPinIntDisable()
714 return(HWREG(ulPort + GPIO_O_MIS)); in GPIOPinIntStatus()
758 HWREG(ulPort + GPIO_O_ICR) = ucPins; in GPIOPinIntClear()
[all …]
A Dadc.c474 HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & in ADCSequenceConfigure()
481 HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & in ADCSequenceConfigure()
565 HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & in ADCSequenceStepConfigure()
572 HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & in ADCSequenceStepConfigure()
579 HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & in ADCSequenceStepConfigure()
928 HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & in ADCSoftwareOversampleStepConfigure()
935 HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & in ADCSoftwareOversampleStepConfigure()
942 HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & in ADCSoftwareOversampleStepConfigure()
1384 HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) | in ADCReferenceSet()
1447 HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) | in ADCResolutionSet()
[all …]
A Dssi.c224 HWREG(ulBase + SSI_O_CR1) = ulRegVal; in SSIConfigSetExpClk()
237 HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; in SSIConfigSetExpClk()
245 HWREG(ulBase + SSI_O_CR0) = ulRegVal; in SSIConfigSetExpClk()
414 HWREG(ulBase + SSI_O_IM) |= ulIntFlags; in SSIIntEnable()
475 return(HWREG(ulBase + SSI_O_MIS)); in SSIIntStatus()
479 return(HWREG(ulBase + SSI_O_RIS)); in SSIIntStatus()
561 HWREG(ulBase + SSI_O_DR) = ulData; in SSIDataPut()
602 HWREG(ulBase + SSI_O_DR) = ulData; in SSIDataPutNonBlocking()
651 *pulData = HWREG(ulBase + SSI_O_DR); in SSIDataGet()
831 HWREG(ulBase + SSI_O_CC) = ulSource; in SSIClockSourceSet()
[all …]
A Depi.c93 HWREG(ulBase + EPI_O_CFG) = ulMode; in EPIModeSet()
134 HWREG(ulBase + EPI_O_BAUD) = ulDivider; in EPIDividerSet()
279 HWREG(ulBase + EPI_O_HB8CFG) = ulConfig; in EPIConfigHB8Set()
461 HWREG(ulBase + EPI_O_GPCFG) = ulConfig; in EPIConfigGPModeSet()
505 HWREG(ulBase + EPI_O_ADDRMAP) = ulMap; in EPIAddressMapSet()
709 return(HWREG(ulBase + EPI_O_RFIFOCNT)); in EPINonBlockingReadAvail()
942 return(HWREG(ulBase + EPI_O_WFIFOCNT)); in EPIWriteFIFOCountGet()
975 HWREG(ulBase + EPI_O_IM) |= ulIntFlags; in EPIIntEnable()
1038 return(HWREG(ulBase + EPI_O_MIS)); in EPIIntStatus()
1042 return(HWREG(ulBase + EPI_O_RIS)); in EPIIntStatus()
[all …]
A Dqei.c80 HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; in QEIEnable()
151 HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & in QEIConfigure()
188 return(HWREG(ulBase + QEI_O_POS)); in QEIPositionGet()
215 HWREG(ulBase + QEI_O_POS) = ulPosition; in QEIPositionSet()
364 HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & in QEIVelocityConfigure()
370 HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; in QEIVelocityConfigure()
399 return(HWREG(ulBase + QEI_O_SPEED)); in QEIVelocityGet()
517 HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; in QEIIntEnable()
580 return(HWREG(ulBase + QEI_O_ISC)); in QEIIntStatus()
584 return(HWREG(ulBase + QEI_O_RIS)); in QEIIntStatus()
[all …]
/lk-master/external/platform/cc13xx/cc13xxware/driverlib/
A Dcrypto.c168 if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & in CRYPTOAesLoadKey()
277 HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; in CRYPTOAesEcb()
324 ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); in CRYPTOAesEcbStatus()
475 HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; in CRYPTOCcmAuthEncrypt()
556 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = in CRYPTOCcmAuthEncrypt()
572 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = in CRYPTOCcmAuthEncrypt()
647 while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & in CRYPTOCcmAuthEncryptResultGet()
798 HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; in CRYPTOCcmInvAuthDecrypt()
879 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = in CRYPTOCcmInvAuthDecrypt()
895 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = in CRYPTOCcmInvAuthDecrypt()
[all …]
A Dflash.c126 HWREG(FLASH_BASE + FLASH_O_FPAC1) = in FlashPowerModeSet()
134 HWREG(FLASH_BASE + FLASH_O_FBAC) = in FlashPowerModeSet()
141 HWREG(FLASH_BASE + FLASH_O_FPAC2) = in FlashPowerModeSet()
160 HWREG(FLASH_BASE + FLASH_O_FBAC) = in FlashPowerModeSet()
167 HWREG(FLASH_BASE + FLASH_O_FPAC2) = in FlashPowerModeSet()
461 HWREG(FLASH_BASE + FLASH_O_EFUSE) = in FlashEfuseReadRow()
538 HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; in FlashDisableSectorsForWrite()
600 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & in SetReadMode()
633 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = in SetReadMode()
668 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & in SetReadMode()
[all …]
A Drfc.h108 HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = in RFCClockEnable()
143 HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; in RFCClockDisable()
164 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0; in RFCCpe0IntEnable()
170 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; in RFCCpe0IntEnable()
192 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0; in RFCCpe1IntEnable()
198 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; in RFCCpe1IntEnable()
214 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = 0x0; in RFCHwIntEnable()
219 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; in RFCHwIntEnable()
241 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0; in RFCCpeIntDisable()
262 HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = 0x0; in RFCHwIntDisable()
[all …]
A Dinterrupt.c169 if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) in IntRegister()
175 ui32Value = HWREG(NVIC_VTABLE); in IntRegister()
185 HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; in IntRegister()
286 ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); in IntPrioritySet()
289 HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; in IntPrioritySet()
354 HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; in IntEnable()
361 HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); in IntEnable()
368 HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); in IntEnable()
414 HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); in IntDisable()
421 HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); in IntDisable()
[all …]
A Dsetup.c181 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; in SetupCacheModeAccordingToCcfgSetting()
184 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; in SetupCacheModeAccordingToCcfgSetting()
297 HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; in trimDevice()
303 HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & in trimDevice()
478 HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & in HapiTrimDeviceShutDown()
484 HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & in HapiTrimDeviceShutDown()
649 … HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & in HapiTrimDeviceShutDown()
655 … HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & in HapiTrimDeviceShutDown()
866 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & in GetTrimForRcOscLfRtuneCtuneTrim()
872 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & in GetTrimForRcOscLfRtuneCtuneTrim()
[all …]
A Dprcm.c332 HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; in PRCMAudioClockConfigSet()
333 HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; in PRCMAudioClockConfigSet()
411 HWREG(PRCM_BASE + in PRCMPowerDomainOn()
417 HWREG(PRCM_BASE + in PRCMPowerDomainOn()
422 HWREG(PRCM_BASE + in PRCMPowerDomainOn()
427 HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |= in PRCMPowerDomainOn()
458 HWREG(PRCM_BASE + in PRCMPowerDomainOff()
464 HWREG(PRCM_BASE + in PRCMPowerDomainOff()
469 HWREG(PRCM_BASE + in PRCMPowerDomainOff()
474 HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &= in PRCMPowerDomainOff()
[all …]
/lk-master/external/platform/stellaris/ti-driverlib/inc/
A Dhw_types.h63 #define HWREG(x) \ macro
147 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
153 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
159 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
165 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
171 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
177 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
183 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
189 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
195 ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
[all …]

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