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Searched refs:MIO_TRI_ENABLE (Results 1 – 4 of 4) sorted by relevance

/lk-master/target/uzed/
A Dtarget.c113 [29] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
115 [31] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
120 [36] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
130 [46] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
133 [49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
134 [50] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
/lk-master/target/zybo/
A Dtarget.c117 [29] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
119 [31] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
124 [36] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
134 [47] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
136 [49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
/lk-master/platform/zynq/
A Dgpio.c157 mio_cfg &= MIO_TRI_ENABLE | in gpio_config()
/lk-master/platform/zynq/include/platform/
A Dzynq.h453 #define MIO_TRI_ENABLE (1) macro

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