1 /*
2  * Copyright (c) 2009 Corey Tabaka
3  * Copyright (c) 2020 Travis Geiseblrecht
4  *
5  * Use of this source code is governed by a MIT-style
6  * license that can be found in the LICENSE file or at
7  * https://opensource.org/licenses/MIT
8  */
9 #pragma once
10 
11 #include <sys/types.h>
12 #include <lk/compiler.h>
13 
14 __BEGIN_CDECLS
15 
16 /*
17  * PCI access return codes
18  */
19 #define _PCI_SUCCESSFUL             0x00
20 #define _PCI_FUNC_NOT_SUPPORTED     0x81
21 #define _PCI_BAD_VENDOR_ID          0x83
22 #define _PCI_DEVICE_NOT_FOUND       0x86
23 #define _PCI_BAD_REGISTER_NUMBER    0x87
24 #define _PCI_SET_FAILED             0x88
25 #define _PCI_BUFFER_TOO_SMALL       0x89
26 
27 /*
28  * PCI configuration space offsets
29  */
30 #define PCI_CONFIG_VENDOR_ID        0x00
31 #define PCI_CONFIG_DEVICE_ID        0x02
32 #define PCI_CONFIG_COMMAND          0x04
33 #define PCI_CONFIG_STATUS           0x06
34 #define PCI_CONFIG_REVISION_ID      0x08
35 #define PCI_CONFIG_CLASS_CODE       0x09
36 #define PCI_CONFIG_CLASS_CODE_INTR  0x09
37 #define PCI_CONFIG_CLASS_CODE_SUB   0x0a
38 #define PCI_CONFIG_CLASS_CODE_BASE  0x0b
39 #define PCI_CONFIG_CACHE_LINE_SIZE  0x0c
40 #define PCI_CONFIG_LATENCY_TIMER    0x0d
41 #define PCI_CONFIG_HEADER_TYPE      0x0e
42 #define PCI_CONFIG_BIST             0x0f
43 #define PCI_CONFIG_BASE_ADDRESSES   0x10
44 #define PCI_CONFIG_CARDBUS_CIS_PTR  0x28
45 #define PCI_CONFIG_SUBSYS_VENDOR_ID 0x2c
46 #define PCI_CONFIG_SUBSYS_ID        0x2e
47 #define PCI_CONFIG_EXP_ROM_ADDRESS  0x30
48 #define PCI_CONFIG_CAPABILITIES     0x34
49 #define PCI_CONFIG_INTERRUPT_LINE   0x3c
50 #define PCI_CONFIG_INTERRUPT_PIN    0x3d
51 #define PCI_CONFIG_MIN_GRANT        0x3e
52 #define PCI_CONFIG_MAX_LATENCY      0x3f
53 
54 /*
55  * PCI header type register bits
56  */
57 #define PCI_HEADER_TYPE_MASK        0x7f
58 #define PCI_HEADER_TYPE_MULTI_FN    0x80
59 
60 /*
61  * PCI header types
62  */
63 #define PCI_HEADER_TYPE_STANDARD    0x00
64 #define PCI_HEADER_TYPE_PCI_BRIDGE  0x01
65 #define PCI_HEADER_TYPE_CARD_BUS    0x02
66 
67 /*
68  * PCI command register bits
69  */
70 #define PCI_COMMAND_IO_EN           0x0001
71 #define PCI_COMMAND_MEM_EN          0x0002
72 #define PCI_COMMAND_BUS_MASTER_EN   0x0004
73 #define PCI_COMMAND_SPECIAL_EN      0x0008
74 #define PCI_COMMAND_MEM_WR_INV_EN   0x0010
75 #define PCI_COMMAND_PAL_SNOOP_EN    0x0020
76 #define PCI_COMMAND_PERR_RESP_EN    0x0040
77 #define PCI_COMMAND_AD_STEP_EN      0x0080
78 #define PCI_COMMAND_SERR_EN         0x0100
79 #define PCI_COMMAND_FAST_B2B_EN     0x0200
80 
81 /*
82  * PCI status register bits
83  */
84 #define PCI_STATUS_NEW_CAPS         0x0010
85 #define PCI_STATUS_66_MHZ           0x0020
86 #define PCI_STATUS_FAST_B2B         0x0080
87 #define PCI_STATUS_MSTR_PERR        0x0100
88 #define PCI_STATUS_DEVSEL_MASK      0x0600
89 #define PCI_STATUS_TARG_ABORT_SIG   0x0800
90 #define PCI_STATUS_TARG_ABORT_RCV   0x1000
91 #define PCI_STATUS_MSTR_ABORT_RCV   0x2000
92 #define PCI_STATUS_SERR_SIG         0x4000
93 #define PCI_STATUS_PERR             0x8000
94 
95 typedef struct {
96     uint16_t vendor_id;
97     uint16_t device_id;
98     uint16_t command;
99     uint16_t status;
100     uint8_t revision_id_0;
101     uint8_t program_interface;
102     uint8_t sub_class;
103     uint8_t base_class;
104     uint8_t cache_line_size;
105     uint8_t latency_timer;
106     uint8_t header_type;
107     uint8_t bist;
108     uint32_t base_addresses[6];
109     uint32_t cardbus_cis_ptr;
110     uint16_t subsystem_vendor_id;
111     uint16_t subsystem_id;
112     uint32_t expansion_rom_address;
113     uint8_t capabilities_ptr;
114     uint8_t reserved_0[3];
115     uint32_t reserved_1;
116     uint8_t interrupt_line;
117     uint8_t interrupt_pin;
118     uint8_t min_grant;
119     uint8_t max_latency;
120 } __PACKED pci_config_t;
121 
122 /*
123  * PCI address structure
124  */
125 typedef struct {
126     uint8_t bus;
127     uint8_t dev_fn;
128 } pci_location_t;
129 
130 typedef struct {
131     uint8_t id;
132     uint8_t next;
133 } __PACKED pci_capability_t;
134 
135 typedef struct {
136     uint8_t bus;
137     uint8_t device;
138     uint8_t link_int_a;
139     uint16_t irq_int_a;
140     uint8_t link_int_b;
141     uint16_t irq_int_b;
142     uint8_t link_int_c;
143     uint16_t irq_int_c;
144     uint8_t link_int_d;
145     uint16_t irq_int_d;
146     uint8_t slot;
147     uint8_t reserved;
148 } __PACKED irq_routing_entry;
149 
150 // only use one of these two:
151 // try to detect PCI based on legacy PC PCI accessor methods
152 status_t pci_init_legacy(void);
153 
154 // try to detect PCI based on a known ecam base.
155 status_t pci_init_ecam(paddr_t ecam_base, uint16_t segment, uint8_t start_bus, uint8_t end_bus);
156 
157 int pci_get_last_bus(void);
158 
159 status_t pci_find_pci_device(pci_location_t *state, uint16_t device_id, uint16_t vendor_id, uint16_t index);
160 status_t pci_find_pci_class_code(pci_location_t *state, uint32_t class_code, uint16_t index);
161 
162 status_t pci_read_config_byte(const pci_location_t *state, uint32_t reg, uint8_t *value);
163 status_t pci_read_config_half(const pci_location_t *state, uint32_t reg, uint16_t *value);
164 status_t pci_read_config_word(const pci_location_t *state, uint32_t reg, uint32_t *value);
165 
166 status_t pci_write_config_byte(const pci_location_t *state, uint32_t reg, uint8_t value);
167 status_t pci_write_config_half(const pci_location_t *state, uint32_t reg, uint16_t value);
168 status_t pci_write_config_word(const pci_location_t *state, uint32_t reg, uint32_t value);
169 
170 status_t pci_get_irq_routing_options(irq_routing_entry *entries, uint16_t *count, uint16_t *pci_irqs);
171 status_t pci_set_irq_hw_int(const pci_location_t *state, uint8_t int_pin, uint8_t irq);
172 
173 __END_CDECLS
174