1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : PIO 8 // Version : 1 9 // Bus type : ahbl 10 // Description : Programmable IO block 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_PIO_DEFINED 13 #define HARDWARE_REGS_PIO_DEFINED 14 // ============================================================================= 15 // Register : PIO_CTRL 16 // Description : PIO control register 17 #define PIO_CTRL_OFFSET 0x00000000 18 #define PIO_CTRL_BITS 0x00000fff 19 #define PIO_CTRL_RESET 0x00000000 20 // ----------------------------------------------------------------------------- 21 // Field : PIO_CTRL_CLKDIV_RESTART 22 // Description : Force clock dividers to restart their count and clear 23 // fractional 24 // accumulators. Restart multiple dividers to synchronise them. 25 #define PIO_CTRL_CLKDIV_RESTART_RESET 0x0 26 #define PIO_CTRL_CLKDIV_RESTART_BITS 0x00000f00 27 #define PIO_CTRL_CLKDIV_RESTART_MSB 11 28 #define PIO_CTRL_CLKDIV_RESTART_LSB 8 29 #define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" 30 // ----------------------------------------------------------------------------- 31 // Field : PIO_CTRL_SM_RESTART 32 // Description : Clear internal SM state which is otherwise difficult to access 33 // (e.g. shift counters). Self-clearing. 34 #define PIO_CTRL_SM_RESTART_RESET 0x0 35 #define PIO_CTRL_SM_RESTART_BITS 0x000000f0 36 #define PIO_CTRL_SM_RESTART_MSB 7 37 #define PIO_CTRL_SM_RESTART_LSB 4 38 #define PIO_CTRL_SM_RESTART_ACCESS "SC" 39 // ----------------------------------------------------------------------------- 40 // Field : PIO_CTRL_SM_ENABLE 41 // Description : Enable state machine 42 #define PIO_CTRL_SM_ENABLE_RESET 0x0 43 #define PIO_CTRL_SM_ENABLE_BITS 0x0000000f 44 #define PIO_CTRL_SM_ENABLE_MSB 3 45 #define PIO_CTRL_SM_ENABLE_LSB 0 46 #define PIO_CTRL_SM_ENABLE_ACCESS "RW" 47 // ============================================================================= 48 // Register : PIO_FSTAT 49 // Description : FIFO status register 50 #define PIO_FSTAT_OFFSET 0x00000004 51 #define PIO_FSTAT_BITS 0x0f0f0f0f 52 #define PIO_FSTAT_RESET 0x0f000f00 53 // ----------------------------------------------------------------------------- 54 // Field : PIO_FSTAT_TXEMPTY 55 // Description : State machine TX FIFO is empty 56 #define PIO_FSTAT_TXEMPTY_RESET 0xf 57 #define PIO_FSTAT_TXEMPTY_BITS 0x0f000000 58 #define PIO_FSTAT_TXEMPTY_MSB 27 59 #define PIO_FSTAT_TXEMPTY_LSB 24 60 #define PIO_FSTAT_TXEMPTY_ACCESS "RO" 61 // ----------------------------------------------------------------------------- 62 // Field : PIO_FSTAT_TXFULL 63 // Description : State machine TX FIFO is full 64 #define PIO_FSTAT_TXFULL_RESET 0x0 65 #define PIO_FSTAT_TXFULL_BITS 0x000f0000 66 #define PIO_FSTAT_TXFULL_MSB 19 67 #define PIO_FSTAT_TXFULL_LSB 16 68 #define PIO_FSTAT_TXFULL_ACCESS "RO" 69 // ----------------------------------------------------------------------------- 70 // Field : PIO_FSTAT_RXEMPTY 71 // Description : State machine RX FIFO is empty 72 #define PIO_FSTAT_RXEMPTY_RESET 0xf 73 #define PIO_FSTAT_RXEMPTY_BITS 0x00000f00 74 #define PIO_FSTAT_RXEMPTY_MSB 11 75 #define PIO_FSTAT_RXEMPTY_LSB 8 76 #define PIO_FSTAT_RXEMPTY_ACCESS "RO" 77 // ----------------------------------------------------------------------------- 78 // Field : PIO_FSTAT_RXFULL 79 // Description : State machine RX FIFO is full 80 #define PIO_FSTAT_RXFULL_RESET 0x0 81 #define PIO_FSTAT_RXFULL_BITS 0x0000000f 82 #define PIO_FSTAT_RXFULL_MSB 3 83 #define PIO_FSTAT_RXFULL_LSB 0 84 #define PIO_FSTAT_RXFULL_ACCESS "RO" 85 // ============================================================================= 86 // Register : PIO_FDEBUG 87 // Description : FIFO debug register 88 #define PIO_FDEBUG_OFFSET 0x00000008 89 #define PIO_FDEBUG_BITS 0x0f0f0f0f 90 #define PIO_FDEBUG_RESET 0x00000000 91 // ----------------------------------------------------------------------------- 92 // Field : PIO_FDEBUG_TXSTALL 93 // Description : State machine has stalled on empty TX FIFO. Write 1 to clear. 94 #define PIO_FDEBUG_TXSTALL_RESET 0x0 95 #define PIO_FDEBUG_TXSTALL_BITS 0x0f000000 96 #define PIO_FDEBUG_TXSTALL_MSB 27 97 #define PIO_FDEBUG_TXSTALL_LSB 24 98 #define PIO_FDEBUG_TXSTALL_ACCESS "WC" 99 // ----------------------------------------------------------------------------- 100 // Field : PIO_FDEBUG_TXOVER 101 // Description : TX FIFO overflow has occurred. Write 1 to clear. 102 #define PIO_FDEBUG_TXOVER_RESET 0x0 103 #define PIO_FDEBUG_TXOVER_BITS 0x000f0000 104 #define PIO_FDEBUG_TXOVER_MSB 19 105 #define PIO_FDEBUG_TXOVER_LSB 16 106 #define PIO_FDEBUG_TXOVER_ACCESS "WC" 107 // ----------------------------------------------------------------------------- 108 // Field : PIO_FDEBUG_RXUNDER 109 // Description : RX FIFO underflow has occurred. Write 1 to clear. 110 #define PIO_FDEBUG_RXUNDER_RESET 0x0 111 #define PIO_FDEBUG_RXUNDER_BITS 0x00000f00 112 #define PIO_FDEBUG_RXUNDER_MSB 11 113 #define PIO_FDEBUG_RXUNDER_LSB 8 114 #define PIO_FDEBUG_RXUNDER_ACCESS "WC" 115 // ----------------------------------------------------------------------------- 116 // Field : PIO_FDEBUG_RXSTALL 117 // Description : State machine has stalled on full RX FIFO. Write 1 to clear. 118 #define PIO_FDEBUG_RXSTALL_RESET 0x0 119 #define PIO_FDEBUG_RXSTALL_BITS 0x0000000f 120 #define PIO_FDEBUG_RXSTALL_MSB 3 121 #define PIO_FDEBUG_RXSTALL_LSB 0 122 #define PIO_FDEBUG_RXSTALL_ACCESS "WC" 123 // ============================================================================= 124 // Register : PIO_FLEVEL 125 // Description : FIFO levels 126 #define PIO_FLEVEL_OFFSET 0x0000000c 127 #define PIO_FLEVEL_BITS 0xffffffff 128 #define PIO_FLEVEL_RESET 0x00000000 129 // ----------------------------------------------------------------------------- 130 // Field : PIO_FLEVEL_RX3 131 // Description : None 132 #define PIO_FLEVEL_RX3_RESET 0x0 133 #define PIO_FLEVEL_RX3_BITS 0xf0000000 134 #define PIO_FLEVEL_RX3_MSB 31 135 #define PIO_FLEVEL_RX3_LSB 28 136 #define PIO_FLEVEL_RX3_ACCESS "RO" 137 // ----------------------------------------------------------------------------- 138 // Field : PIO_FLEVEL_TX3 139 // Description : None 140 #define PIO_FLEVEL_TX3_RESET 0x0 141 #define PIO_FLEVEL_TX3_BITS 0x0f000000 142 #define PIO_FLEVEL_TX3_MSB 27 143 #define PIO_FLEVEL_TX3_LSB 24 144 #define PIO_FLEVEL_TX3_ACCESS "RO" 145 // ----------------------------------------------------------------------------- 146 // Field : PIO_FLEVEL_RX2 147 // Description : None 148 #define PIO_FLEVEL_RX2_RESET 0x0 149 #define PIO_FLEVEL_RX2_BITS 0x00f00000 150 #define PIO_FLEVEL_RX2_MSB 23 151 #define PIO_FLEVEL_RX2_LSB 20 152 #define PIO_FLEVEL_RX2_ACCESS "RO" 153 // ----------------------------------------------------------------------------- 154 // Field : PIO_FLEVEL_TX2 155 // Description : None 156 #define PIO_FLEVEL_TX2_RESET 0x0 157 #define PIO_FLEVEL_TX2_BITS 0x000f0000 158 #define PIO_FLEVEL_TX2_MSB 19 159 #define PIO_FLEVEL_TX2_LSB 16 160 #define PIO_FLEVEL_TX2_ACCESS "RO" 161 // ----------------------------------------------------------------------------- 162 // Field : PIO_FLEVEL_RX1 163 // Description : None 164 #define PIO_FLEVEL_RX1_RESET 0x0 165 #define PIO_FLEVEL_RX1_BITS 0x0000f000 166 #define PIO_FLEVEL_RX1_MSB 15 167 #define PIO_FLEVEL_RX1_LSB 12 168 #define PIO_FLEVEL_RX1_ACCESS "RO" 169 // ----------------------------------------------------------------------------- 170 // Field : PIO_FLEVEL_TX1 171 // Description : None 172 #define PIO_FLEVEL_TX1_RESET 0x0 173 #define PIO_FLEVEL_TX1_BITS 0x00000f00 174 #define PIO_FLEVEL_TX1_MSB 11 175 #define PIO_FLEVEL_TX1_LSB 8 176 #define PIO_FLEVEL_TX1_ACCESS "RO" 177 // ----------------------------------------------------------------------------- 178 // Field : PIO_FLEVEL_RX0 179 // Description : None 180 #define PIO_FLEVEL_RX0_RESET 0x0 181 #define PIO_FLEVEL_RX0_BITS 0x000000f0 182 #define PIO_FLEVEL_RX0_MSB 7 183 #define PIO_FLEVEL_RX0_LSB 4 184 #define PIO_FLEVEL_RX0_ACCESS "RO" 185 // ----------------------------------------------------------------------------- 186 // Field : PIO_FLEVEL_TX0 187 // Description : None 188 #define PIO_FLEVEL_TX0_RESET 0x0 189 #define PIO_FLEVEL_TX0_BITS 0x0000000f 190 #define PIO_FLEVEL_TX0_MSB 3 191 #define PIO_FLEVEL_TX0_LSB 0 192 #define PIO_FLEVEL_TX0_ACCESS "RO" 193 // ============================================================================= 194 // Register : PIO_TXF0 195 // Description : Direct write access to the TX FIFO for this state machine. Each 196 // write pushes one word to the FIFO. 197 #define PIO_TXF0_OFFSET 0x00000010 198 #define PIO_TXF0_BITS 0xffffffff 199 #define PIO_TXF0_RESET 0x00000000 200 #define PIO_TXF0_MSB 31 201 #define PIO_TXF0_LSB 0 202 #define PIO_TXF0_ACCESS "WF" 203 // ============================================================================= 204 // Register : PIO_TXF1 205 // Description : Direct write access to the TX FIFO for this state machine. Each 206 // write pushes one word to the FIFO. 207 #define PIO_TXF1_OFFSET 0x00000014 208 #define PIO_TXF1_BITS 0xffffffff 209 #define PIO_TXF1_RESET 0x00000000 210 #define PIO_TXF1_MSB 31 211 #define PIO_TXF1_LSB 0 212 #define PIO_TXF1_ACCESS "WF" 213 // ============================================================================= 214 // Register : PIO_TXF2 215 // Description : Direct write access to the TX FIFO for this state machine. Each 216 // write pushes one word to the FIFO. 217 #define PIO_TXF2_OFFSET 0x00000018 218 #define PIO_TXF2_BITS 0xffffffff 219 #define PIO_TXF2_RESET 0x00000000 220 #define PIO_TXF2_MSB 31 221 #define PIO_TXF2_LSB 0 222 #define PIO_TXF2_ACCESS "WF" 223 // ============================================================================= 224 // Register : PIO_TXF3 225 // Description : Direct write access to the TX FIFO for this state machine. Each 226 // write pushes one word to the FIFO. 227 #define PIO_TXF3_OFFSET 0x0000001c 228 #define PIO_TXF3_BITS 0xffffffff 229 #define PIO_TXF3_RESET 0x00000000 230 #define PIO_TXF3_MSB 31 231 #define PIO_TXF3_LSB 0 232 #define PIO_TXF3_ACCESS "WF" 233 // ============================================================================= 234 // Register : PIO_RXF0 235 // Description : Direct read access to the RX FIFO for this state machine. Each 236 // read pops one word from the FIFO. 237 #define PIO_RXF0_OFFSET 0x00000020 238 #define PIO_RXF0_BITS 0xffffffff 239 #define PIO_RXF0_RESET "-" 240 #define PIO_RXF0_MSB 31 241 #define PIO_RXF0_LSB 0 242 #define PIO_RXF0_ACCESS "RF" 243 // ============================================================================= 244 // Register : PIO_RXF1 245 // Description : Direct read access to the RX FIFO for this state machine. Each 246 // read pops one word from the FIFO. 247 #define PIO_RXF1_OFFSET 0x00000024 248 #define PIO_RXF1_BITS 0xffffffff 249 #define PIO_RXF1_RESET "-" 250 #define PIO_RXF1_MSB 31 251 #define PIO_RXF1_LSB 0 252 #define PIO_RXF1_ACCESS "RF" 253 // ============================================================================= 254 // Register : PIO_RXF2 255 // Description : Direct read access to the RX FIFO for this state machine. Each 256 // read pops one word from the FIFO. 257 #define PIO_RXF2_OFFSET 0x00000028 258 #define PIO_RXF2_BITS 0xffffffff 259 #define PIO_RXF2_RESET "-" 260 #define PIO_RXF2_MSB 31 261 #define PIO_RXF2_LSB 0 262 #define PIO_RXF2_ACCESS "RF" 263 // ============================================================================= 264 // Register : PIO_RXF3 265 // Description : Direct read access to the RX FIFO for this state machine. Each 266 // read pops one word from the FIFO. 267 #define PIO_RXF3_OFFSET 0x0000002c 268 #define PIO_RXF3_BITS 0xffffffff 269 #define PIO_RXF3_RESET "-" 270 #define PIO_RXF3_MSB 31 271 #define PIO_RXF3_LSB 0 272 #define PIO_RXF3_ACCESS "RF" 273 // ============================================================================= 274 // Register : PIO_IRQ 275 // Description : Interrupt request register. Write 1 to clear 276 #define PIO_IRQ_OFFSET 0x00000030 277 #define PIO_IRQ_BITS 0x000000ff 278 #define PIO_IRQ_RESET 0x00000000 279 #define PIO_IRQ_MSB 7 280 #define PIO_IRQ_LSB 0 281 #define PIO_IRQ_ACCESS "WC" 282 // ============================================================================= 283 // Register : PIO_IRQ_FORCE 284 // Description : Writing a 1 to each of these bits will forcibly assert the 285 // corresponding IRQ. 286 // Note this is different to the INTF register: writing here 287 // affects PIO internal 288 // state. INTF just asserts the processor-facing IRQ signal for 289 // testing ISRs, 290 // and is not visible to the state machines. 291 #define PIO_IRQ_FORCE_OFFSET 0x00000034 292 #define PIO_IRQ_FORCE_BITS 0x000000ff 293 #define PIO_IRQ_FORCE_RESET 0x00000000 294 #define PIO_IRQ_FORCE_MSB 7 295 #define PIO_IRQ_FORCE_LSB 0 296 #define PIO_IRQ_FORCE_ACCESS "WF" 297 // ============================================================================= 298 // Register : PIO_INPUT_SYNC_BYPASS 299 // Description : There is a 2-flipflop synchronizer on each GPIO input, which 300 // protects 301 // PIO logic from metastabilities. This increases input delay, and 302 // for fast 303 // synchronous IO (e.g. SPI) these synchronizers may need to be 304 // bypassed. 305 // Each bit in this register corresponds to one GPIO. 306 // 0 -> input is synchronized (default) 307 // 1 -> synchronizer is bypassed 308 // If in doubt, leave this register as all zeroes. 309 #define PIO_INPUT_SYNC_BYPASS_OFFSET 0x00000038 310 #define PIO_INPUT_SYNC_BYPASS_BITS 0xffffffff 311 #define PIO_INPUT_SYNC_BYPASS_RESET 0x00000000 312 #define PIO_INPUT_SYNC_BYPASS_MSB 31 313 #define PIO_INPUT_SYNC_BYPASS_LSB 0 314 #define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" 315 // ============================================================================= 316 // Register : PIO_DBG_PADOUT 317 // Description : Read to sample the pad output values PIO is currently driving 318 // to the GPIOs. 319 #define PIO_DBG_PADOUT_OFFSET 0x0000003c 320 #define PIO_DBG_PADOUT_BITS 0xffffffff 321 #define PIO_DBG_PADOUT_RESET 0x00000000 322 #define PIO_DBG_PADOUT_MSB 31 323 #define PIO_DBG_PADOUT_LSB 0 324 #define PIO_DBG_PADOUT_ACCESS "RO" 325 // ============================================================================= 326 // Register : PIO_DBG_PADOE 327 // Description : Read to sample the pad output enables (direction) PIO is 328 // currently driving to the GPIOs. 329 #define PIO_DBG_PADOE_OFFSET 0x00000040 330 #define PIO_DBG_PADOE_BITS 0xffffffff 331 #define PIO_DBG_PADOE_RESET 0x00000000 332 #define PIO_DBG_PADOE_MSB 31 333 #define PIO_DBG_PADOE_LSB 0 334 #define PIO_DBG_PADOE_ACCESS "RO" 335 // ============================================================================= 336 // Register : PIO_DBG_CFGINFO 337 // Description : The PIO hardware has some free parameters that may vary between 338 // chip products. 339 // These should be provided in the chip datasheet, but are also 340 // exposed here. 341 #define PIO_DBG_CFGINFO_OFFSET 0x00000044 342 #define PIO_DBG_CFGINFO_BITS 0x003f0f3f 343 #define PIO_DBG_CFGINFO_RESET 0x00000000 344 // ----------------------------------------------------------------------------- 345 // Field : PIO_DBG_CFGINFO_IMEM_SIZE 346 // Description : The size of the instruction memory, measured in units of one 347 // instruction 348 #define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" 349 #define PIO_DBG_CFGINFO_IMEM_SIZE_BITS 0x003f0000 350 #define PIO_DBG_CFGINFO_IMEM_SIZE_MSB 21 351 #define PIO_DBG_CFGINFO_IMEM_SIZE_LSB 16 352 #define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" 353 // ----------------------------------------------------------------------------- 354 // Field : PIO_DBG_CFGINFO_SM_COUNT 355 // Description : The number of state machines this PIO instance is equipped 356 // with. 357 #define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" 358 #define PIO_DBG_CFGINFO_SM_COUNT_BITS 0x00000f00 359 #define PIO_DBG_CFGINFO_SM_COUNT_MSB 11 360 #define PIO_DBG_CFGINFO_SM_COUNT_LSB 8 361 #define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" 362 // ----------------------------------------------------------------------------- 363 // Field : PIO_DBG_CFGINFO_FIFO_DEPTH 364 // Description : The depth of the state machine TX/RX FIFOs, measured in words. 365 // Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double 366 // this depth. 367 #define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" 368 #define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS 0x0000003f 369 #define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB 5 370 #define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB 0 371 #define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" 372 // ============================================================================= 373 // Register : PIO_INSTR_MEM0 374 // Description : Write-only access to instruction memory location 0 375 #define PIO_INSTR_MEM0_OFFSET 0x00000048 376 #define PIO_INSTR_MEM0_BITS 0x0000ffff 377 #define PIO_INSTR_MEM0_RESET 0x00000000 378 #define PIO_INSTR_MEM0_MSB 15 379 #define PIO_INSTR_MEM0_LSB 0 380 #define PIO_INSTR_MEM0_ACCESS "WO" 381 // ============================================================================= 382 // Register : PIO_INSTR_MEM1 383 // Description : Write-only access to instruction memory location 1 384 #define PIO_INSTR_MEM1_OFFSET 0x0000004c 385 #define PIO_INSTR_MEM1_BITS 0x0000ffff 386 #define PIO_INSTR_MEM1_RESET 0x00000000 387 #define PIO_INSTR_MEM1_MSB 15 388 #define PIO_INSTR_MEM1_LSB 0 389 #define PIO_INSTR_MEM1_ACCESS "WO" 390 // ============================================================================= 391 // Register : PIO_INSTR_MEM2 392 // Description : Write-only access to instruction memory location 2 393 #define PIO_INSTR_MEM2_OFFSET 0x00000050 394 #define PIO_INSTR_MEM2_BITS 0x0000ffff 395 #define PIO_INSTR_MEM2_RESET 0x00000000 396 #define PIO_INSTR_MEM2_MSB 15 397 #define PIO_INSTR_MEM2_LSB 0 398 #define PIO_INSTR_MEM2_ACCESS "WO" 399 // ============================================================================= 400 // Register : PIO_INSTR_MEM3 401 // Description : Write-only access to instruction memory location 3 402 #define PIO_INSTR_MEM3_OFFSET 0x00000054 403 #define PIO_INSTR_MEM3_BITS 0x0000ffff 404 #define PIO_INSTR_MEM3_RESET 0x00000000 405 #define PIO_INSTR_MEM3_MSB 15 406 #define PIO_INSTR_MEM3_LSB 0 407 #define PIO_INSTR_MEM3_ACCESS "WO" 408 // ============================================================================= 409 // Register : PIO_INSTR_MEM4 410 // Description : Write-only access to instruction memory location 4 411 #define PIO_INSTR_MEM4_OFFSET 0x00000058 412 #define PIO_INSTR_MEM4_BITS 0x0000ffff 413 #define PIO_INSTR_MEM4_RESET 0x00000000 414 #define PIO_INSTR_MEM4_MSB 15 415 #define PIO_INSTR_MEM4_LSB 0 416 #define PIO_INSTR_MEM4_ACCESS "WO" 417 // ============================================================================= 418 // Register : PIO_INSTR_MEM5 419 // Description : Write-only access to instruction memory location 5 420 #define PIO_INSTR_MEM5_OFFSET 0x0000005c 421 #define PIO_INSTR_MEM5_BITS 0x0000ffff 422 #define PIO_INSTR_MEM5_RESET 0x00000000 423 #define PIO_INSTR_MEM5_MSB 15 424 #define PIO_INSTR_MEM5_LSB 0 425 #define PIO_INSTR_MEM5_ACCESS "WO" 426 // ============================================================================= 427 // Register : PIO_INSTR_MEM6 428 // Description : Write-only access to instruction memory location 6 429 #define PIO_INSTR_MEM6_OFFSET 0x00000060 430 #define PIO_INSTR_MEM6_BITS 0x0000ffff 431 #define PIO_INSTR_MEM6_RESET 0x00000000 432 #define PIO_INSTR_MEM6_MSB 15 433 #define PIO_INSTR_MEM6_LSB 0 434 #define PIO_INSTR_MEM6_ACCESS "WO" 435 // ============================================================================= 436 // Register : PIO_INSTR_MEM7 437 // Description : Write-only access to instruction memory location 7 438 #define PIO_INSTR_MEM7_OFFSET 0x00000064 439 #define PIO_INSTR_MEM7_BITS 0x0000ffff 440 #define PIO_INSTR_MEM7_RESET 0x00000000 441 #define PIO_INSTR_MEM7_MSB 15 442 #define PIO_INSTR_MEM7_LSB 0 443 #define PIO_INSTR_MEM7_ACCESS "WO" 444 // ============================================================================= 445 // Register : PIO_INSTR_MEM8 446 // Description : Write-only access to instruction memory location 8 447 #define PIO_INSTR_MEM8_OFFSET 0x00000068 448 #define PIO_INSTR_MEM8_BITS 0x0000ffff 449 #define PIO_INSTR_MEM8_RESET 0x00000000 450 #define PIO_INSTR_MEM8_MSB 15 451 #define PIO_INSTR_MEM8_LSB 0 452 #define PIO_INSTR_MEM8_ACCESS "WO" 453 // ============================================================================= 454 // Register : PIO_INSTR_MEM9 455 // Description : Write-only access to instruction memory location 9 456 #define PIO_INSTR_MEM9_OFFSET 0x0000006c 457 #define PIO_INSTR_MEM9_BITS 0x0000ffff 458 #define PIO_INSTR_MEM9_RESET 0x00000000 459 #define PIO_INSTR_MEM9_MSB 15 460 #define PIO_INSTR_MEM9_LSB 0 461 #define PIO_INSTR_MEM9_ACCESS "WO" 462 // ============================================================================= 463 // Register : PIO_INSTR_MEM10 464 // Description : Write-only access to instruction memory location 10 465 #define PIO_INSTR_MEM10_OFFSET 0x00000070 466 #define PIO_INSTR_MEM10_BITS 0x0000ffff 467 #define PIO_INSTR_MEM10_RESET 0x00000000 468 #define PIO_INSTR_MEM10_MSB 15 469 #define PIO_INSTR_MEM10_LSB 0 470 #define PIO_INSTR_MEM10_ACCESS "WO" 471 // ============================================================================= 472 // Register : PIO_INSTR_MEM11 473 // Description : Write-only access to instruction memory location 11 474 #define PIO_INSTR_MEM11_OFFSET 0x00000074 475 #define PIO_INSTR_MEM11_BITS 0x0000ffff 476 #define PIO_INSTR_MEM11_RESET 0x00000000 477 #define PIO_INSTR_MEM11_MSB 15 478 #define PIO_INSTR_MEM11_LSB 0 479 #define PIO_INSTR_MEM11_ACCESS "WO" 480 // ============================================================================= 481 // Register : PIO_INSTR_MEM12 482 // Description : Write-only access to instruction memory location 12 483 #define PIO_INSTR_MEM12_OFFSET 0x00000078 484 #define PIO_INSTR_MEM12_BITS 0x0000ffff 485 #define PIO_INSTR_MEM12_RESET 0x00000000 486 #define PIO_INSTR_MEM12_MSB 15 487 #define PIO_INSTR_MEM12_LSB 0 488 #define PIO_INSTR_MEM12_ACCESS "WO" 489 // ============================================================================= 490 // Register : PIO_INSTR_MEM13 491 // Description : Write-only access to instruction memory location 13 492 #define PIO_INSTR_MEM13_OFFSET 0x0000007c 493 #define PIO_INSTR_MEM13_BITS 0x0000ffff 494 #define PIO_INSTR_MEM13_RESET 0x00000000 495 #define PIO_INSTR_MEM13_MSB 15 496 #define PIO_INSTR_MEM13_LSB 0 497 #define PIO_INSTR_MEM13_ACCESS "WO" 498 // ============================================================================= 499 // Register : PIO_INSTR_MEM14 500 // Description : Write-only access to instruction memory location 14 501 #define PIO_INSTR_MEM14_OFFSET 0x00000080 502 #define PIO_INSTR_MEM14_BITS 0x0000ffff 503 #define PIO_INSTR_MEM14_RESET 0x00000000 504 #define PIO_INSTR_MEM14_MSB 15 505 #define PIO_INSTR_MEM14_LSB 0 506 #define PIO_INSTR_MEM14_ACCESS "WO" 507 // ============================================================================= 508 // Register : PIO_INSTR_MEM15 509 // Description : Write-only access to instruction memory location 15 510 #define PIO_INSTR_MEM15_OFFSET 0x00000084 511 #define PIO_INSTR_MEM15_BITS 0x0000ffff 512 #define PIO_INSTR_MEM15_RESET 0x00000000 513 #define PIO_INSTR_MEM15_MSB 15 514 #define PIO_INSTR_MEM15_LSB 0 515 #define PIO_INSTR_MEM15_ACCESS "WO" 516 // ============================================================================= 517 // Register : PIO_INSTR_MEM16 518 // Description : Write-only access to instruction memory location 16 519 #define PIO_INSTR_MEM16_OFFSET 0x00000088 520 #define PIO_INSTR_MEM16_BITS 0x0000ffff 521 #define PIO_INSTR_MEM16_RESET 0x00000000 522 #define PIO_INSTR_MEM16_MSB 15 523 #define PIO_INSTR_MEM16_LSB 0 524 #define PIO_INSTR_MEM16_ACCESS "WO" 525 // ============================================================================= 526 // Register : PIO_INSTR_MEM17 527 // Description : Write-only access to instruction memory location 17 528 #define PIO_INSTR_MEM17_OFFSET 0x0000008c 529 #define PIO_INSTR_MEM17_BITS 0x0000ffff 530 #define PIO_INSTR_MEM17_RESET 0x00000000 531 #define PIO_INSTR_MEM17_MSB 15 532 #define PIO_INSTR_MEM17_LSB 0 533 #define PIO_INSTR_MEM17_ACCESS "WO" 534 // ============================================================================= 535 // Register : PIO_INSTR_MEM18 536 // Description : Write-only access to instruction memory location 18 537 #define PIO_INSTR_MEM18_OFFSET 0x00000090 538 #define PIO_INSTR_MEM18_BITS 0x0000ffff 539 #define PIO_INSTR_MEM18_RESET 0x00000000 540 #define PIO_INSTR_MEM18_MSB 15 541 #define PIO_INSTR_MEM18_LSB 0 542 #define PIO_INSTR_MEM18_ACCESS "WO" 543 // ============================================================================= 544 // Register : PIO_INSTR_MEM19 545 // Description : Write-only access to instruction memory location 19 546 #define PIO_INSTR_MEM19_OFFSET 0x00000094 547 #define PIO_INSTR_MEM19_BITS 0x0000ffff 548 #define PIO_INSTR_MEM19_RESET 0x00000000 549 #define PIO_INSTR_MEM19_MSB 15 550 #define PIO_INSTR_MEM19_LSB 0 551 #define PIO_INSTR_MEM19_ACCESS "WO" 552 // ============================================================================= 553 // Register : PIO_INSTR_MEM20 554 // Description : Write-only access to instruction memory location 20 555 #define PIO_INSTR_MEM20_OFFSET 0x00000098 556 #define PIO_INSTR_MEM20_BITS 0x0000ffff 557 #define PIO_INSTR_MEM20_RESET 0x00000000 558 #define PIO_INSTR_MEM20_MSB 15 559 #define PIO_INSTR_MEM20_LSB 0 560 #define PIO_INSTR_MEM20_ACCESS "WO" 561 // ============================================================================= 562 // Register : PIO_INSTR_MEM21 563 // Description : Write-only access to instruction memory location 21 564 #define PIO_INSTR_MEM21_OFFSET 0x0000009c 565 #define PIO_INSTR_MEM21_BITS 0x0000ffff 566 #define PIO_INSTR_MEM21_RESET 0x00000000 567 #define PIO_INSTR_MEM21_MSB 15 568 #define PIO_INSTR_MEM21_LSB 0 569 #define PIO_INSTR_MEM21_ACCESS "WO" 570 // ============================================================================= 571 // Register : PIO_INSTR_MEM22 572 // Description : Write-only access to instruction memory location 22 573 #define PIO_INSTR_MEM22_OFFSET 0x000000a0 574 #define PIO_INSTR_MEM22_BITS 0x0000ffff 575 #define PIO_INSTR_MEM22_RESET 0x00000000 576 #define PIO_INSTR_MEM22_MSB 15 577 #define PIO_INSTR_MEM22_LSB 0 578 #define PIO_INSTR_MEM22_ACCESS "WO" 579 // ============================================================================= 580 // Register : PIO_INSTR_MEM23 581 // Description : Write-only access to instruction memory location 23 582 #define PIO_INSTR_MEM23_OFFSET 0x000000a4 583 #define PIO_INSTR_MEM23_BITS 0x0000ffff 584 #define PIO_INSTR_MEM23_RESET 0x00000000 585 #define PIO_INSTR_MEM23_MSB 15 586 #define PIO_INSTR_MEM23_LSB 0 587 #define PIO_INSTR_MEM23_ACCESS "WO" 588 // ============================================================================= 589 // Register : PIO_INSTR_MEM24 590 // Description : Write-only access to instruction memory location 24 591 #define PIO_INSTR_MEM24_OFFSET 0x000000a8 592 #define PIO_INSTR_MEM24_BITS 0x0000ffff 593 #define PIO_INSTR_MEM24_RESET 0x00000000 594 #define PIO_INSTR_MEM24_MSB 15 595 #define PIO_INSTR_MEM24_LSB 0 596 #define PIO_INSTR_MEM24_ACCESS "WO" 597 // ============================================================================= 598 // Register : PIO_INSTR_MEM25 599 // Description : Write-only access to instruction memory location 25 600 #define PIO_INSTR_MEM25_OFFSET 0x000000ac 601 #define PIO_INSTR_MEM25_BITS 0x0000ffff 602 #define PIO_INSTR_MEM25_RESET 0x00000000 603 #define PIO_INSTR_MEM25_MSB 15 604 #define PIO_INSTR_MEM25_LSB 0 605 #define PIO_INSTR_MEM25_ACCESS "WO" 606 // ============================================================================= 607 // Register : PIO_INSTR_MEM26 608 // Description : Write-only access to instruction memory location 26 609 #define PIO_INSTR_MEM26_OFFSET 0x000000b0 610 #define PIO_INSTR_MEM26_BITS 0x0000ffff 611 #define PIO_INSTR_MEM26_RESET 0x00000000 612 #define PIO_INSTR_MEM26_MSB 15 613 #define PIO_INSTR_MEM26_LSB 0 614 #define PIO_INSTR_MEM26_ACCESS "WO" 615 // ============================================================================= 616 // Register : PIO_INSTR_MEM27 617 // Description : Write-only access to instruction memory location 27 618 #define PIO_INSTR_MEM27_OFFSET 0x000000b4 619 #define PIO_INSTR_MEM27_BITS 0x0000ffff 620 #define PIO_INSTR_MEM27_RESET 0x00000000 621 #define PIO_INSTR_MEM27_MSB 15 622 #define PIO_INSTR_MEM27_LSB 0 623 #define PIO_INSTR_MEM27_ACCESS "WO" 624 // ============================================================================= 625 // Register : PIO_INSTR_MEM28 626 // Description : Write-only access to instruction memory location 28 627 #define PIO_INSTR_MEM28_OFFSET 0x000000b8 628 #define PIO_INSTR_MEM28_BITS 0x0000ffff 629 #define PIO_INSTR_MEM28_RESET 0x00000000 630 #define PIO_INSTR_MEM28_MSB 15 631 #define PIO_INSTR_MEM28_LSB 0 632 #define PIO_INSTR_MEM28_ACCESS "WO" 633 // ============================================================================= 634 // Register : PIO_INSTR_MEM29 635 // Description : Write-only access to instruction memory location 29 636 #define PIO_INSTR_MEM29_OFFSET 0x000000bc 637 #define PIO_INSTR_MEM29_BITS 0x0000ffff 638 #define PIO_INSTR_MEM29_RESET 0x00000000 639 #define PIO_INSTR_MEM29_MSB 15 640 #define PIO_INSTR_MEM29_LSB 0 641 #define PIO_INSTR_MEM29_ACCESS "WO" 642 // ============================================================================= 643 // Register : PIO_INSTR_MEM30 644 // Description : Write-only access to instruction memory location 30 645 #define PIO_INSTR_MEM30_OFFSET 0x000000c0 646 #define PIO_INSTR_MEM30_BITS 0x0000ffff 647 #define PIO_INSTR_MEM30_RESET 0x00000000 648 #define PIO_INSTR_MEM30_MSB 15 649 #define PIO_INSTR_MEM30_LSB 0 650 #define PIO_INSTR_MEM30_ACCESS "WO" 651 // ============================================================================= 652 // Register : PIO_INSTR_MEM31 653 // Description : Write-only access to instruction memory location 31 654 #define PIO_INSTR_MEM31_OFFSET 0x000000c4 655 #define PIO_INSTR_MEM31_BITS 0x0000ffff 656 #define PIO_INSTR_MEM31_RESET 0x00000000 657 #define PIO_INSTR_MEM31_MSB 15 658 #define PIO_INSTR_MEM31_LSB 0 659 #define PIO_INSTR_MEM31_ACCESS "WO" 660 // ============================================================================= 661 // Register : PIO_SM0_CLKDIV 662 // Description : Clock divider register for state machine 0 663 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 664 #define PIO_SM0_CLKDIV_OFFSET 0x000000c8 665 #define PIO_SM0_CLKDIV_BITS 0xffffff00 666 #define PIO_SM0_CLKDIV_RESET 0x00010000 667 // ----------------------------------------------------------------------------- 668 // Field : PIO_SM0_CLKDIV_INT 669 // Description : Effective frequency is sysclk/int. 670 // Value of 0 is interpreted as max possible value 671 #define PIO_SM0_CLKDIV_INT_RESET 0x0001 672 #define PIO_SM0_CLKDIV_INT_BITS 0xffff0000 673 #define PIO_SM0_CLKDIV_INT_MSB 31 674 #define PIO_SM0_CLKDIV_INT_LSB 16 675 #define PIO_SM0_CLKDIV_INT_ACCESS "RW" 676 // ----------------------------------------------------------------------------- 677 // Field : PIO_SM0_CLKDIV_FRAC 678 // Description : Fractional part of clock divider 679 #define PIO_SM0_CLKDIV_FRAC_RESET 0x00 680 #define PIO_SM0_CLKDIV_FRAC_BITS 0x0000ff00 681 #define PIO_SM0_CLKDIV_FRAC_MSB 15 682 #define PIO_SM0_CLKDIV_FRAC_LSB 8 683 #define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" 684 // ============================================================================= 685 // Register : PIO_SM0_EXECCTRL 686 // Description : Execution/behavioural settings for state machine 0 687 #define PIO_SM0_EXECCTRL_OFFSET 0x000000cc 688 #define PIO_SM0_EXECCTRL_BITS 0xffffff9f 689 #define PIO_SM0_EXECCTRL_RESET 0x0001f000 690 // ----------------------------------------------------------------------------- 691 // Field : PIO_SM0_EXECCTRL_EXEC_STALLED 692 // Description : An instruction written to SMx_INSTR is stalled, and latched by 693 // the 694 // state machine. Will clear once the instruction completes. 695 #define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET 0x0 696 #define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS 0x80000000 697 #define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB 31 698 #define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB 31 699 #define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" 700 // ----------------------------------------------------------------------------- 701 // Field : PIO_SM0_EXECCTRL_SIDE_EN 702 // Description : If 1, the delay MSB is used as side-set enable, rather than a 703 // side-set data bit. This allows instructions to perform side-set 704 // optionally, 705 // rather than on every instruction. 706 #define PIO_SM0_EXECCTRL_SIDE_EN_RESET 0x0 707 #define PIO_SM0_EXECCTRL_SIDE_EN_BITS 0x40000000 708 #define PIO_SM0_EXECCTRL_SIDE_EN_MSB 30 709 #define PIO_SM0_EXECCTRL_SIDE_EN_LSB 30 710 #define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" 711 // ----------------------------------------------------------------------------- 712 // Field : PIO_SM0_EXECCTRL_SIDE_PINDIR 713 // Description : Side-set data is asserted to pin OEs instead of pin values 714 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET 0x0 715 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 716 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB 29 717 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB 29 718 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 719 // ----------------------------------------------------------------------------- 720 // Field : PIO_SM0_EXECCTRL_JMP_PIN 721 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 722 // input mapping. 723 #define PIO_SM0_EXECCTRL_JMP_PIN_RESET 0x00 724 #define PIO_SM0_EXECCTRL_JMP_PIN_BITS 0x1f000000 725 #define PIO_SM0_EXECCTRL_JMP_PIN_MSB 28 726 #define PIO_SM0_EXECCTRL_JMP_PIN_LSB 24 727 #define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" 728 // ----------------------------------------------------------------------------- 729 // Field : PIO_SM0_EXECCTRL_OUT_EN_SEL 730 // Description : Which data bit to use for inline OUT enable 731 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET 0x00 732 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 733 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB 23 734 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB 19 735 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 736 // ----------------------------------------------------------------------------- 737 // Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN 738 // Description : If 1, use a bit of OUT data as an auxiliary write enable 739 // When used in conjunction with OUT_STICKY, writes with an enable 740 // of 0 will 741 // deassert the latest pin write. This can create useful 742 // masking/override behaviour 743 // due to the priority ordering of state machine pin writes (SM0 < 744 // SM1 < ...) 745 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET 0x0 746 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 747 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB 18 748 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB 18 749 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 750 // ----------------------------------------------------------------------------- 751 // Field : PIO_SM0_EXECCTRL_OUT_STICKY 752 // Description : Continuously assert the most recent OUT/SET to the pins 753 #define PIO_SM0_EXECCTRL_OUT_STICKY_RESET 0x0 754 #define PIO_SM0_EXECCTRL_OUT_STICKY_BITS 0x00020000 755 #define PIO_SM0_EXECCTRL_OUT_STICKY_MSB 17 756 #define PIO_SM0_EXECCTRL_OUT_STICKY_LSB 17 757 #define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" 758 // ----------------------------------------------------------------------------- 759 // Field : PIO_SM0_EXECCTRL_WRAP_TOP 760 // Description : After reaching this address, execution is wrapped to 761 // wrap_bottom. 762 // If the instruction is a jump, and the jump condition is true, 763 // the jump takes priority. 764 #define PIO_SM0_EXECCTRL_WRAP_TOP_RESET 0x1f 765 #define PIO_SM0_EXECCTRL_WRAP_TOP_BITS 0x0001f000 766 #define PIO_SM0_EXECCTRL_WRAP_TOP_MSB 16 767 #define PIO_SM0_EXECCTRL_WRAP_TOP_LSB 12 768 #define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" 769 // ----------------------------------------------------------------------------- 770 // Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM 771 // Description : After reaching wrap_top, execution is wrapped to this address. 772 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET 0x00 773 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 774 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB 11 775 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB 7 776 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 777 // ----------------------------------------------------------------------------- 778 // Field : PIO_SM0_EXECCTRL_STATUS_SEL 779 // Description : Comparison used for the MOV x, STATUS instruction. 780 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 781 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 782 #define PIO_SM0_EXECCTRL_STATUS_SEL_RESET 0x0 783 #define PIO_SM0_EXECCTRL_STATUS_SEL_BITS 0x00000010 784 #define PIO_SM0_EXECCTRL_STATUS_SEL_MSB 4 785 #define PIO_SM0_EXECCTRL_STATUS_SEL_LSB 4 786 #define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" 787 #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 788 #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 789 // ----------------------------------------------------------------------------- 790 // Field : PIO_SM0_EXECCTRL_STATUS_N 791 // Description : Comparison level for the MOV x, STATUS instruction 792 #define PIO_SM0_EXECCTRL_STATUS_N_RESET 0x0 793 #define PIO_SM0_EXECCTRL_STATUS_N_BITS 0x0000000f 794 #define PIO_SM0_EXECCTRL_STATUS_N_MSB 3 795 #define PIO_SM0_EXECCTRL_STATUS_N_LSB 0 796 #define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" 797 // ============================================================================= 798 // Register : PIO_SM0_SHIFTCTRL 799 // Description : Control behaviour of the input/output shift registers for state 800 // machine 0 801 #define PIO_SM0_SHIFTCTRL_OFFSET 0x000000d0 802 #define PIO_SM0_SHIFTCTRL_BITS 0xffff0000 803 #define PIO_SM0_SHIFTCTRL_RESET 0x000c0000 804 // ----------------------------------------------------------------------------- 805 // Field : PIO_SM0_SHIFTCTRL_FJOIN_RX 806 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 807 // as deep. 808 // TX FIFO is disabled as a result (always reads as both full and 809 // empty). 810 // FIFOs are flushed when this bit is changed. 811 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET 0x0 812 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 813 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB 31 814 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB 31 815 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 816 // ----------------------------------------------------------------------------- 817 // Field : PIO_SM0_SHIFTCTRL_FJOIN_TX 818 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 819 // as deep. 820 // RX FIFO is disabled as a result (always reads as both full and 821 // empty). 822 // FIFOs are flushed when this bit is changed. 823 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET 0x0 824 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 825 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB 30 826 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB 30 827 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 828 // ----------------------------------------------------------------------------- 829 // Field : PIO_SM0_SHIFTCTRL_PULL_THRESH 830 // Description : Number of bits shifted out of TXSR before autopull or 831 // conditional pull. 832 // Write 0 for value of 32. 833 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET 0x00 834 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 835 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB 29 836 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB 25 837 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 838 // ----------------------------------------------------------------------------- 839 // Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH 840 // Description : Number of bits shifted into RXSR before autopush or conditional 841 // push. 842 // Write 0 for value of 32. 843 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET 0x00 844 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 845 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB 24 846 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB 20 847 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 848 // ----------------------------------------------------------------------------- 849 // Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR 850 // Description : 1 = shift out of output shift register to right. 0 = to left. 851 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 852 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 853 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 854 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 855 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 856 // ----------------------------------------------------------------------------- 857 // Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR 858 // Description : 1 = shift input shift register to right (data enters from 859 // left). 0 = to left. 860 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 861 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 862 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB 18 863 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB 18 864 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 865 // ----------------------------------------------------------------------------- 866 // Field : PIO_SM0_SHIFTCTRL_AUTOPULL 867 // Description : Pull automatically when the output shift register is emptied 868 #define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET 0x0 869 #define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS 0x00020000 870 #define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB 17 871 #define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB 17 872 #define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" 873 // ----------------------------------------------------------------------------- 874 // Field : PIO_SM0_SHIFTCTRL_AUTOPUSH 875 // Description : Push automatically when the input shift register is filled 876 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET 0x0 877 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 878 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB 16 879 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB 16 880 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 881 // ============================================================================= 882 // Register : PIO_SM0_ADDR 883 // Description : Current instruction address of state machine 0 884 #define PIO_SM0_ADDR_OFFSET 0x000000d4 885 #define PIO_SM0_ADDR_BITS 0x0000001f 886 #define PIO_SM0_ADDR_RESET 0x00000000 887 #define PIO_SM0_ADDR_MSB 4 888 #define PIO_SM0_ADDR_LSB 0 889 #define PIO_SM0_ADDR_ACCESS "RO" 890 // ============================================================================= 891 // Register : PIO_SM0_INSTR 892 // Description : Instruction currently being executed by state machine 0 893 // Write to execute an instruction immediately (including jumps) 894 // and then resume execution. 895 #define PIO_SM0_INSTR_OFFSET 0x000000d8 896 #define PIO_SM0_INSTR_BITS 0x0000ffff 897 #define PIO_SM0_INSTR_RESET "-" 898 #define PIO_SM0_INSTR_MSB 15 899 #define PIO_SM0_INSTR_LSB 0 900 #define PIO_SM0_INSTR_ACCESS "RW" 901 // ============================================================================= 902 // Register : PIO_SM0_PINCTRL 903 // Description : State machine pin control 904 #define PIO_SM0_PINCTRL_OFFSET 0x000000dc 905 #define PIO_SM0_PINCTRL_BITS 0xffffffff 906 #define PIO_SM0_PINCTRL_RESET 0x14000000 907 // ----------------------------------------------------------------------------- 908 // Field : PIO_SM0_PINCTRL_SIDESET_COUNT 909 // Description : The number of delay bits co-opted for side-set. Inclusive of 910 // the enable bit, if present. 911 #define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET 0x0 912 #define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 913 #define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB 31 914 #define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB 29 915 #define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" 916 // ----------------------------------------------------------------------------- 917 // Field : PIO_SM0_PINCTRL_SET_COUNT 918 // Description : The number of pins asserted by a SET. Max of 5 919 #define PIO_SM0_PINCTRL_SET_COUNT_RESET 0x5 920 #define PIO_SM0_PINCTRL_SET_COUNT_BITS 0x1c000000 921 #define PIO_SM0_PINCTRL_SET_COUNT_MSB 28 922 #define PIO_SM0_PINCTRL_SET_COUNT_LSB 26 923 #define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" 924 // ----------------------------------------------------------------------------- 925 // Field : PIO_SM0_PINCTRL_OUT_COUNT 926 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 927 #define PIO_SM0_PINCTRL_OUT_COUNT_RESET 0x00 928 #define PIO_SM0_PINCTRL_OUT_COUNT_BITS 0x03f00000 929 #define PIO_SM0_PINCTRL_OUT_COUNT_MSB 25 930 #define PIO_SM0_PINCTRL_OUT_COUNT_LSB 20 931 #define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" 932 // ----------------------------------------------------------------------------- 933 // Field : PIO_SM0_PINCTRL_IN_BASE 934 // Description : The virtual pin corresponding to IN bit 0 935 #define PIO_SM0_PINCTRL_IN_BASE_RESET 0x00 936 #define PIO_SM0_PINCTRL_IN_BASE_BITS 0x000f8000 937 #define PIO_SM0_PINCTRL_IN_BASE_MSB 19 938 #define PIO_SM0_PINCTRL_IN_BASE_LSB 15 939 #define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" 940 // ----------------------------------------------------------------------------- 941 // Field : PIO_SM0_PINCTRL_SIDESET_BASE 942 // Description : The virtual pin corresponding to delay field bit 0 943 #define PIO_SM0_PINCTRL_SIDESET_BASE_RESET 0x00 944 #define PIO_SM0_PINCTRL_SIDESET_BASE_BITS 0x00007c00 945 #define PIO_SM0_PINCTRL_SIDESET_BASE_MSB 14 946 #define PIO_SM0_PINCTRL_SIDESET_BASE_LSB 10 947 #define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" 948 // ----------------------------------------------------------------------------- 949 // Field : PIO_SM0_PINCTRL_SET_BASE 950 // Description : The virtual pin corresponding to SET bit 0 951 #define PIO_SM0_PINCTRL_SET_BASE_RESET 0x00 952 #define PIO_SM0_PINCTRL_SET_BASE_BITS 0x000003e0 953 #define PIO_SM0_PINCTRL_SET_BASE_MSB 9 954 #define PIO_SM0_PINCTRL_SET_BASE_LSB 5 955 #define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" 956 // ----------------------------------------------------------------------------- 957 // Field : PIO_SM0_PINCTRL_OUT_BASE 958 // Description : The virtual pin corresponding to OUT bit 0 959 #define PIO_SM0_PINCTRL_OUT_BASE_RESET 0x00 960 #define PIO_SM0_PINCTRL_OUT_BASE_BITS 0x0000001f 961 #define PIO_SM0_PINCTRL_OUT_BASE_MSB 4 962 #define PIO_SM0_PINCTRL_OUT_BASE_LSB 0 963 #define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" 964 // ============================================================================= 965 // Register : PIO_SM1_CLKDIV 966 // Description : Clock divider register for state machine 1 967 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 968 #define PIO_SM1_CLKDIV_OFFSET 0x000000e0 969 #define PIO_SM1_CLKDIV_BITS 0xffffff00 970 #define PIO_SM1_CLKDIV_RESET 0x00010000 971 // ----------------------------------------------------------------------------- 972 // Field : PIO_SM1_CLKDIV_INT 973 // Description : Effective frequency is sysclk/int. 974 // Value of 0 is interpreted as max possible value 975 #define PIO_SM1_CLKDIV_INT_RESET 0x0001 976 #define PIO_SM1_CLKDIV_INT_BITS 0xffff0000 977 #define PIO_SM1_CLKDIV_INT_MSB 31 978 #define PIO_SM1_CLKDIV_INT_LSB 16 979 #define PIO_SM1_CLKDIV_INT_ACCESS "RW" 980 // ----------------------------------------------------------------------------- 981 // Field : PIO_SM1_CLKDIV_FRAC 982 // Description : Fractional part of clock divider 983 #define PIO_SM1_CLKDIV_FRAC_RESET 0x00 984 #define PIO_SM1_CLKDIV_FRAC_BITS 0x0000ff00 985 #define PIO_SM1_CLKDIV_FRAC_MSB 15 986 #define PIO_SM1_CLKDIV_FRAC_LSB 8 987 #define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" 988 // ============================================================================= 989 // Register : PIO_SM1_EXECCTRL 990 // Description : Execution/behavioural settings for state machine 1 991 #define PIO_SM1_EXECCTRL_OFFSET 0x000000e4 992 #define PIO_SM1_EXECCTRL_BITS 0xffffff9f 993 #define PIO_SM1_EXECCTRL_RESET 0x0001f000 994 // ----------------------------------------------------------------------------- 995 // Field : PIO_SM1_EXECCTRL_EXEC_STALLED 996 // Description : An instruction written to SMx_INSTR is stalled, and latched by 997 // the 998 // state machine. Will clear once the instruction completes. 999 #define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET 0x0 1000 #define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS 0x80000000 1001 #define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB 31 1002 #define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB 31 1003 #define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" 1004 // ----------------------------------------------------------------------------- 1005 // Field : PIO_SM1_EXECCTRL_SIDE_EN 1006 // Description : If 1, the delay MSB is used as side-set enable, rather than a 1007 // side-set data bit. This allows instructions to perform side-set 1008 // optionally, 1009 // rather than on every instruction. 1010 #define PIO_SM1_EXECCTRL_SIDE_EN_RESET 0x0 1011 #define PIO_SM1_EXECCTRL_SIDE_EN_BITS 0x40000000 1012 #define PIO_SM1_EXECCTRL_SIDE_EN_MSB 30 1013 #define PIO_SM1_EXECCTRL_SIDE_EN_LSB 30 1014 #define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" 1015 // ----------------------------------------------------------------------------- 1016 // Field : PIO_SM1_EXECCTRL_SIDE_PINDIR 1017 // Description : Side-set data is asserted to pin OEs instead of pin values 1018 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET 0x0 1019 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 1020 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB 29 1021 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB 29 1022 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 1023 // ----------------------------------------------------------------------------- 1024 // Field : PIO_SM1_EXECCTRL_JMP_PIN 1025 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 1026 // input mapping. 1027 #define PIO_SM1_EXECCTRL_JMP_PIN_RESET 0x00 1028 #define PIO_SM1_EXECCTRL_JMP_PIN_BITS 0x1f000000 1029 #define PIO_SM1_EXECCTRL_JMP_PIN_MSB 28 1030 #define PIO_SM1_EXECCTRL_JMP_PIN_LSB 24 1031 #define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" 1032 // ----------------------------------------------------------------------------- 1033 // Field : PIO_SM1_EXECCTRL_OUT_EN_SEL 1034 // Description : Which data bit to use for inline OUT enable 1035 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET 0x00 1036 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 1037 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB 23 1038 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB 19 1039 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 1040 // ----------------------------------------------------------------------------- 1041 // Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN 1042 // Description : If 1, use a bit of OUT data as an auxiliary write enable 1043 // When used in conjunction with OUT_STICKY, writes with an enable 1044 // of 0 will 1045 // deassert the latest pin write. This can create useful 1046 // masking/override behaviour 1047 // due to the priority ordering of state machine pin writes (SM0 < 1048 // SM1 < ...) 1049 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET 0x0 1050 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 1051 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB 18 1052 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB 18 1053 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 1054 // ----------------------------------------------------------------------------- 1055 // Field : PIO_SM1_EXECCTRL_OUT_STICKY 1056 // Description : Continuously assert the most recent OUT/SET to the pins 1057 #define PIO_SM1_EXECCTRL_OUT_STICKY_RESET 0x0 1058 #define PIO_SM1_EXECCTRL_OUT_STICKY_BITS 0x00020000 1059 #define PIO_SM1_EXECCTRL_OUT_STICKY_MSB 17 1060 #define PIO_SM1_EXECCTRL_OUT_STICKY_LSB 17 1061 #define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" 1062 // ----------------------------------------------------------------------------- 1063 // Field : PIO_SM1_EXECCTRL_WRAP_TOP 1064 // Description : After reaching this address, execution is wrapped to 1065 // wrap_bottom. 1066 // If the instruction is a jump, and the jump condition is true, 1067 // the jump takes priority. 1068 #define PIO_SM1_EXECCTRL_WRAP_TOP_RESET 0x1f 1069 #define PIO_SM1_EXECCTRL_WRAP_TOP_BITS 0x0001f000 1070 #define PIO_SM1_EXECCTRL_WRAP_TOP_MSB 16 1071 #define PIO_SM1_EXECCTRL_WRAP_TOP_LSB 12 1072 #define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" 1073 // ----------------------------------------------------------------------------- 1074 // Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM 1075 // Description : After reaching wrap_top, execution is wrapped to this address. 1076 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET 0x00 1077 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 1078 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB 11 1079 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB 7 1080 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 1081 // ----------------------------------------------------------------------------- 1082 // Field : PIO_SM1_EXECCTRL_STATUS_SEL 1083 // Description : Comparison used for the MOV x, STATUS instruction. 1084 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 1085 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 1086 #define PIO_SM1_EXECCTRL_STATUS_SEL_RESET 0x0 1087 #define PIO_SM1_EXECCTRL_STATUS_SEL_BITS 0x00000010 1088 #define PIO_SM1_EXECCTRL_STATUS_SEL_MSB 4 1089 #define PIO_SM1_EXECCTRL_STATUS_SEL_LSB 4 1090 #define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" 1091 #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 1092 #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 1093 // ----------------------------------------------------------------------------- 1094 // Field : PIO_SM1_EXECCTRL_STATUS_N 1095 // Description : Comparison level for the MOV x, STATUS instruction 1096 #define PIO_SM1_EXECCTRL_STATUS_N_RESET 0x0 1097 #define PIO_SM1_EXECCTRL_STATUS_N_BITS 0x0000000f 1098 #define PIO_SM1_EXECCTRL_STATUS_N_MSB 3 1099 #define PIO_SM1_EXECCTRL_STATUS_N_LSB 0 1100 #define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" 1101 // ============================================================================= 1102 // Register : PIO_SM1_SHIFTCTRL 1103 // Description : Control behaviour of the input/output shift registers for state 1104 // machine 1 1105 #define PIO_SM1_SHIFTCTRL_OFFSET 0x000000e8 1106 #define PIO_SM1_SHIFTCTRL_BITS 0xffff0000 1107 #define PIO_SM1_SHIFTCTRL_RESET 0x000c0000 1108 // ----------------------------------------------------------------------------- 1109 // Field : PIO_SM1_SHIFTCTRL_FJOIN_RX 1110 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 1111 // as deep. 1112 // TX FIFO is disabled as a result (always reads as both full and 1113 // empty). 1114 // FIFOs are flushed when this bit is changed. 1115 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET 0x0 1116 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 1117 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB 31 1118 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB 31 1119 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 1120 // ----------------------------------------------------------------------------- 1121 // Field : PIO_SM1_SHIFTCTRL_FJOIN_TX 1122 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 1123 // as deep. 1124 // RX FIFO is disabled as a result (always reads as both full and 1125 // empty). 1126 // FIFOs are flushed when this bit is changed. 1127 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET 0x0 1128 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 1129 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB 30 1130 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB 30 1131 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 1132 // ----------------------------------------------------------------------------- 1133 // Field : PIO_SM1_SHIFTCTRL_PULL_THRESH 1134 // Description : Number of bits shifted out of TXSR before autopull or 1135 // conditional pull. 1136 // Write 0 for value of 32. 1137 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET 0x00 1138 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 1139 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB 29 1140 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB 25 1141 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 1142 // ----------------------------------------------------------------------------- 1143 // Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH 1144 // Description : Number of bits shifted into RXSR before autopush or conditional 1145 // push. 1146 // Write 0 for value of 32. 1147 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET 0x00 1148 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 1149 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB 24 1150 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB 20 1151 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 1152 // ----------------------------------------------------------------------------- 1153 // Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR 1154 // Description : 1 = shift out of output shift register to right. 0 = to left. 1155 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 1156 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 1157 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 1158 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 1159 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 1160 // ----------------------------------------------------------------------------- 1161 // Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR 1162 // Description : 1 = shift input shift register to right (data enters from 1163 // left). 0 = to left. 1164 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 1165 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 1166 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB 18 1167 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB 18 1168 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 1169 // ----------------------------------------------------------------------------- 1170 // Field : PIO_SM1_SHIFTCTRL_AUTOPULL 1171 // Description : Pull automatically when the output shift register is emptied 1172 #define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET 0x0 1173 #define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS 0x00020000 1174 #define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB 17 1175 #define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB 17 1176 #define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1177 // ----------------------------------------------------------------------------- 1178 // Field : PIO_SM1_SHIFTCTRL_AUTOPUSH 1179 // Description : Push automatically when the input shift register is filled 1180 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET 0x0 1181 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 1182 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB 16 1183 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB 16 1184 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1185 // ============================================================================= 1186 // Register : PIO_SM1_ADDR 1187 // Description : Current instruction address of state machine 1 1188 #define PIO_SM1_ADDR_OFFSET 0x000000ec 1189 #define PIO_SM1_ADDR_BITS 0x0000001f 1190 #define PIO_SM1_ADDR_RESET 0x00000000 1191 #define PIO_SM1_ADDR_MSB 4 1192 #define PIO_SM1_ADDR_LSB 0 1193 #define PIO_SM1_ADDR_ACCESS "RO" 1194 // ============================================================================= 1195 // Register : PIO_SM1_INSTR 1196 // Description : Instruction currently being executed by state machine 1 1197 // Write to execute an instruction immediately (including jumps) 1198 // and then resume execution. 1199 #define PIO_SM1_INSTR_OFFSET 0x000000f0 1200 #define PIO_SM1_INSTR_BITS 0x0000ffff 1201 #define PIO_SM1_INSTR_RESET "-" 1202 #define PIO_SM1_INSTR_MSB 15 1203 #define PIO_SM1_INSTR_LSB 0 1204 #define PIO_SM1_INSTR_ACCESS "RW" 1205 // ============================================================================= 1206 // Register : PIO_SM1_PINCTRL 1207 // Description : State machine pin control 1208 #define PIO_SM1_PINCTRL_OFFSET 0x000000f4 1209 #define PIO_SM1_PINCTRL_BITS 0xffffffff 1210 #define PIO_SM1_PINCTRL_RESET 0x14000000 1211 // ----------------------------------------------------------------------------- 1212 // Field : PIO_SM1_PINCTRL_SIDESET_COUNT 1213 // Description : The number of delay bits co-opted for side-set. Inclusive of 1214 // the enable bit, if present. 1215 #define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET 0x0 1216 #define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 1217 #define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB 31 1218 #define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB 29 1219 #define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1220 // ----------------------------------------------------------------------------- 1221 // Field : PIO_SM1_PINCTRL_SET_COUNT 1222 // Description : The number of pins asserted by a SET. Max of 5 1223 #define PIO_SM1_PINCTRL_SET_COUNT_RESET 0x5 1224 #define PIO_SM1_PINCTRL_SET_COUNT_BITS 0x1c000000 1225 #define PIO_SM1_PINCTRL_SET_COUNT_MSB 28 1226 #define PIO_SM1_PINCTRL_SET_COUNT_LSB 26 1227 #define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" 1228 // ----------------------------------------------------------------------------- 1229 // Field : PIO_SM1_PINCTRL_OUT_COUNT 1230 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1231 #define PIO_SM1_PINCTRL_OUT_COUNT_RESET 0x00 1232 #define PIO_SM1_PINCTRL_OUT_COUNT_BITS 0x03f00000 1233 #define PIO_SM1_PINCTRL_OUT_COUNT_MSB 25 1234 #define PIO_SM1_PINCTRL_OUT_COUNT_LSB 20 1235 #define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" 1236 // ----------------------------------------------------------------------------- 1237 // Field : PIO_SM1_PINCTRL_IN_BASE 1238 // Description : The virtual pin corresponding to IN bit 0 1239 #define PIO_SM1_PINCTRL_IN_BASE_RESET 0x00 1240 #define PIO_SM1_PINCTRL_IN_BASE_BITS 0x000f8000 1241 #define PIO_SM1_PINCTRL_IN_BASE_MSB 19 1242 #define PIO_SM1_PINCTRL_IN_BASE_LSB 15 1243 #define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" 1244 // ----------------------------------------------------------------------------- 1245 // Field : PIO_SM1_PINCTRL_SIDESET_BASE 1246 // Description : The virtual pin corresponding to delay field bit 0 1247 #define PIO_SM1_PINCTRL_SIDESET_BASE_RESET 0x00 1248 #define PIO_SM1_PINCTRL_SIDESET_BASE_BITS 0x00007c00 1249 #define PIO_SM1_PINCTRL_SIDESET_BASE_MSB 14 1250 #define PIO_SM1_PINCTRL_SIDESET_BASE_LSB 10 1251 #define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" 1252 // ----------------------------------------------------------------------------- 1253 // Field : PIO_SM1_PINCTRL_SET_BASE 1254 // Description : The virtual pin corresponding to SET bit 0 1255 #define PIO_SM1_PINCTRL_SET_BASE_RESET 0x00 1256 #define PIO_SM1_PINCTRL_SET_BASE_BITS 0x000003e0 1257 #define PIO_SM1_PINCTRL_SET_BASE_MSB 9 1258 #define PIO_SM1_PINCTRL_SET_BASE_LSB 5 1259 #define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" 1260 // ----------------------------------------------------------------------------- 1261 // Field : PIO_SM1_PINCTRL_OUT_BASE 1262 // Description : The virtual pin corresponding to OUT bit 0 1263 #define PIO_SM1_PINCTRL_OUT_BASE_RESET 0x00 1264 #define PIO_SM1_PINCTRL_OUT_BASE_BITS 0x0000001f 1265 #define PIO_SM1_PINCTRL_OUT_BASE_MSB 4 1266 #define PIO_SM1_PINCTRL_OUT_BASE_LSB 0 1267 #define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" 1268 // ============================================================================= 1269 // Register : PIO_SM2_CLKDIV 1270 // Description : Clock divider register for state machine 2 1271 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 1272 #define PIO_SM2_CLKDIV_OFFSET 0x000000f8 1273 #define PIO_SM2_CLKDIV_BITS 0xffffff00 1274 #define PIO_SM2_CLKDIV_RESET 0x00010000 1275 // ----------------------------------------------------------------------------- 1276 // Field : PIO_SM2_CLKDIV_INT 1277 // Description : Effective frequency is sysclk/int. 1278 // Value of 0 is interpreted as max possible value 1279 #define PIO_SM2_CLKDIV_INT_RESET 0x0001 1280 #define PIO_SM2_CLKDIV_INT_BITS 0xffff0000 1281 #define PIO_SM2_CLKDIV_INT_MSB 31 1282 #define PIO_SM2_CLKDIV_INT_LSB 16 1283 #define PIO_SM2_CLKDIV_INT_ACCESS "RW" 1284 // ----------------------------------------------------------------------------- 1285 // Field : PIO_SM2_CLKDIV_FRAC 1286 // Description : Fractional part of clock divider 1287 #define PIO_SM2_CLKDIV_FRAC_RESET 0x00 1288 #define PIO_SM2_CLKDIV_FRAC_BITS 0x0000ff00 1289 #define PIO_SM2_CLKDIV_FRAC_MSB 15 1290 #define PIO_SM2_CLKDIV_FRAC_LSB 8 1291 #define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" 1292 // ============================================================================= 1293 // Register : PIO_SM2_EXECCTRL 1294 // Description : Execution/behavioural settings for state machine 2 1295 #define PIO_SM2_EXECCTRL_OFFSET 0x000000fc 1296 #define PIO_SM2_EXECCTRL_BITS 0xffffff9f 1297 #define PIO_SM2_EXECCTRL_RESET 0x0001f000 1298 // ----------------------------------------------------------------------------- 1299 // Field : PIO_SM2_EXECCTRL_EXEC_STALLED 1300 // Description : An instruction written to SMx_INSTR is stalled, and latched by 1301 // the 1302 // state machine. Will clear once the instruction completes. 1303 #define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET 0x0 1304 #define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS 0x80000000 1305 #define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB 31 1306 #define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB 31 1307 #define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" 1308 // ----------------------------------------------------------------------------- 1309 // Field : PIO_SM2_EXECCTRL_SIDE_EN 1310 // Description : If 1, the delay MSB is used as side-set enable, rather than a 1311 // side-set data bit. This allows instructions to perform side-set 1312 // optionally, 1313 // rather than on every instruction. 1314 #define PIO_SM2_EXECCTRL_SIDE_EN_RESET 0x0 1315 #define PIO_SM2_EXECCTRL_SIDE_EN_BITS 0x40000000 1316 #define PIO_SM2_EXECCTRL_SIDE_EN_MSB 30 1317 #define PIO_SM2_EXECCTRL_SIDE_EN_LSB 30 1318 #define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" 1319 // ----------------------------------------------------------------------------- 1320 // Field : PIO_SM2_EXECCTRL_SIDE_PINDIR 1321 // Description : Side-set data is asserted to pin OEs instead of pin values 1322 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET 0x0 1323 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 1324 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB 29 1325 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB 29 1326 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 1327 // ----------------------------------------------------------------------------- 1328 // Field : PIO_SM2_EXECCTRL_JMP_PIN 1329 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 1330 // input mapping. 1331 #define PIO_SM2_EXECCTRL_JMP_PIN_RESET 0x00 1332 #define PIO_SM2_EXECCTRL_JMP_PIN_BITS 0x1f000000 1333 #define PIO_SM2_EXECCTRL_JMP_PIN_MSB 28 1334 #define PIO_SM2_EXECCTRL_JMP_PIN_LSB 24 1335 #define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" 1336 // ----------------------------------------------------------------------------- 1337 // Field : PIO_SM2_EXECCTRL_OUT_EN_SEL 1338 // Description : Which data bit to use for inline OUT enable 1339 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET 0x00 1340 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 1341 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB 23 1342 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB 19 1343 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 1344 // ----------------------------------------------------------------------------- 1345 // Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN 1346 // Description : If 1, use a bit of OUT data as an auxiliary write enable 1347 // When used in conjunction with OUT_STICKY, writes with an enable 1348 // of 0 will 1349 // deassert the latest pin write. This can create useful 1350 // masking/override behaviour 1351 // due to the priority ordering of state machine pin writes (SM0 < 1352 // SM1 < ...) 1353 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET 0x0 1354 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 1355 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB 18 1356 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB 18 1357 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 1358 // ----------------------------------------------------------------------------- 1359 // Field : PIO_SM2_EXECCTRL_OUT_STICKY 1360 // Description : Continuously assert the most recent OUT/SET to the pins 1361 #define PIO_SM2_EXECCTRL_OUT_STICKY_RESET 0x0 1362 #define PIO_SM2_EXECCTRL_OUT_STICKY_BITS 0x00020000 1363 #define PIO_SM2_EXECCTRL_OUT_STICKY_MSB 17 1364 #define PIO_SM2_EXECCTRL_OUT_STICKY_LSB 17 1365 #define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" 1366 // ----------------------------------------------------------------------------- 1367 // Field : PIO_SM2_EXECCTRL_WRAP_TOP 1368 // Description : After reaching this address, execution is wrapped to 1369 // wrap_bottom. 1370 // If the instruction is a jump, and the jump condition is true, 1371 // the jump takes priority. 1372 #define PIO_SM2_EXECCTRL_WRAP_TOP_RESET 0x1f 1373 #define PIO_SM2_EXECCTRL_WRAP_TOP_BITS 0x0001f000 1374 #define PIO_SM2_EXECCTRL_WRAP_TOP_MSB 16 1375 #define PIO_SM2_EXECCTRL_WRAP_TOP_LSB 12 1376 #define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" 1377 // ----------------------------------------------------------------------------- 1378 // Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM 1379 // Description : After reaching wrap_top, execution is wrapped to this address. 1380 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET 0x00 1381 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 1382 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB 11 1383 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB 7 1384 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 1385 // ----------------------------------------------------------------------------- 1386 // Field : PIO_SM2_EXECCTRL_STATUS_SEL 1387 // Description : Comparison used for the MOV x, STATUS instruction. 1388 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 1389 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 1390 #define PIO_SM2_EXECCTRL_STATUS_SEL_RESET 0x0 1391 #define PIO_SM2_EXECCTRL_STATUS_SEL_BITS 0x00000010 1392 #define PIO_SM2_EXECCTRL_STATUS_SEL_MSB 4 1393 #define PIO_SM2_EXECCTRL_STATUS_SEL_LSB 4 1394 #define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" 1395 #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 1396 #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 1397 // ----------------------------------------------------------------------------- 1398 // Field : PIO_SM2_EXECCTRL_STATUS_N 1399 // Description : Comparison level for the MOV x, STATUS instruction 1400 #define PIO_SM2_EXECCTRL_STATUS_N_RESET 0x0 1401 #define PIO_SM2_EXECCTRL_STATUS_N_BITS 0x0000000f 1402 #define PIO_SM2_EXECCTRL_STATUS_N_MSB 3 1403 #define PIO_SM2_EXECCTRL_STATUS_N_LSB 0 1404 #define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" 1405 // ============================================================================= 1406 // Register : PIO_SM2_SHIFTCTRL 1407 // Description : Control behaviour of the input/output shift registers for state 1408 // machine 2 1409 #define PIO_SM2_SHIFTCTRL_OFFSET 0x00000100 1410 #define PIO_SM2_SHIFTCTRL_BITS 0xffff0000 1411 #define PIO_SM2_SHIFTCTRL_RESET 0x000c0000 1412 // ----------------------------------------------------------------------------- 1413 // Field : PIO_SM2_SHIFTCTRL_FJOIN_RX 1414 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 1415 // as deep. 1416 // TX FIFO is disabled as a result (always reads as both full and 1417 // empty). 1418 // FIFOs are flushed when this bit is changed. 1419 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET 0x0 1420 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 1421 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB 31 1422 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB 31 1423 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 1424 // ----------------------------------------------------------------------------- 1425 // Field : PIO_SM2_SHIFTCTRL_FJOIN_TX 1426 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 1427 // as deep. 1428 // RX FIFO is disabled as a result (always reads as both full and 1429 // empty). 1430 // FIFOs are flushed when this bit is changed. 1431 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET 0x0 1432 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 1433 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB 30 1434 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB 30 1435 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 1436 // ----------------------------------------------------------------------------- 1437 // Field : PIO_SM2_SHIFTCTRL_PULL_THRESH 1438 // Description : Number of bits shifted out of TXSR before autopull or 1439 // conditional pull. 1440 // Write 0 for value of 32. 1441 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET 0x00 1442 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 1443 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB 29 1444 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB 25 1445 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 1446 // ----------------------------------------------------------------------------- 1447 // Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH 1448 // Description : Number of bits shifted into RXSR before autopush or conditional 1449 // push. 1450 // Write 0 for value of 32. 1451 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET 0x00 1452 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 1453 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB 24 1454 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB 20 1455 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 1456 // ----------------------------------------------------------------------------- 1457 // Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR 1458 // Description : 1 = shift out of output shift register to right. 0 = to left. 1459 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 1460 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 1461 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 1462 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 1463 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 1464 // ----------------------------------------------------------------------------- 1465 // Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR 1466 // Description : 1 = shift input shift register to right (data enters from 1467 // left). 0 = to left. 1468 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 1469 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 1470 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB 18 1471 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB 18 1472 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 1473 // ----------------------------------------------------------------------------- 1474 // Field : PIO_SM2_SHIFTCTRL_AUTOPULL 1475 // Description : Pull automatically when the output shift register is emptied 1476 #define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET 0x0 1477 #define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS 0x00020000 1478 #define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB 17 1479 #define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB 17 1480 #define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1481 // ----------------------------------------------------------------------------- 1482 // Field : PIO_SM2_SHIFTCTRL_AUTOPUSH 1483 // Description : Push automatically when the input shift register is filled 1484 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET 0x0 1485 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 1486 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB 16 1487 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB 16 1488 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1489 // ============================================================================= 1490 // Register : PIO_SM2_ADDR 1491 // Description : Current instruction address of state machine 2 1492 #define PIO_SM2_ADDR_OFFSET 0x00000104 1493 #define PIO_SM2_ADDR_BITS 0x0000001f 1494 #define PIO_SM2_ADDR_RESET 0x00000000 1495 #define PIO_SM2_ADDR_MSB 4 1496 #define PIO_SM2_ADDR_LSB 0 1497 #define PIO_SM2_ADDR_ACCESS "RO" 1498 // ============================================================================= 1499 // Register : PIO_SM2_INSTR 1500 // Description : Instruction currently being executed by state machine 2 1501 // Write to execute an instruction immediately (including jumps) 1502 // and then resume execution. 1503 #define PIO_SM2_INSTR_OFFSET 0x00000108 1504 #define PIO_SM2_INSTR_BITS 0x0000ffff 1505 #define PIO_SM2_INSTR_RESET "-" 1506 #define PIO_SM2_INSTR_MSB 15 1507 #define PIO_SM2_INSTR_LSB 0 1508 #define PIO_SM2_INSTR_ACCESS "RW" 1509 // ============================================================================= 1510 // Register : PIO_SM2_PINCTRL 1511 // Description : State machine pin control 1512 #define PIO_SM2_PINCTRL_OFFSET 0x0000010c 1513 #define PIO_SM2_PINCTRL_BITS 0xffffffff 1514 #define PIO_SM2_PINCTRL_RESET 0x14000000 1515 // ----------------------------------------------------------------------------- 1516 // Field : PIO_SM2_PINCTRL_SIDESET_COUNT 1517 // Description : The number of delay bits co-opted for side-set. Inclusive of 1518 // the enable bit, if present. 1519 #define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET 0x0 1520 #define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 1521 #define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB 31 1522 #define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB 29 1523 #define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1524 // ----------------------------------------------------------------------------- 1525 // Field : PIO_SM2_PINCTRL_SET_COUNT 1526 // Description : The number of pins asserted by a SET. Max of 5 1527 #define PIO_SM2_PINCTRL_SET_COUNT_RESET 0x5 1528 #define PIO_SM2_PINCTRL_SET_COUNT_BITS 0x1c000000 1529 #define PIO_SM2_PINCTRL_SET_COUNT_MSB 28 1530 #define PIO_SM2_PINCTRL_SET_COUNT_LSB 26 1531 #define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" 1532 // ----------------------------------------------------------------------------- 1533 // Field : PIO_SM2_PINCTRL_OUT_COUNT 1534 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1535 #define PIO_SM2_PINCTRL_OUT_COUNT_RESET 0x00 1536 #define PIO_SM2_PINCTRL_OUT_COUNT_BITS 0x03f00000 1537 #define PIO_SM2_PINCTRL_OUT_COUNT_MSB 25 1538 #define PIO_SM2_PINCTRL_OUT_COUNT_LSB 20 1539 #define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" 1540 // ----------------------------------------------------------------------------- 1541 // Field : PIO_SM2_PINCTRL_IN_BASE 1542 // Description : The virtual pin corresponding to IN bit 0 1543 #define PIO_SM2_PINCTRL_IN_BASE_RESET 0x00 1544 #define PIO_SM2_PINCTRL_IN_BASE_BITS 0x000f8000 1545 #define PIO_SM2_PINCTRL_IN_BASE_MSB 19 1546 #define PIO_SM2_PINCTRL_IN_BASE_LSB 15 1547 #define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" 1548 // ----------------------------------------------------------------------------- 1549 // Field : PIO_SM2_PINCTRL_SIDESET_BASE 1550 // Description : The virtual pin corresponding to delay field bit 0 1551 #define PIO_SM2_PINCTRL_SIDESET_BASE_RESET 0x00 1552 #define PIO_SM2_PINCTRL_SIDESET_BASE_BITS 0x00007c00 1553 #define PIO_SM2_PINCTRL_SIDESET_BASE_MSB 14 1554 #define PIO_SM2_PINCTRL_SIDESET_BASE_LSB 10 1555 #define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" 1556 // ----------------------------------------------------------------------------- 1557 // Field : PIO_SM2_PINCTRL_SET_BASE 1558 // Description : The virtual pin corresponding to SET bit 0 1559 #define PIO_SM2_PINCTRL_SET_BASE_RESET 0x00 1560 #define PIO_SM2_PINCTRL_SET_BASE_BITS 0x000003e0 1561 #define PIO_SM2_PINCTRL_SET_BASE_MSB 9 1562 #define PIO_SM2_PINCTRL_SET_BASE_LSB 5 1563 #define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" 1564 // ----------------------------------------------------------------------------- 1565 // Field : PIO_SM2_PINCTRL_OUT_BASE 1566 // Description : The virtual pin corresponding to OUT bit 0 1567 #define PIO_SM2_PINCTRL_OUT_BASE_RESET 0x00 1568 #define PIO_SM2_PINCTRL_OUT_BASE_BITS 0x0000001f 1569 #define PIO_SM2_PINCTRL_OUT_BASE_MSB 4 1570 #define PIO_SM2_PINCTRL_OUT_BASE_LSB 0 1571 #define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" 1572 // ============================================================================= 1573 // Register : PIO_SM3_CLKDIV 1574 // Description : Clock divider register for state machine 3 1575 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 1576 #define PIO_SM3_CLKDIV_OFFSET 0x00000110 1577 #define PIO_SM3_CLKDIV_BITS 0xffffff00 1578 #define PIO_SM3_CLKDIV_RESET 0x00010000 1579 // ----------------------------------------------------------------------------- 1580 // Field : PIO_SM3_CLKDIV_INT 1581 // Description : Effective frequency is sysclk/int. 1582 // Value of 0 is interpreted as max possible value 1583 #define PIO_SM3_CLKDIV_INT_RESET 0x0001 1584 #define PIO_SM3_CLKDIV_INT_BITS 0xffff0000 1585 #define PIO_SM3_CLKDIV_INT_MSB 31 1586 #define PIO_SM3_CLKDIV_INT_LSB 16 1587 #define PIO_SM3_CLKDIV_INT_ACCESS "RW" 1588 // ----------------------------------------------------------------------------- 1589 // Field : PIO_SM3_CLKDIV_FRAC 1590 // Description : Fractional part of clock divider 1591 #define PIO_SM3_CLKDIV_FRAC_RESET 0x00 1592 #define PIO_SM3_CLKDIV_FRAC_BITS 0x0000ff00 1593 #define PIO_SM3_CLKDIV_FRAC_MSB 15 1594 #define PIO_SM3_CLKDIV_FRAC_LSB 8 1595 #define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" 1596 // ============================================================================= 1597 // Register : PIO_SM3_EXECCTRL 1598 // Description : Execution/behavioural settings for state machine 3 1599 #define PIO_SM3_EXECCTRL_OFFSET 0x00000114 1600 #define PIO_SM3_EXECCTRL_BITS 0xffffff9f 1601 #define PIO_SM3_EXECCTRL_RESET 0x0001f000 1602 // ----------------------------------------------------------------------------- 1603 // Field : PIO_SM3_EXECCTRL_EXEC_STALLED 1604 // Description : An instruction written to SMx_INSTR is stalled, and latched by 1605 // the 1606 // state machine. Will clear once the instruction completes. 1607 #define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET 0x0 1608 #define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS 0x80000000 1609 #define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB 31 1610 #define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB 31 1611 #define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" 1612 // ----------------------------------------------------------------------------- 1613 // Field : PIO_SM3_EXECCTRL_SIDE_EN 1614 // Description : If 1, the delay MSB is used as side-set enable, rather than a 1615 // side-set data bit. This allows instructions to perform side-set 1616 // optionally, 1617 // rather than on every instruction. 1618 #define PIO_SM3_EXECCTRL_SIDE_EN_RESET 0x0 1619 #define PIO_SM3_EXECCTRL_SIDE_EN_BITS 0x40000000 1620 #define PIO_SM3_EXECCTRL_SIDE_EN_MSB 30 1621 #define PIO_SM3_EXECCTRL_SIDE_EN_LSB 30 1622 #define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" 1623 // ----------------------------------------------------------------------------- 1624 // Field : PIO_SM3_EXECCTRL_SIDE_PINDIR 1625 // Description : Side-set data is asserted to pin OEs instead of pin values 1626 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET 0x0 1627 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 1628 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB 29 1629 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB 29 1630 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" 1631 // ----------------------------------------------------------------------------- 1632 // Field : PIO_SM3_EXECCTRL_JMP_PIN 1633 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by 1634 // input mapping. 1635 #define PIO_SM3_EXECCTRL_JMP_PIN_RESET 0x00 1636 #define PIO_SM3_EXECCTRL_JMP_PIN_BITS 0x1f000000 1637 #define PIO_SM3_EXECCTRL_JMP_PIN_MSB 28 1638 #define PIO_SM3_EXECCTRL_JMP_PIN_LSB 24 1639 #define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" 1640 // ----------------------------------------------------------------------------- 1641 // Field : PIO_SM3_EXECCTRL_OUT_EN_SEL 1642 // Description : Which data bit to use for inline OUT enable 1643 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET 0x00 1644 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 1645 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB 23 1646 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB 19 1647 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" 1648 // ----------------------------------------------------------------------------- 1649 // Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN 1650 // Description : If 1, use a bit of OUT data as an auxiliary write enable 1651 // When used in conjunction with OUT_STICKY, writes with an enable 1652 // of 0 will 1653 // deassert the latest pin write. This can create useful 1654 // masking/override behaviour 1655 // due to the priority ordering of state machine pin writes (SM0 < 1656 // SM1 < ...) 1657 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET 0x0 1658 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 1659 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB 18 1660 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB 18 1661 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" 1662 // ----------------------------------------------------------------------------- 1663 // Field : PIO_SM3_EXECCTRL_OUT_STICKY 1664 // Description : Continuously assert the most recent OUT/SET to the pins 1665 #define PIO_SM3_EXECCTRL_OUT_STICKY_RESET 0x0 1666 #define PIO_SM3_EXECCTRL_OUT_STICKY_BITS 0x00020000 1667 #define PIO_SM3_EXECCTRL_OUT_STICKY_MSB 17 1668 #define PIO_SM3_EXECCTRL_OUT_STICKY_LSB 17 1669 #define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" 1670 // ----------------------------------------------------------------------------- 1671 // Field : PIO_SM3_EXECCTRL_WRAP_TOP 1672 // Description : After reaching this address, execution is wrapped to 1673 // wrap_bottom. 1674 // If the instruction is a jump, and the jump condition is true, 1675 // the jump takes priority. 1676 #define PIO_SM3_EXECCTRL_WRAP_TOP_RESET 0x1f 1677 #define PIO_SM3_EXECCTRL_WRAP_TOP_BITS 0x0001f000 1678 #define PIO_SM3_EXECCTRL_WRAP_TOP_MSB 16 1679 #define PIO_SM3_EXECCTRL_WRAP_TOP_LSB 12 1680 #define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" 1681 // ----------------------------------------------------------------------------- 1682 // Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM 1683 // Description : After reaching wrap_top, execution is wrapped to this address. 1684 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET 0x00 1685 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 1686 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB 11 1687 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB 7 1688 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" 1689 // ----------------------------------------------------------------------------- 1690 // Field : PIO_SM3_EXECCTRL_STATUS_SEL 1691 // Description : Comparison used for the MOV x, STATUS instruction. 1692 // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes 1693 // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes 1694 #define PIO_SM3_EXECCTRL_STATUS_SEL_RESET 0x0 1695 #define PIO_SM3_EXECCTRL_STATUS_SEL_BITS 0x00000010 1696 #define PIO_SM3_EXECCTRL_STATUS_SEL_MSB 4 1697 #define PIO_SM3_EXECCTRL_STATUS_SEL_LSB 4 1698 #define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" 1699 #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 1700 #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 1701 // ----------------------------------------------------------------------------- 1702 // Field : PIO_SM3_EXECCTRL_STATUS_N 1703 // Description : Comparison level for the MOV x, STATUS instruction 1704 #define PIO_SM3_EXECCTRL_STATUS_N_RESET 0x0 1705 #define PIO_SM3_EXECCTRL_STATUS_N_BITS 0x0000000f 1706 #define PIO_SM3_EXECCTRL_STATUS_N_MSB 3 1707 #define PIO_SM3_EXECCTRL_STATUS_N_LSB 0 1708 #define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" 1709 // ============================================================================= 1710 // Register : PIO_SM3_SHIFTCTRL 1711 // Description : Control behaviour of the input/output shift registers for state 1712 // machine 3 1713 #define PIO_SM3_SHIFTCTRL_OFFSET 0x00000118 1714 #define PIO_SM3_SHIFTCTRL_BITS 0xffff0000 1715 #define PIO_SM3_SHIFTCTRL_RESET 0x000c0000 1716 // ----------------------------------------------------------------------------- 1717 // Field : PIO_SM3_SHIFTCTRL_FJOIN_RX 1718 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice 1719 // as deep. 1720 // TX FIFO is disabled as a result (always reads as both full and 1721 // empty). 1722 // FIFOs are flushed when this bit is changed. 1723 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET 0x0 1724 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 1725 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB 31 1726 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB 31 1727 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" 1728 // ----------------------------------------------------------------------------- 1729 // Field : PIO_SM3_SHIFTCTRL_FJOIN_TX 1730 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice 1731 // as deep. 1732 // RX FIFO is disabled as a result (always reads as both full and 1733 // empty). 1734 // FIFOs are flushed when this bit is changed. 1735 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET 0x0 1736 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 1737 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB 30 1738 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB 30 1739 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" 1740 // ----------------------------------------------------------------------------- 1741 // Field : PIO_SM3_SHIFTCTRL_PULL_THRESH 1742 // Description : Number of bits shifted out of TXSR before autopull or 1743 // conditional pull. 1744 // Write 0 for value of 32. 1745 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET 0x00 1746 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 1747 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB 29 1748 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB 25 1749 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" 1750 // ----------------------------------------------------------------------------- 1751 // Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH 1752 // Description : Number of bits shifted into RXSR before autopush or conditional 1753 // push. 1754 // Write 0 for value of 32. 1755 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET 0x00 1756 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 1757 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB 24 1758 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB 20 1759 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" 1760 // ----------------------------------------------------------------------------- 1761 // Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR 1762 // Description : 1 = shift out of output shift register to right. 0 = to left. 1763 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 1764 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 1765 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 1766 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 1767 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" 1768 // ----------------------------------------------------------------------------- 1769 // Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR 1770 // Description : 1 = shift input shift register to right (data enters from 1771 // left). 0 = to left. 1772 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 1773 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 1774 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB 18 1775 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB 18 1776 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" 1777 // ----------------------------------------------------------------------------- 1778 // Field : PIO_SM3_SHIFTCTRL_AUTOPULL 1779 // Description : Pull automatically when the output shift register is emptied 1780 #define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET 0x0 1781 #define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS 0x00020000 1782 #define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB 17 1783 #define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB 17 1784 #define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" 1785 // ----------------------------------------------------------------------------- 1786 // Field : PIO_SM3_SHIFTCTRL_AUTOPUSH 1787 // Description : Push automatically when the input shift register is filled 1788 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET 0x0 1789 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 1790 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB 16 1791 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB 16 1792 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" 1793 // ============================================================================= 1794 // Register : PIO_SM3_ADDR 1795 // Description : Current instruction address of state machine 3 1796 #define PIO_SM3_ADDR_OFFSET 0x0000011c 1797 #define PIO_SM3_ADDR_BITS 0x0000001f 1798 #define PIO_SM3_ADDR_RESET 0x00000000 1799 #define PIO_SM3_ADDR_MSB 4 1800 #define PIO_SM3_ADDR_LSB 0 1801 #define PIO_SM3_ADDR_ACCESS "RO" 1802 // ============================================================================= 1803 // Register : PIO_SM3_INSTR 1804 // Description : Instruction currently being executed by state machine 3 1805 // Write to execute an instruction immediately (including jumps) 1806 // and then resume execution. 1807 #define PIO_SM3_INSTR_OFFSET 0x00000120 1808 #define PIO_SM3_INSTR_BITS 0x0000ffff 1809 #define PIO_SM3_INSTR_RESET "-" 1810 #define PIO_SM3_INSTR_MSB 15 1811 #define PIO_SM3_INSTR_LSB 0 1812 #define PIO_SM3_INSTR_ACCESS "RW" 1813 // ============================================================================= 1814 // Register : PIO_SM3_PINCTRL 1815 // Description : State machine pin control 1816 #define PIO_SM3_PINCTRL_OFFSET 0x00000124 1817 #define PIO_SM3_PINCTRL_BITS 0xffffffff 1818 #define PIO_SM3_PINCTRL_RESET 0x14000000 1819 // ----------------------------------------------------------------------------- 1820 // Field : PIO_SM3_PINCTRL_SIDESET_COUNT 1821 // Description : The number of delay bits co-opted for side-set. Inclusive of 1822 // the enable bit, if present. 1823 #define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET 0x0 1824 #define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 1825 #define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB 31 1826 #define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB 29 1827 #define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" 1828 // ----------------------------------------------------------------------------- 1829 // Field : PIO_SM3_PINCTRL_SET_COUNT 1830 // Description : The number of pins asserted by a SET. Max of 5 1831 #define PIO_SM3_PINCTRL_SET_COUNT_RESET 0x5 1832 #define PIO_SM3_PINCTRL_SET_COUNT_BITS 0x1c000000 1833 #define PIO_SM3_PINCTRL_SET_COUNT_MSB 28 1834 #define PIO_SM3_PINCTRL_SET_COUNT_LSB 26 1835 #define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" 1836 // ----------------------------------------------------------------------------- 1837 // Field : PIO_SM3_PINCTRL_OUT_COUNT 1838 // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins 1839 #define PIO_SM3_PINCTRL_OUT_COUNT_RESET 0x00 1840 #define PIO_SM3_PINCTRL_OUT_COUNT_BITS 0x03f00000 1841 #define PIO_SM3_PINCTRL_OUT_COUNT_MSB 25 1842 #define PIO_SM3_PINCTRL_OUT_COUNT_LSB 20 1843 #define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" 1844 // ----------------------------------------------------------------------------- 1845 // Field : PIO_SM3_PINCTRL_IN_BASE 1846 // Description : The virtual pin corresponding to IN bit 0 1847 #define PIO_SM3_PINCTRL_IN_BASE_RESET 0x00 1848 #define PIO_SM3_PINCTRL_IN_BASE_BITS 0x000f8000 1849 #define PIO_SM3_PINCTRL_IN_BASE_MSB 19 1850 #define PIO_SM3_PINCTRL_IN_BASE_LSB 15 1851 #define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" 1852 // ----------------------------------------------------------------------------- 1853 // Field : PIO_SM3_PINCTRL_SIDESET_BASE 1854 // Description : The virtual pin corresponding to delay field bit 0 1855 #define PIO_SM3_PINCTRL_SIDESET_BASE_RESET 0x00 1856 #define PIO_SM3_PINCTRL_SIDESET_BASE_BITS 0x00007c00 1857 #define PIO_SM3_PINCTRL_SIDESET_BASE_MSB 14 1858 #define PIO_SM3_PINCTRL_SIDESET_BASE_LSB 10 1859 #define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" 1860 // ----------------------------------------------------------------------------- 1861 // Field : PIO_SM3_PINCTRL_SET_BASE 1862 // Description : The virtual pin corresponding to SET bit 0 1863 #define PIO_SM3_PINCTRL_SET_BASE_RESET 0x00 1864 #define PIO_SM3_PINCTRL_SET_BASE_BITS 0x000003e0 1865 #define PIO_SM3_PINCTRL_SET_BASE_MSB 9 1866 #define PIO_SM3_PINCTRL_SET_BASE_LSB 5 1867 #define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" 1868 // ----------------------------------------------------------------------------- 1869 // Field : PIO_SM3_PINCTRL_OUT_BASE 1870 // Description : The virtual pin corresponding to OUT bit 0 1871 #define PIO_SM3_PINCTRL_OUT_BASE_RESET 0x00 1872 #define PIO_SM3_PINCTRL_OUT_BASE_BITS 0x0000001f 1873 #define PIO_SM3_PINCTRL_OUT_BASE_MSB 4 1874 #define PIO_SM3_PINCTRL_OUT_BASE_LSB 0 1875 #define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" 1876 // ============================================================================= 1877 // Register : PIO_INTR 1878 // Description : Raw Interrupts 1879 #define PIO_INTR_OFFSET 0x00000128 1880 #define PIO_INTR_BITS 0x00000fff 1881 #define PIO_INTR_RESET 0x00000000 1882 // ----------------------------------------------------------------------------- 1883 // Field : PIO_INTR_SM3 1884 // Description : None 1885 #define PIO_INTR_SM3_RESET 0x0 1886 #define PIO_INTR_SM3_BITS 0x00000800 1887 #define PIO_INTR_SM3_MSB 11 1888 #define PIO_INTR_SM3_LSB 11 1889 #define PIO_INTR_SM3_ACCESS "RO" 1890 // ----------------------------------------------------------------------------- 1891 // Field : PIO_INTR_SM2 1892 // Description : None 1893 #define PIO_INTR_SM2_RESET 0x0 1894 #define PIO_INTR_SM2_BITS 0x00000400 1895 #define PIO_INTR_SM2_MSB 10 1896 #define PIO_INTR_SM2_LSB 10 1897 #define PIO_INTR_SM2_ACCESS "RO" 1898 // ----------------------------------------------------------------------------- 1899 // Field : PIO_INTR_SM1 1900 // Description : None 1901 #define PIO_INTR_SM1_RESET 0x0 1902 #define PIO_INTR_SM1_BITS 0x00000200 1903 #define PIO_INTR_SM1_MSB 9 1904 #define PIO_INTR_SM1_LSB 9 1905 #define PIO_INTR_SM1_ACCESS "RO" 1906 // ----------------------------------------------------------------------------- 1907 // Field : PIO_INTR_SM0 1908 // Description : None 1909 #define PIO_INTR_SM0_RESET 0x0 1910 #define PIO_INTR_SM0_BITS 0x00000100 1911 #define PIO_INTR_SM0_MSB 8 1912 #define PIO_INTR_SM0_LSB 8 1913 #define PIO_INTR_SM0_ACCESS "RO" 1914 // ----------------------------------------------------------------------------- 1915 // Field : PIO_INTR_SM3_TXNFULL 1916 // Description : None 1917 #define PIO_INTR_SM3_TXNFULL_RESET 0x0 1918 #define PIO_INTR_SM3_TXNFULL_BITS 0x00000080 1919 #define PIO_INTR_SM3_TXNFULL_MSB 7 1920 #define PIO_INTR_SM3_TXNFULL_LSB 7 1921 #define PIO_INTR_SM3_TXNFULL_ACCESS "RO" 1922 // ----------------------------------------------------------------------------- 1923 // Field : PIO_INTR_SM2_TXNFULL 1924 // Description : None 1925 #define PIO_INTR_SM2_TXNFULL_RESET 0x0 1926 #define PIO_INTR_SM2_TXNFULL_BITS 0x00000040 1927 #define PIO_INTR_SM2_TXNFULL_MSB 6 1928 #define PIO_INTR_SM2_TXNFULL_LSB 6 1929 #define PIO_INTR_SM2_TXNFULL_ACCESS "RO" 1930 // ----------------------------------------------------------------------------- 1931 // Field : PIO_INTR_SM1_TXNFULL 1932 // Description : None 1933 #define PIO_INTR_SM1_TXNFULL_RESET 0x0 1934 #define PIO_INTR_SM1_TXNFULL_BITS 0x00000020 1935 #define PIO_INTR_SM1_TXNFULL_MSB 5 1936 #define PIO_INTR_SM1_TXNFULL_LSB 5 1937 #define PIO_INTR_SM1_TXNFULL_ACCESS "RO" 1938 // ----------------------------------------------------------------------------- 1939 // Field : PIO_INTR_SM0_TXNFULL 1940 // Description : None 1941 #define PIO_INTR_SM0_TXNFULL_RESET 0x0 1942 #define PIO_INTR_SM0_TXNFULL_BITS 0x00000010 1943 #define PIO_INTR_SM0_TXNFULL_MSB 4 1944 #define PIO_INTR_SM0_TXNFULL_LSB 4 1945 #define PIO_INTR_SM0_TXNFULL_ACCESS "RO" 1946 // ----------------------------------------------------------------------------- 1947 // Field : PIO_INTR_SM3_RXNEMPTY 1948 // Description : None 1949 #define PIO_INTR_SM3_RXNEMPTY_RESET 0x0 1950 #define PIO_INTR_SM3_RXNEMPTY_BITS 0x00000008 1951 #define PIO_INTR_SM3_RXNEMPTY_MSB 3 1952 #define PIO_INTR_SM3_RXNEMPTY_LSB 3 1953 #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" 1954 // ----------------------------------------------------------------------------- 1955 // Field : PIO_INTR_SM2_RXNEMPTY 1956 // Description : None 1957 #define PIO_INTR_SM2_RXNEMPTY_RESET 0x0 1958 #define PIO_INTR_SM2_RXNEMPTY_BITS 0x00000004 1959 #define PIO_INTR_SM2_RXNEMPTY_MSB 2 1960 #define PIO_INTR_SM2_RXNEMPTY_LSB 2 1961 #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" 1962 // ----------------------------------------------------------------------------- 1963 // Field : PIO_INTR_SM1_RXNEMPTY 1964 // Description : None 1965 #define PIO_INTR_SM1_RXNEMPTY_RESET 0x0 1966 #define PIO_INTR_SM1_RXNEMPTY_BITS 0x00000002 1967 #define PIO_INTR_SM1_RXNEMPTY_MSB 1 1968 #define PIO_INTR_SM1_RXNEMPTY_LSB 1 1969 #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" 1970 // ----------------------------------------------------------------------------- 1971 // Field : PIO_INTR_SM0_RXNEMPTY 1972 // Description : None 1973 #define PIO_INTR_SM0_RXNEMPTY_RESET 0x0 1974 #define PIO_INTR_SM0_RXNEMPTY_BITS 0x00000001 1975 #define PIO_INTR_SM0_RXNEMPTY_MSB 0 1976 #define PIO_INTR_SM0_RXNEMPTY_LSB 0 1977 #define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" 1978 // ============================================================================= 1979 // Register : PIO_IRQ0_INTE 1980 // Description : Interrupt Enable for irq0 1981 #define PIO_IRQ0_INTE_OFFSET 0x0000012c 1982 #define PIO_IRQ0_INTE_BITS 0x00000fff 1983 #define PIO_IRQ0_INTE_RESET 0x00000000 1984 // ----------------------------------------------------------------------------- 1985 // Field : PIO_IRQ0_INTE_SM3 1986 // Description : None 1987 #define PIO_IRQ0_INTE_SM3_RESET 0x0 1988 #define PIO_IRQ0_INTE_SM3_BITS 0x00000800 1989 #define PIO_IRQ0_INTE_SM3_MSB 11 1990 #define PIO_IRQ0_INTE_SM3_LSB 11 1991 #define PIO_IRQ0_INTE_SM3_ACCESS "RW" 1992 // ----------------------------------------------------------------------------- 1993 // Field : PIO_IRQ0_INTE_SM2 1994 // Description : None 1995 #define PIO_IRQ0_INTE_SM2_RESET 0x0 1996 #define PIO_IRQ0_INTE_SM2_BITS 0x00000400 1997 #define PIO_IRQ0_INTE_SM2_MSB 10 1998 #define PIO_IRQ0_INTE_SM2_LSB 10 1999 #define PIO_IRQ0_INTE_SM2_ACCESS "RW" 2000 // ----------------------------------------------------------------------------- 2001 // Field : PIO_IRQ0_INTE_SM1 2002 // Description : None 2003 #define PIO_IRQ0_INTE_SM1_RESET 0x0 2004 #define PIO_IRQ0_INTE_SM1_BITS 0x00000200 2005 #define PIO_IRQ0_INTE_SM1_MSB 9 2006 #define PIO_IRQ0_INTE_SM1_LSB 9 2007 #define PIO_IRQ0_INTE_SM1_ACCESS "RW" 2008 // ----------------------------------------------------------------------------- 2009 // Field : PIO_IRQ0_INTE_SM0 2010 // Description : None 2011 #define PIO_IRQ0_INTE_SM0_RESET 0x0 2012 #define PIO_IRQ0_INTE_SM0_BITS 0x00000100 2013 #define PIO_IRQ0_INTE_SM0_MSB 8 2014 #define PIO_IRQ0_INTE_SM0_LSB 8 2015 #define PIO_IRQ0_INTE_SM0_ACCESS "RW" 2016 // ----------------------------------------------------------------------------- 2017 // Field : PIO_IRQ0_INTE_SM3_TXNFULL 2018 // Description : None 2019 #define PIO_IRQ0_INTE_SM3_TXNFULL_RESET 0x0 2020 #define PIO_IRQ0_INTE_SM3_TXNFULL_BITS 0x00000080 2021 #define PIO_IRQ0_INTE_SM3_TXNFULL_MSB 7 2022 #define PIO_IRQ0_INTE_SM3_TXNFULL_LSB 7 2023 #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" 2024 // ----------------------------------------------------------------------------- 2025 // Field : PIO_IRQ0_INTE_SM2_TXNFULL 2026 // Description : None 2027 #define PIO_IRQ0_INTE_SM2_TXNFULL_RESET 0x0 2028 #define PIO_IRQ0_INTE_SM2_TXNFULL_BITS 0x00000040 2029 #define PIO_IRQ0_INTE_SM2_TXNFULL_MSB 6 2030 #define PIO_IRQ0_INTE_SM2_TXNFULL_LSB 6 2031 #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" 2032 // ----------------------------------------------------------------------------- 2033 // Field : PIO_IRQ0_INTE_SM1_TXNFULL 2034 // Description : None 2035 #define PIO_IRQ0_INTE_SM1_TXNFULL_RESET 0x0 2036 #define PIO_IRQ0_INTE_SM1_TXNFULL_BITS 0x00000020 2037 #define PIO_IRQ0_INTE_SM1_TXNFULL_MSB 5 2038 #define PIO_IRQ0_INTE_SM1_TXNFULL_LSB 5 2039 #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" 2040 // ----------------------------------------------------------------------------- 2041 // Field : PIO_IRQ0_INTE_SM0_TXNFULL 2042 // Description : None 2043 #define PIO_IRQ0_INTE_SM0_TXNFULL_RESET 0x0 2044 #define PIO_IRQ0_INTE_SM0_TXNFULL_BITS 0x00000010 2045 #define PIO_IRQ0_INTE_SM0_TXNFULL_MSB 4 2046 #define PIO_IRQ0_INTE_SM0_TXNFULL_LSB 4 2047 #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" 2048 // ----------------------------------------------------------------------------- 2049 // Field : PIO_IRQ0_INTE_SM3_RXNEMPTY 2050 // Description : None 2051 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET 0x0 2052 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS 0x00000008 2053 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB 3 2054 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB 3 2055 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" 2056 // ----------------------------------------------------------------------------- 2057 // Field : PIO_IRQ0_INTE_SM2_RXNEMPTY 2058 // Description : None 2059 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET 0x0 2060 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS 0x00000004 2061 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB 2 2062 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB 2 2063 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" 2064 // ----------------------------------------------------------------------------- 2065 // Field : PIO_IRQ0_INTE_SM1_RXNEMPTY 2066 // Description : None 2067 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET 0x0 2068 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS 0x00000002 2069 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB 1 2070 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB 1 2071 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" 2072 // ----------------------------------------------------------------------------- 2073 // Field : PIO_IRQ0_INTE_SM0_RXNEMPTY 2074 // Description : None 2075 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET 0x0 2076 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS 0x00000001 2077 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB 0 2078 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB 0 2079 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" 2080 // ============================================================================= 2081 // Register : PIO_IRQ0_INTF 2082 // Description : Interrupt Force for irq0 2083 #define PIO_IRQ0_INTF_OFFSET 0x00000130 2084 #define PIO_IRQ0_INTF_BITS 0x00000fff 2085 #define PIO_IRQ0_INTF_RESET 0x00000000 2086 // ----------------------------------------------------------------------------- 2087 // Field : PIO_IRQ0_INTF_SM3 2088 // Description : None 2089 #define PIO_IRQ0_INTF_SM3_RESET 0x0 2090 #define PIO_IRQ0_INTF_SM3_BITS 0x00000800 2091 #define PIO_IRQ0_INTF_SM3_MSB 11 2092 #define PIO_IRQ0_INTF_SM3_LSB 11 2093 #define PIO_IRQ0_INTF_SM3_ACCESS "RW" 2094 // ----------------------------------------------------------------------------- 2095 // Field : PIO_IRQ0_INTF_SM2 2096 // Description : None 2097 #define PIO_IRQ0_INTF_SM2_RESET 0x0 2098 #define PIO_IRQ0_INTF_SM2_BITS 0x00000400 2099 #define PIO_IRQ0_INTF_SM2_MSB 10 2100 #define PIO_IRQ0_INTF_SM2_LSB 10 2101 #define PIO_IRQ0_INTF_SM2_ACCESS "RW" 2102 // ----------------------------------------------------------------------------- 2103 // Field : PIO_IRQ0_INTF_SM1 2104 // Description : None 2105 #define PIO_IRQ0_INTF_SM1_RESET 0x0 2106 #define PIO_IRQ0_INTF_SM1_BITS 0x00000200 2107 #define PIO_IRQ0_INTF_SM1_MSB 9 2108 #define PIO_IRQ0_INTF_SM1_LSB 9 2109 #define PIO_IRQ0_INTF_SM1_ACCESS "RW" 2110 // ----------------------------------------------------------------------------- 2111 // Field : PIO_IRQ0_INTF_SM0 2112 // Description : None 2113 #define PIO_IRQ0_INTF_SM0_RESET 0x0 2114 #define PIO_IRQ0_INTF_SM0_BITS 0x00000100 2115 #define PIO_IRQ0_INTF_SM0_MSB 8 2116 #define PIO_IRQ0_INTF_SM0_LSB 8 2117 #define PIO_IRQ0_INTF_SM0_ACCESS "RW" 2118 // ----------------------------------------------------------------------------- 2119 // Field : PIO_IRQ0_INTF_SM3_TXNFULL 2120 // Description : None 2121 #define PIO_IRQ0_INTF_SM3_TXNFULL_RESET 0x0 2122 #define PIO_IRQ0_INTF_SM3_TXNFULL_BITS 0x00000080 2123 #define PIO_IRQ0_INTF_SM3_TXNFULL_MSB 7 2124 #define PIO_IRQ0_INTF_SM3_TXNFULL_LSB 7 2125 #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" 2126 // ----------------------------------------------------------------------------- 2127 // Field : PIO_IRQ0_INTF_SM2_TXNFULL 2128 // Description : None 2129 #define PIO_IRQ0_INTF_SM2_TXNFULL_RESET 0x0 2130 #define PIO_IRQ0_INTF_SM2_TXNFULL_BITS 0x00000040 2131 #define PIO_IRQ0_INTF_SM2_TXNFULL_MSB 6 2132 #define PIO_IRQ0_INTF_SM2_TXNFULL_LSB 6 2133 #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" 2134 // ----------------------------------------------------------------------------- 2135 // Field : PIO_IRQ0_INTF_SM1_TXNFULL 2136 // Description : None 2137 #define PIO_IRQ0_INTF_SM1_TXNFULL_RESET 0x0 2138 #define PIO_IRQ0_INTF_SM1_TXNFULL_BITS 0x00000020 2139 #define PIO_IRQ0_INTF_SM1_TXNFULL_MSB 5 2140 #define PIO_IRQ0_INTF_SM1_TXNFULL_LSB 5 2141 #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" 2142 // ----------------------------------------------------------------------------- 2143 // Field : PIO_IRQ0_INTF_SM0_TXNFULL 2144 // Description : None 2145 #define PIO_IRQ0_INTF_SM0_TXNFULL_RESET 0x0 2146 #define PIO_IRQ0_INTF_SM0_TXNFULL_BITS 0x00000010 2147 #define PIO_IRQ0_INTF_SM0_TXNFULL_MSB 4 2148 #define PIO_IRQ0_INTF_SM0_TXNFULL_LSB 4 2149 #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" 2150 // ----------------------------------------------------------------------------- 2151 // Field : PIO_IRQ0_INTF_SM3_RXNEMPTY 2152 // Description : None 2153 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET 0x0 2154 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS 0x00000008 2155 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB 3 2156 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB 3 2157 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" 2158 // ----------------------------------------------------------------------------- 2159 // Field : PIO_IRQ0_INTF_SM2_RXNEMPTY 2160 // Description : None 2161 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET 0x0 2162 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS 0x00000004 2163 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB 2 2164 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB 2 2165 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" 2166 // ----------------------------------------------------------------------------- 2167 // Field : PIO_IRQ0_INTF_SM1_RXNEMPTY 2168 // Description : None 2169 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET 0x0 2170 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS 0x00000002 2171 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB 1 2172 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB 1 2173 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" 2174 // ----------------------------------------------------------------------------- 2175 // Field : PIO_IRQ0_INTF_SM0_RXNEMPTY 2176 // Description : None 2177 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET 0x0 2178 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS 0x00000001 2179 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB 0 2180 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB 0 2181 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" 2182 // ============================================================================= 2183 // Register : PIO_IRQ0_INTS 2184 // Description : Interrupt status after masking & forcing for irq0 2185 #define PIO_IRQ0_INTS_OFFSET 0x00000134 2186 #define PIO_IRQ0_INTS_BITS 0x00000fff 2187 #define PIO_IRQ0_INTS_RESET 0x00000000 2188 // ----------------------------------------------------------------------------- 2189 // Field : PIO_IRQ0_INTS_SM3 2190 // Description : None 2191 #define PIO_IRQ0_INTS_SM3_RESET 0x0 2192 #define PIO_IRQ0_INTS_SM3_BITS 0x00000800 2193 #define PIO_IRQ0_INTS_SM3_MSB 11 2194 #define PIO_IRQ0_INTS_SM3_LSB 11 2195 #define PIO_IRQ0_INTS_SM3_ACCESS "RO" 2196 // ----------------------------------------------------------------------------- 2197 // Field : PIO_IRQ0_INTS_SM2 2198 // Description : None 2199 #define PIO_IRQ0_INTS_SM2_RESET 0x0 2200 #define PIO_IRQ0_INTS_SM2_BITS 0x00000400 2201 #define PIO_IRQ0_INTS_SM2_MSB 10 2202 #define PIO_IRQ0_INTS_SM2_LSB 10 2203 #define PIO_IRQ0_INTS_SM2_ACCESS "RO" 2204 // ----------------------------------------------------------------------------- 2205 // Field : PIO_IRQ0_INTS_SM1 2206 // Description : None 2207 #define PIO_IRQ0_INTS_SM1_RESET 0x0 2208 #define PIO_IRQ0_INTS_SM1_BITS 0x00000200 2209 #define PIO_IRQ0_INTS_SM1_MSB 9 2210 #define PIO_IRQ0_INTS_SM1_LSB 9 2211 #define PIO_IRQ0_INTS_SM1_ACCESS "RO" 2212 // ----------------------------------------------------------------------------- 2213 // Field : PIO_IRQ0_INTS_SM0 2214 // Description : None 2215 #define PIO_IRQ0_INTS_SM0_RESET 0x0 2216 #define PIO_IRQ0_INTS_SM0_BITS 0x00000100 2217 #define PIO_IRQ0_INTS_SM0_MSB 8 2218 #define PIO_IRQ0_INTS_SM0_LSB 8 2219 #define PIO_IRQ0_INTS_SM0_ACCESS "RO" 2220 // ----------------------------------------------------------------------------- 2221 // Field : PIO_IRQ0_INTS_SM3_TXNFULL 2222 // Description : None 2223 #define PIO_IRQ0_INTS_SM3_TXNFULL_RESET 0x0 2224 #define PIO_IRQ0_INTS_SM3_TXNFULL_BITS 0x00000080 2225 #define PIO_IRQ0_INTS_SM3_TXNFULL_MSB 7 2226 #define PIO_IRQ0_INTS_SM3_TXNFULL_LSB 7 2227 #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" 2228 // ----------------------------------------------------------------------------- 2229 // Field : PIO_IRQ0_INTS_SM2_TXNFULL 2230 // Description : None 2231 #define PIO_IRQ0_INTS_SM2_TXNFULL_RESET 0x0 2232 #define PIO_IRQ0_INTS_SM2_TXNFULL_BITS 0x00000040 2233 #define PIO_IRQ0_INTS_SM2_TXNFULL_MSB 6 2234 #define PIO_IRQ0_INTS_SM2_TXNFULL_LSB 6 2235 #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" 2236 // ----------------------------------------------------------------------------- 2237 // Field : PIO_IRQ0_INTS_SM1_TXNFULL 2238 // Description : None 2239 #define PIO_IRQ0_INTS_SM1_TXNFULL_RESET 0x0 2240 #define PIO_IRQ0_INTS_SM1_TXNFULL_BITS 0x00000020 2241 #define PIO_IRQ0_INTS_SM1_TXNFULL_MSB 5 2242 #define PIO_IRQ0_INTS_SM1_TXNFULL_LSB 5 2243 #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" 2244 // ----------------------------------------------------------------------------- 2245 // Field : PIO_IRQ0_INTS_SM0_TXNFULL 2246 // Description : None 2247 #define PIO_IRQ0_INTS_SM0_TXNFULL_RESET 0x0 2248 #define PIO_IRQ0_INTS_SM0_TXNFULL_BITS 0x00000010 2249 #define PIO_IRQ0_INTS_SM0_TXNFULL_MSB 4 2250 #define PIO_IRQ0_INTS_SM0_TXNFULL_LSB 4 2251 #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" 2252 // ----------------------------------------------------------------------------- 2253 // Field : PIO_IRQ0_INTS_SM3_RXNEMPTY 2254 // Description : None 2255 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET 0x0 2256 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS 0x00000008 2257 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB 3 2258 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB 3 2259 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" 2260 // ----------------------------------------------------------------------------- 2261 // Field : PIO_IRQ0_INTS_SM2_RXNEMPTY 2262 // Description : None 2263 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET 0x0 2264 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS 0x00000004 2265 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB 2 2266 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB 2 2267 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" 2268 // ----------------------------------------------------------------------------- 2269 // Field : PIO_IRQ0_INTS_SM1_RXNEMPTY 2270 // Description : None 2271 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET 0x0 2272 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS 0x00000002 2273 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB 1 2274 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB 1 2275 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" 2276 // ----------------------------------------------------------------------------- 2277 // Field : PIO_IRQ0_INTS_SM0_RXNEMPTY 2278 // Description : None 2279 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET 0x0 2280 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS 0x00000001 2281 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB 0 2282 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB 0 2283 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" 2284 // ============================================================================= 2285 // Register : PIO_IRQ1_INTE 2286 // Description : Interrupt Enable for irq1 2287 #define PIO_IRQ1_INTE_OFFSET 0x00000138 2288 #define PIO_IRQ1_INTE_BITS 0x00000fff 2289 #define PIO_IRQ1_INTE_RESET 0x00000000 2290 // ----------------------------------------------------------------------------- 2291 // Field : PIO_IRQ1_INTE_SM3 2292 // Description : None 2293 #define PIO_IRQ1_INTE_SM3_RESET 0x0 2294 #define PIO_IRQ1_INTE_SM3_BITS 0x00000800 2295 #define PIO_IRQ1_INTE_SM3_MSB 11 2296 #define PIO_IRQ1_INTE_SM3_LSB 11 2297 #define PIO_IRQ1_INTE_SM3_ACCESS "RW" 2298 // ----------------------------------------------------------------------------- 2299 // Field : PIO_IRQ1_INTE_SM2 2300 // Description : None 2301 #define PIO_IRQ1_INTE_SM2_RESET 0x0 2302 #define PIO_IRQ1_INTE_SM2_BITS 0x00000400 2303 #define PIO_IRQ1_INTE_SM2_MSB 10 2304 #define PIO_IRQ1_INTE_SM2_LSB 10 2305 #define PIO_IRQ1_INTE_SM2_ACCESS "RW" 2306 // ----------------------------------------------------------------------------- 2307 // Field : PIO_IRQ1_INTE_SM1 2308 // Description : None 2309 #define PIO_IRQ1_INTE_SM1_RESET 0x0 2310 #define PIO_IRQ1_INTE_SM1_BITS 0x00000200 2311 #define PIO_IRQ1_INTE_SM1_MSB 9 2312 #define PIO_IRQ1_INTE_SM1_LSB 9 2313 #define PIO_IRQ1_INTE_SM1_ACCESS "RW" 2314 // ----------------------------------------------------------------------------- 2315 // Field : PIO_IRQ1_INTE_SM0 2316 // Description : None 2317 #define PIO_IRQ1_INTE_SM0_RESET 0x0 2318 #define PIO_IRQ1_INTE_SM0_BITS 0x00000100 2319 #define PIO_IRQ1_INTE_SM0_MSB 8 2320 #define PIO_IRQ1_INTE_SM0_LSB 8 2321 #define PIO_IRQ1_INTE_SM0_ACCESS "RW" 2322 // ----------------------------------------------------------------------------- 2323 // Field : PIO_IRQ1_INTE_SM3_TXNFULL 2324 // Description : None 2325 #define PIO_IRQ1_INTE_SM3_TXNFULL_RESET 0x0 2326 #define PIO_IRQ1_INTE_SM3_TXNFULL_BITS 0x00000080 2327 #define PIO_IRQ1_INTE_SM3_TXNFULL_MSB 7 2328 #define PIO_IRQ1_INTE_SM3_TXNFULL_LSB 7 2329 #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" 2330 // ----------------------------------------------------------------------------- 2331 // Field : PIO_IRQ1_INTE_SM2_TXNFULL 2332 // Description : None 2333 #define PIO_IRQ1_INTE_SM2_TXNFULL_RESET 0x0 2334 #define PIO_IRQ1_INTE_SM2_TXNFULL_BITS 0x00000040 2335 #define PIO_IRQ1_INTE_SM2_TXNFULL_MSB 6 2336 #define PIO_IRQ1_INTE_SM2_TXNFULL_LSB 6 2337 #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" 2338 // ----------------------------------------------------------------------------- 2339 // Field : PIO_IRQ1_INTE_SM1_TXNFULL 2340 // Description : None 2341 #define PIO_IRQ1_INTE_SM1_TXNFULL_RESET 0x0 2342 #define PIO_IRQ1_INTE_SM1_TXNFULL_BITS 0x00000020 2343 #define PIO_IRQ1_INTE_SM1_TXNFULL_MSB 5 2344 #define PIO_IRQ1_INTE_SM1_TXNFULL_LSB 5 2345 #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" 2346 // ----------------------------------------------------------------------------- 2347 // Field : PIO_IRQ1_INTE_SM0_TXNFULL 2348 // Description : None 2349 #define PIO_IRQ1_INTE_SM0_TXNFULL_RESET 0x0 2350 #define PIO_IRQ1_INTE_SM0_TXNFULL_BITS 0x00000010 2351 #define PIO_IRQ1_INTE_SM0_TXNFULL_MSB 4 2352 #define PIO_IRQ1_INTE_SM0_TXNFULL_LSB 4 2353 #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" 2354 // ----------------------------------------------------------------------------- 2355 // Field : PIO_IRQ1_INTE_SM3_RXNEMPTY 2356 // Description : None 2357 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET 0x0 2358 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS 0x00000008 2359 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB 3 2360 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB 3 2361 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" 2362 // ----------------------------------------------------------------------------- 2363 // Field : PIO_IRQ1_INTE_SM2_RXNEMPTY 2364 // Description : None 2365 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET 0x0 2366 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS 0x00000004 2367 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB 2 2368 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB 2 2369 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" 2370 // ----------------------------------------------------------------------------- 2371 // Field : PIO_IRQ1_INTE_SM1_RXNEMPTY 2372 // Description : None 2373 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET 0x0 2374 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS 0x00000002 2375 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB 1 2376 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB 1 2377 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" 2378 // ----------------------------------------------------------------------------- 2379 // Field : PIO_IRQ1_INTE_SM0_RXNEMPTY 2380 // Description : None 2381 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET 0x0 2382 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS 0x00000001 2383 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB 0 2384 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB 0 2385 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" 2386 // ============================================================================= 2387 // Register : PIO_IRQ1_INTF 2388 // Description : Interrupt Force for irq1 2389 #define PIO_IRQ1_INTF_OFFSET 0x0000013c 2390 #define PIO_IRQ1_INTF_BITS 0x00000fff 2391 #define PIO_IRQ1_INTF_RESET 0x00000000 2392 // ----------------------------------------------------------------------------- 2393 // Field : PIO_IRQ1_INTF_SM3 2394 // Description : None 2395 #define PIO_IRQ1_INTF_SM3_RESET 0x0 2396 #define PIO_IRQ1_INTF_SM3_BITS 0x00000800 2397 #define PIO_IRQ1_INTF_SM3_MSB 11 2398 #define PIO_IRQ1_INTF_SM3_LSB 11 2399 #define PIO_IRQ1_INTF_SM3_ACCESS "RW" 2400 // ----------------------------------------------------------------------------- 2401 // Field : PIO_IRQ1_INTF_SM2 2402 // Description : None 2403 #define PIO_IRQ1_INTF_SM2_RESET 0x0 2404 #define PIO_IRQ1_INTF_SM2_BITS 0x00000400 2405 #define PIO_IRQ1_INTF_SM2_MSB 10 2406 #define PIO_IRQ1_INTF_SM2_LSB 10 2407 #define PIO_IRQ1_INTF_SM2_ACCESS "RW" 2408 // ----------------------------------------------------------------------------- 2409 // Field : PIO_IRQ1_INTF_SM1 2410 // Description : None 2411 #define PIO_IRQ1_INTF_SM1_RESET 0x0 2412 #define PIO_IRQ1_INTF_SM1_BITS 0x00000200 2413 #define PIO_IRQ1_INTF_SM1_MSB 9 2414 #define PIO_IRQ1_INTF_SM1_LSB 9 2415 #define PIO_IRQ1_INTF_SM1_ACCESS "RW" 2416 // ----------------------------------------------------------------------------- 2417 // Field : PIO_IRQ1_INTF_SM0 2418 // Description : None 2419 #define PIO_IRQ1_INTF_SM0_RESET 0x0 2420 #define PIO_IRQ1_INTF_SM0_BITS 0x00000100 2421 #define PIO_IRQ1_INTF_SM0_MSB 8 2422 #define PIO_IRQ1_INTF_SM0_LSB 8 2423 #define PIO_IRQ1_INTF_SM0_ACCESS "RW" 2424 // ----------------------------------------------------------------------------- 2425 // Field : PIO_IRQ1_INTF_SM3_TXNFULL 2426 // Description : None 2427 #define PIO_IRQ1_INTF_SM3_TXNFULL_RESET 0x0 2428 #define PIO_IRQ1_INTF_SM3_TXNFULL_BITS 0x00000080 2429 #define PIO_IRQ1_INTF_SM3_TXNFULL_MSB 7 2430 #define PIO_IRQ1_INTF_SM3_TXNFULL_LSB 7 2431 #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" 2432 // ----------------------------------------------------------------------------- 2433 // Field : PIO_IRQ1_INTF_SM2_TXNFULL 2434 // Description : None 2435 #define PIO_IRQ1_INTF_SM2_TXNFULL_RESET 0x0 2436 #define PIO_IRQ1_INTF_SM2_TXNFULL_BITS 0x00000040 2437 #define PIO_IRQ1_INTF_SM2_TXNFULL_MSB 6 2438 #define PIO_IRQ1_INTF_SM2_TXNFULL_LSB 6 2439 #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" 2440 // ----------------------------------------------------------------------------- 2441 // Field : PIO_IRQ1_INTF_SM1_TXNFULL 2442 // Description : None 2443 #define PIO_IRQ1_INTF_SM1_TXNFULL_RESET 0x0 2444 #define PIO_IRQ1_INTF_SM1_TXNFULL_BITS 0x00000020 2445 #define PIO_IRQ1_INTF_SM1_TXNFULL_MSB 5 2446 #define PIO_IRQ1_INTF_SM1_TXNFULL_LSB 5 2447 #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" 2448 // ----------------------------------------------------------------------------- 2449 // Field : PIO_IRQ1_INTF_SM0_TXNFULL 2450 // Description : None 2451 #define PIO_IRQ1_INTF_SM0_TXNFULL_RESET 0x0 2452 #define PIO_IRQ1_INTF_SM0_TXNFULL_BITS 0x00000010 2453 #define PIO_IRQ1_INTF_SM0_TXNFULL_MSB 4 2454 #define PIO_IRQ1_INTF_SM0_TXNFULL_LSB 4 2455 #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" 2456 // ----------------------------------------------------------------------------- 2457 // Field : PIO_IRQ1_INTF_SM3_RXNEMPTY 2458 // Description : None 2459 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET 0x0 2460 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS 0x00000008 2461 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB 3 2462 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB 3 2463 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" 2464 // ----------------------------------------------------------------------------- 2465 // Field : PIO_IRQ1_INTF_SM2_RXNEMPTY 2466 // Description : None 2467 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET 0x0 2468 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS 0x00000004 2469 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB 2 2470 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB 2 2471 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" 2472 // ----------------------------------------------------------------------------- 2473 // Field : PIO_IRQ1_INTF_SM1_RXNEMPTY 2474 // Description : None 2475 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET 0x0 2476 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS 0x00000002 2477 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB 1 2478 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB 1 2479 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" 2480 // ----------------------------------------------------------------------------- 2481 // Field : PIO_IRQ1_INTF_SM0_RXNEMPTY 2482 // Description : None 2483 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET 0x0 2484 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS 0x00000001 2485 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB 0 2486 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB 0 2487 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" 2488 // ============================================================================= 2489 // Register : PIO_IRQ1_INTS 2490 // Description : Interrupt status after masking & forcing for irq1 2491 #define PIO_IRQ1_INTS_OFFSET 0x00000140 2492 #define PIO_IRQ1_INTS_BITS 0x00000fff 2493 #define PIO_IRQ1_INTS_RESET 0x00000000 2494 // ----------------------------------------------------------------------------- 2495 // Field : PIO_IRQ1_INTS_SM3 2496 // Description : None 2497 #define PIO_IRQ1_INTS_SM3_RESET 0x0 2498 #define PIO_IRQ1_INTS_SM3_BITS 0x00000800 2499 #define PIO_IRQ1_INTS_SM3_MSB 11 2500 #define PIO_IRQ1_INTS_SM3_LSB 11 2501 #define PIO_IRQ1_INTS_SM3_ACCESS "RO" 2502 // ----------------------------------------------------------------------------- 2503 // Field : PIO_IRQ1_INTS_SM2 2504 // Description : None 2505 #define PIO_IRQ1_INTS_SM2_RESET 0x0 2506 #define PIO_IRQ1_INTS_SM2_BITS 0x00000400 2507 #define PIO_IRQ1_INTS_SM2_MSB 10 2508 #define PIO_IRQ1_INTS_SM2_LSB 10 2509 #define PIO_IRQ1_INTS_SM2_ACCESS "RO" 2510 // ----------------------------------------------------------------------------- 2511 // Field : PIO_IRQ1_INTS_SM1 2512 // Description : None 2513 #define PIO_IRQ1_INTS_SM1_RESET 0x0 2514 #define PIO_IRQ1_INTS_SM1_BITS 0x00000200 2515 #define PIO_IRQ1_INTS_SM1_MSB 9 2516 #define PIO_IRQ1_INTS_SM1_LSB 9 2517 #define PIO_IRQ1_INTS_SM1_ACCESS "RO" 2518 // ----------------------------------------------------------------------------- 2519 // Field : PIO_IRQ1_INTS_SM0 2520 // Description : None 2521 #define PIO_IRQ1_INTS_SM0_RESET 0x0 2522 #define PIO_IRQ1_INTS_SM0_BITS 0x00000100 2523 #define PIO_IRQ1_INTS_SM0_MSB 8 2524 #define PIO_IRQ1_INTS_SM0_LSB 8 2525 #define PIO_IRQ1_INTS_SM0_ACCESS "RO" 2526 // ----------------------------------------------------------------------------- 2527 // Field : PIO_IRQ1_INTS_SM3_TXNFULL 2528 // Description : None 2529 #define PIO_IRQ1_INTS_SM3_TXNFULL_RESET 0x0 2530 #define PIO_IRQ1_INTS_SM3_TXNFULL_BITS 0x00000080 2531 #define PIO_IRQ1_INTS_SM3_TXNFULL_MSB 7 2532 #define PIO_IRQ1_INTS_SM3_TXNFULL_LSB 7 2533 #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" 2534 // ----------------------------------------------------------------------------- 2535 // Field : PIO_IRQ1_INTS_SM2_TXNFULL 2536 // Description : None 2537 #define PIO_IRQ1_INTS_SM2_TXNFULL_RESET 0x0 2538 #define PIO_IRQ1_INTS_SM2_TXNFULL_BITS 0x00000040 2539 #define PIO_IRQ1_INTS_SM2_TXNFULL_MSB 6 2540 #define PIO_IRQ1_INTS_SM2_TXNFULL_LSB 6 2541 #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" 2542 // ----------------------------------------------------------------------------- 2543 // Field : PIO_IRQ1_INTS_SM1_TXNFULL 2544 // Description : None 2545 #define PIO_IRQ1_INTS_SM1_TXNFULL_RESET 0x0 2546 #define PIO_IRQ1_INTS_SM1_TXNFULL_BITS 0x00000020 2547 #define PIO_IRQ1_INTS_SM1_TXNFULL_MSB 5 2548 #define PIO_IRQ1_INTS_SM1_TXNFULL_LSB 5 2549 #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" 2550 // ----------------------------------------------------------------------------- 2551 // Field : PIO_IRQ1_INTS_SM0_TXNFULL 2552 // Description : None 2553 #define PIO_IRQ1_INTS_SM0_TXNFULL_RESET 0x0 2554 #define PIO_IRQ1_INTS_SM0_TXNFULL_BITS 0x00000010 2555 #define PIO_IRQ1_INTS_SM0_TXNFULL_MSB 4 2556 #define PIO_IRQ1_INTS_SM0_TXNFULL_LSB 4 2557 #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" 2558 // ----------------------------------------------------------------------------- 2559 // Field : PIO_IRQ1_INTS_SM3_RXNEMPTY 2560 // Description : None 2561 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET 0x0 2562 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS 0x00000008 2563 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB 3 2564 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB 3 2565 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" 2566 // ----------------------------------------------------------------------------- 2567 // Field : PIO_IRQ1_INTS_SM2_RXNEMPTY 2568 // Description : None 2569 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET 0x0 2570 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS 0x00000004 2571 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB 2 2572 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB 2 2573 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" 2574 // ----------------------------------------------------------------------------- 2575 // Field : PIO_IRQ1_INTS_SM1_RXNEMPTY 2576 // Description : None 2577 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET 0x0 2578 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS 0x00000002 2579 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB 1 2580 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB 1 2581 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" 2582 // ----------------------------------------------------------------------------- 2583 // Field : PIO_IRQ1_INTS_SM0_RXNEMPTY 2584 // Description : None 2585 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET 0x0 2586 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS 0x00000001 2587 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB 0 2588 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB 0 2589 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" 2590 // ============================================================================= 2591 #endif // HARDWARE_REGS_PIO_DEFINED 2592