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Searched refs:PLIC_ENABLE (Results 1 – 2 of 2) sorted by relevance

/lk-master/platform/qemu-virt-riscv/
A Dplic.c25 #define PLIC_ENABLE(irq, hart) (PLIC_BASE_VIRT + 0x2000 + (0x80 * PLIC_HART_IDX(hart)) + (4 * … macro
39 *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32)); in plic_early_init()
51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()
/lk-master/platform/sifive/
A Dplic.c26 #define PLIC_ENABLE(irq, hart) (PLIC_BASE + 0x2000 + (0x80 * PLIC_HART_IDX(hart)) + (4 * ((irq… macro
39 *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32)); in plic_early_init()
51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()

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