1 /* 2 * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.Redistribution and use in so 3 * urce and binary forms, with or withoutmodification, are permitted provided that the following condit 4 * ions are met:1. Redistributions of source code must retain the above copyright notice, this list of 5 * conditions and the following disclaimer.2. Redistributions in binary form must reproduce the above c 6 * opyright notice, this list of conditions and the following disclaimer in the documentation and/or ot 7 * her materials provided with the distribution.3. Neither the name of Nordic Semiconductor ASA nor the 8 * names of its contributors may be used to endorse or promote products derived from this software wit 9 * hout specific prior written permission.THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRI 10 * BUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THEIMPLIED WARRA 11 * NTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEARE DISCLAIMED. IN NO EVENT SHALL NORD 12 * IC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLA 13 * RY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OFSUBSTITUTE GOODS OR SERVIC 14 * ES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIAB 15 * ILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN A 16 * NY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF SUCH DAMAGE. 17 * 18 * @file nrf5340_network.h 19 * @brief CMSIS HeaderFile 20 * @version 1 21 * @date 14. August 2020 22 * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:14 23 * from File 'nrf5340_network.svd', 24 * last modified on Friday, 14.08.2020 13:02:07 25 */ 26 27 28 29 /** @addtogroup Nordic Semiconductor 30 * @{ 31 */ 32 33 34 /** @addtogroup nrf5340_network 35 * @{ 36 */ 37 38 39 #ifndef NRF5340_NETWORK_H 40 #define NRF5340_NETWORK_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 47 /** @addtogroup Configuration_of_CMSIS 48 * @{ 49 */ 50 51 52 53 /* =========================================================================================================================== */ 54 /* ================ Interrupt Number Definition ================ */ 55 /* =========================================================================================================================== */ 56 57 typedef enum { 58 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 59 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 60 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 61 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 62 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 63 and No Match */ 64 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 65 related Fault */ 66 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 67 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 68 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 69 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 70 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 71 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 72 /* ====================================== nrf5340_network Specific Interrupt Numbers ======================================= */ 73 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 74 RADIO_IRQn = 8, /*!< 8 RADIO */ 75 RNG_IRQn = 9, /*!< 9 RNG */ 76 GPIOTE_IRQn = 10, /*!< 10 GPIOTE */ 77 WDT_IRQn = 11, /*!< 11 WDT */ 78 TIMER0_IRQn = 12, /*!< 12 TIMER0 */ 79 ECB_IRQn = 13, /*!< 13 ECB */ 80 AAR_CCM_IRQn = 14, /*!< 14 AAR_CCM */ 81 TEMP_IRQn = 16, /*!< 16 TEMP */ 82 RTC0_IRQn = 17, /*!< 17 RTC0 */ 83 IPC_IRQn = 18, /*!< 18 IPC */ 84 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 19, /*!< 19 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ 85 EGU0_IRQn = 20, /*!< 20 EGU0 */ 86 RTC1_IRQn = 22, /*!< 22 RTC1 */ 87 TIMER1_IRQn = 24, /*!< 24 TIMER1 */ 88 TIMER2_IRQn = 25, /*!< 25 TIMER2 */ 89 SWI0_IRQn = 26, /*!< 26 SWI0 */ 90 SWI1_IRQn = 27, /*!< 27 SWI1 */ 91 SWI2_IRQn = 28, /*!< 28 SWI2 */ 92 SWI3_IRQn = 29 /*!< 29 SWI3 */ 93 } IRQn_Type; 94 95 96 97 /* =========================================================================================================================== */ 98 /* ================ Processor and Core Peripheral Section ================ */ 99 /* =========================================================================================================================== */ 100 101 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 102 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 103 #define __DSP_PRESENT 0 /*!< DSP present or not */ 104 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 106 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 107 #define __MPU_PRESENT 1 /*!< MPU present */ 108 #define __FPU_PRESENT 0 /*!< FPU present */ 109 #define __FPU_DP 0 /*!< unused, Device has no FPU */ 110 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 111 112 113 /** @} */ /* End of group Configuration_of_CMSIS */ 114 115 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 116 #include "system_nrf5340_network.h" /*!< nrf5340_network System */ 117 118 #ifndef __IM /*!< Fallback for older CMSIS versions */ 119 #define __IM __I 120 #endif 121 #ifndef __OM /*!< Fallback for older CMSIS versions */ 122 #define __OM __O 123 #endif 124 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 125 #define __IOM __IO 126 #endif 127 128 129 /* =========================================================================================================================== */ 130 /* ================ Device Specific Cluster Section ================ */ 131 /* =========================================================================================================================== */ 132 133 134 /** @addtogroup Device_Peripheral_clusters 135 * @{ 136 */ 137 138 139 /** 140 * @brief FICR_INFO [INFO] (Device info) 141 */ 142 typedef struct { 143 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 144 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 145 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 146 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 147 configuration */ 148 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 149 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 150 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 151 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 152 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 153 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 154 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 155 156 157 /** 158 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 159 */ 160 typedef struct { 161 __IOM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 162 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 163 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 164 165 166 /** 167 * @brief VREQCTRL_VREGRADIO [VREGRADIO] (Unspecified) 168 */ 169 typedef struct { 170 __IOM uint32_t VREQH; /*!< (@ 0x00000000) Request high voltage on RADIO After requesting 171 high voltage, the user must wait until VREQHREADY 172 is set to Ready */ 173 __IM uint32_t RESERVED; 174 __IM uint32_t VREQHREADY; /*!< (@ 0x00000008) High voltage on RADIO is ready */ 175 } VREQCTRL_VREGRADIO_Type; /*!< Size = 12 (0xc) */ 176 177 178 /** 179 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 180 */ 181 typedef struct { 182 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 183 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 184 data sent from the debugger to the CPU has 185 been read. */ 186 __IM uint32_t RESERVED[30]; 187 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 188 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 189 the data sent from the CPU to the debugger 190 has been read. */ 191 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 192 193 194 /** 195 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 196 */ 197 typedef struct { 198 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 199 register from being written until next reset. */ 200 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 201 and performs an ERASEALL operation. */ 202 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 203 204 205 /** 206 * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) 207 */ 208 typedef struct { 209 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register 210 from being written to until next reset. */ 211 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register 212 and enables debug access to non-secure mode. */ 213 } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ 214 215 216 /** 217 * @brief RADIO_PSEL [PSEL] (Unspecified) 218 */ 219 typedef struct { 220 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 221 n */ 222 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 223 224 225 /** 226 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 227 */ 228 typedef struct { 229 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 230 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 231 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 232 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 233 234 235 /** 236 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 237 */ 238 typedef struct { 239 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 240 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 241 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 242 243 244 /** 245 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 246 */ 247 typedef struct { 248 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 249 for task CHG[n].EN */ 250 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 251 for task CHG[n].DIS */ 252 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 253 254 255 /** 256 * @brief SPIM_PSEL [PSEL] (Unspecified) 257 */ 258 typedef struct { 259 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 260 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 261 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 262 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 263 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 264 265 266 /** 267 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 268 */ 269 typedef struct { 270 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 271 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 272 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 273 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 274 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 275 276 277 /** 278 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 279 */ 280 typedef struct { 281 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 282 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 283 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 284 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 285 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 286 287 288 /** 289 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 290 */ 291 typedef struct { 292 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 293 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 294 of SCK and minimum duration CSN must stay 295 high between transactions */ 296 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 297 298 299 /** 300 * @brief SPIS_PSEL [PSEL] (Unspecified) 301 */ 302 typedef struct { 303 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 304 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 305 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 306 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 307 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 308 309 310 /** 311 * @brief SPIS_RXD [RXD] (Unspecified) 312 */ 313 typedef struct { 314 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 315 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 316 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 317 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 318 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 319 320 321 /** 322 * @brief SPIS_TXD [TXD] (Unspecified) 323 */ 324 typedef struct { 325 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 326 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 327 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 328 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 329 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 330 331 332 /** 333 * @brief TWIM_PSEL [PSEL] (Unspecified) 334 */ 335 typedef struct { 336 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 337 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 338 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 339 340 341 /** 342 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 343 */ 344 typedef struct { 345 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 346 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 347 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 348 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 349 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 350 351 352 /** 353 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 354 */ 355 typedef struct { 356 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 357 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 358 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 359 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 360 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 361 362 363 /** 364 * @brief TWIS_PSEL [PSEL] (Unspecified) 365 */ 366 typedef struct { 367 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 368 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 369 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 370 371 372 /** 373 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 374 */ 375 typedef struct { 376 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 377 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 378 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 379 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 380 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 381 382 383 /** 384 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 385 */ 386 typedef struct { 387 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 388 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 389 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 390 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 391 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 392 393 394 /** 395 * @brief UARTE_PSEL [PSEL] (Unspecified) 396 */ 397 typedef struct { 398 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 399 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 400 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 401 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 402 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 403 404 405 /** 406 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 407 */ 408 typedef struct { 409 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 410 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 411 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 412 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 413 414 415 /** 416 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 417 */ 418 typedef struct { 419 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 420 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 421 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 422 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 423 424 425 /** 426 * @brief ACL_ACL [ACL] (Unspecified) 427 */ 428 typedef struct { 429 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned 430 start address of region n to protect */ 431 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 432 counting from address ACL[n].ADDR. Write 433 '0' as no effect. */ 434 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 435 n as defined by start address ACL[n].ADDR 436 and size ACL[n].SIZE */ 437 __IM uint32_t RESERVED; 438 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 439 440 441 /** 442 * @brief VMC_RAM [RAM] (Unspecified) 443 */ 444 typedef struct { 445 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAM[n] power control register */ 446 __IOM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAM[n] power control set 447 register */ 448 __IOM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAM[n] power control clear 449 register */ 450 __IM uint32_t RESERVED; 451 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 452 453 454 /** @} */ /* End of group Device_Peripheral_clusters */ 455 456 457 /* =========================================================================================================================== */ 458 /* ================ Device Specific Peripheral Section ================ */ 459 /* =========================================================================================================================== */ 460 461 462 /** @addtogroup Device_Peripheral_peripherals 463 * @{ 464 */ 465 466 467 468 /* =========================================================================================================================== */ 469 /* ================ FICR_NS ================ */ 470 /* =========================================================================================================================== */ 471 472 473 /** 474 * @brief Factory Information Configuration Registers (FICR_NS) 475 */ 476 477 typedef struct { /*!< (@ 0x01FF0000) FICR_NS Structure */ 478 __IM uint32_t RESERVED[128]; 479 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 480 __IM uint32_t RESERVED1[21]; 481 __IM uint32_t ER[4]; /*!< (@ 0x00000280) Description collection: Encryption Root, word 482 n */ 483 __IM uint32_t IR[4]; /*!< (@ 0x00000290) Description collection: Identity Root, word n */ 484 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000002A0) Device address type */ 485 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000002A4) Description collection: Device address n */ 486 __IM uint32_t RESERVED2[21]; 487 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 488 } NRF_FICR_Type; /*!< Size = 1024 (0x400) */ 489 490 491 492 /* =========================================================================================================================== */ 493 /* ================ UICR_NS ================ */ 494 /* =========================================================================================================================== */ 495 496 497 /** 498 * @brief User Information Configuration Registers (UICR_NS) 499 */ 500 501 typedef struct { /*!< (@ 0x01FF8000) UICR_NS Structure */ 502 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 503 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000004) Erase protection */ 504 __IM uint32_t RESERVED[126]; 505 __IOM uint32_t NRFFW[32]; /*!< (@ 0x00000200) Description collection: Reserved for Nordic firmware 506 design */ 507 __IM uint32_t RESERVED1[32]; 508 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000300) Description collection: Reserved for customer */ 509 } NRF_UICR_Type; /*!< Size = 896 (0x380) */ 510 511 512 513 /* =========================================================================================================================== */ 514 /* ================ CTI_NS ================ */ 515 /* =========================================================================================================================== */ 516 517 518 /** 519 * @brief Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. (CTI_NS) 520 */ 521 522 typedef struct { /*!< (@ 0xE0042000) CTI_NS Structure */ 523 __IOM uint32_t CTICONTROL; /*!< (@ 0x00000000) CTI Control register */ 524 __IM uint32_t RESERVED[3]; 525 __OM uint32_t CTIINTACK; /*!< (@ 0x00000010) CTI Interrupt Acknowledge register */ 526 __IOM uint32_t CTIAPPSET; /*!< (@ 0x00000014) CTI Application Trigger Set register */ 527 __OM uint32_t CTIAPPCLEAR; /*!< (@ 0x00000018) CTI Application Trigger Clear register */ 528 __OM uint32_t CTIAPPPULSE; /*!< (@ 0x0000001C) CTI Application Pulse register */ 529 __IOM uint32_t CTIINEN[8]; /*!< (@ 0x00000020) Description collection: CTI Trigger input */ 530 __IM uint32_t RESERVED1[24]; 531 __IOM uint32_t CTIOUTEN[8]; /*!< (@ 0x000000A0) Description collection: CTI Trigger output */ 532 __IM uint32_t RESERVED2[28]; 533 __IM uint32_t CTITRIGINSTATUS; /*!< (@ 0x00000130) CTI Trigger In Status register */ 534 __IM uint32_t CTITRIGOUTSTATUS; /*!< (@ 0x00000134) CTI Trigger Out Status register */ 535 __IM uint32_t CTICHINSTATUS; /*!< (@ 0x00000138) CTI Channel In Status register */ 536 __IM uint32_t RESERVED3; 537 __IOM uint32_t CTIGATE; /*!< (@ 0x00000140) Enable CTI Channel Gate register */ 538 __IM uint32_t RESERVED4[926]; 539 __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture register */ 540 __IM uint32_t RESERVED5[2]; 541 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration register */ 542 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier register */ 543 __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 544 __IM uint32_t PIDR5; /*!< (@ 0x00000FD4) Peripheral ID5 register */ 545 __IM uint32_t PIDR6; /*!< (@ 0x00000FD8) Peripheral ID6 register */ 546 __IM uint32_t PIDR7; /*!< (@ 0x00000FDC) Peripheral ID7 register */ 547 __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 548 __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 549 __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 550 __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 551 __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ 552 __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ 553 __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ 554 __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ 555 } NRF_CTI_Type; /*!< Size = 4096 (0x1000) */ 556 557 558 559 /* =========================================================================================================================== */ 560 /* ================ DCNF_NS ================ */ 561 /* =========================================================================================================================== */ 562 563 564 /** 565 * @brief Domain configuration management (DCNF_NS) 566 */ 567 568 typedef struct { /*!< (@ 0x41000000) DCNF_NS Structure */ 569 __IM uint32_t RESERVED[264]; 570 __IM uint32_t CPUID; /*!< (@ 0x00000420) CPU ID of this subsystem */ 571 } NRF_DCNF_Type; /*!< Size = 1060 (0x424) */ 572 573 574 575 /* =========================================================================================================================== */ 576 /* ================ VREQCTRL_NS ================ */ 577 /* =========================================================================================================================== */ 578 579 580 /** 581 * @brief Voltage request control (VREQCTRL_NS) 582 */ 583 584 typedef struct { /*!< (@ 0x41004000) VREQCTRL_NS Structure */ 585 __IM uint32_t RESERVED[320]; 586 __IOM VREQCTRL_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000500) Unspecified */ 587 } NRF_VREQCTRL_Type; /*!< Size = 1292 (0x50c) */ 588 589 590 591 /* =========================================================================================================================== */ 592 /* ================ CLOCK_NS ================ */ 593 /* =========================================================================================================================== */ 594 595 596 /** 597 * @brief Clock management (CLOCK_NS) 598 */ 599 600 typedef struct { /*!< (@ 0x41005000) CLOCK_NS Structure */ 601 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 602 HFCLKSRC */ 603 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 604 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 605 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 606 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 607 __IM uint32_t RESERVED[27]; 608 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 609 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 610 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 611 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 612 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 613 __IM uint32_t RESERVED1[27]; 614 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 615 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 616 __IM uint32_t RESERVED2[5]; 617 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 618 __IM uint32_t RESERVED3[24]; 619 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 620 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 621 __IM uint32_t RESERVED4[5]; 622 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 623 __IM uint32_t RESERVED5[88]; 624 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 625 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 626 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 627 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 628 __IM uint32_t RESERVED6[62]; 629 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 630 triggered */ 631 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 632 is running This register value in any CLOCK 633 instance reflects status only due to configurations/action 634 in that CLOCK instance. */ 635 __IM uint32_t RESERVED7; 636 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 637 triggered */ 638 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 639 This register value in any CLOCK instance 640 reflects status only due to configurations/actions 641 in that CLOCK instance. */ 642 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 643 task was triggered */ 644 __IM uint32_t RESERVED8[61]; 645 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 646 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 647 __IM uint32_t RESERVED9[15]; 648 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 649 __IM uint32_t RESERVED10[5]; 650 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 651 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 652 } NRF_CLOCK_Type; /*!< Size = 1400 (0x578) */ 653 654 655 656 /* =========================================================================================================================== */ 657 /* ================ POWER_NS ================ */ 658 /* =========================================================================================================================== */ 659 660 661 /** 662 * @brief Power control (POWER_NS) 663 */ 664 665 typedef struct { /*!< (@ 0x41005000) POWER_NS Structure */ 666 __IM uint32_t RESERVED[30]; 667 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 668 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 669 __IM uint32_t RESERVED1[30]; 670 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 671 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 672 __IM uint32_t RESERVED2[2]; 673 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 674 __IM uint32_t RESERVED3[2]; 675 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 676 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 677 __IM uint32_t RESERVED4[27]; 678 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 679 __IM uint32_t RESERVED5[2]; 680 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 681 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 682 __IM uint32_t RESERVED6[89]; 683 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 684 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 685 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 686 __IM uint32_t RESERVED7[132]; 687 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 688 register */ 689 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 690 691 692 693 /* =========================================================================================================================== */ 694 /* ================ RESET_NS ================ */ 695 /* =========================================================================================================================== */ 696 697 698 /** 699 * @brief Reset control (RESET_NS) 700 */ 701 702 typedef struct { /*!< (@ 0x41005000) RESET_NS Structure */ 703 __IM uint32_t RESERVED[256]; 704 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 705 } NRF_RESET_Type; /*!< Size = 1028 (0x404) */ 706 707 708 709 /* =========================================================================================================================== */ 710 /* ================ CTRLAP_NS ================ */ 711 /* =========================================================================================================================== */ 712 713 714 /** 715 * @brief Control access port (CTRLAP_NS) 716 */ 717 718 typedef struct { /*!< (@ 0x41006000) CTRLAP_NS Structure */ 719 __IM uint32_t RESERVED[256]; 720 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 721 __IM uint32_t RESERVED1[30]; 722 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 723 __IM uint32_t RESERVED2[14]; 724 __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ 725 __IM uint32_t RESERVED3[46]; 726 __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral */ 727 } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ 728 729 730 731 /* =========================================================================================================================== */ 732 /* ================ RADIO_NS ================ */ 733 /* =========================================================================================================================== */ 734 735 736 /** 737 * @brief 2.4 GHz radio (RADIO_NS) 738 */ 739 740 typedef struct { /*!< (@ 0x41008000) RADIO_NS Structure */ 741 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 742 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 743 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 744 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 745 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 746 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 747 the receive signal strength */ 748 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 749 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 750 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 751 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 752 802.15.4 mode */ 753 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 754 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 755 802.15.4 mode */ 756 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 757 __IM uint32_t RESERVED[19]; 758 __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000080) Subscribe configuration for task TXEN */ 759 __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000084) Subscribe configuration for task RXEN */ 760 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000088) Subscribe configuration for task START */ 761 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000008C) Subscribe configuration for task STOP */ 762 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000090) Subscribe configuration for task DISABLE */ 763 __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000094) Subscribe configuration for task RSSISTART */ 764 __IOM uint32_t SUBSCRIBE_RSSISTOP; /*!< (@ 0x00000098) Subscribe configuration for task RSSISTOP */ 765 __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x0000009C) Subscribe configuration for task BCSTART */ 766 __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x000000A0) Subscribe configuration for task BCSTOP */ 767 __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x000000A4) Subscribe configuration for task EDSTART */ 768 __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x000000A8) Subscribe configuration for task EDSTOP */ 769 __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x000000AC) Subscribe configuration for task CCASTART */ 770 __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x000000B0) Subscribe configuration for task CCASTOP */ 771 __IM uint32_t RESERVED1[19]; 772 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 773 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 774 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 775 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 776 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 777 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 778 packet */ 779 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 780 received packet */ 781 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 782 __IM uint32_t RESERVED2[2]; 783 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 784 __IM uint32_t RESERVED3; 785 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 786 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 787 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 788 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 789 ED sample is ready for readout from the 790 RADIO.EDSAMPLE register */ 791 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 792 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 793 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 794 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 795 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 796 from Ble_LR125Kbit to Ble_LR500Kbit. */ 797 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 798 TX path */ 799 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 800 RX path */ 801 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 802 __IM uint32_t RESERVED4[2]; 803 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 804 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 805 from air */ 806 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 807 CTEInfo byte) */ 808 __IM uint32_t RESERVED5[3]; 809 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 810 __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x00000184) Publish configuration for event ADDRESS */ 811 __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000188) Publish configuration for event PAYLOAD */ 812 __IOM uint32_t PUBLISH_END; /*!< (@ 0x0000018C) Publish configuration for event END */ 813 __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000190) Publish configuration for event DISABLED */ 814 __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000194) Publish configuration for event DEVMATCH */ 815 __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000198) Publish configuration for event DEVMISS */ 816 __IOM uint32_t PUBLISH_RSSIEND; /*!< (@ 0x0000019C) Publish configuration for event RSSIEND */ 817 __IM uint32_t RESERVED6[2]; 818 __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x000001A8) Publish configuration for event BCMATCH */ 819 __IM uint32_t RESERVED7; 820 __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x000001B0) Publish configuration for event CRCOK */ 821 __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x000001B4) Publish configuration for event CRCERROR */ 822 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x000001B8) Publish configuration for event FRAMESTART */ 823 __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x000001BC) Publish configuration for event EDEND */ 824 __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x000001C0) Publish configuration for event EDSTOPPED */ 825 __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x000001C4) Publish configuration for event CCAIDLE */ 826 __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x000001C8) Publish configuration for event CCABUSY */ 827 __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x000001CC) Publish configuration for event CCASTOPPED */ 828 __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x000001D0) Publish configuration for event RATEBOOST */ 829 __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x000001D4) Publish configuration for event TXREADY */ 830 __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x000001D8) Publish configuration for event RXREADY */ 831 __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH */ 832 __IM uint32_t RESERVED8[2]; 833 __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x000001E8) Publish configuration for event SYNC */ 834 __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x000001EC) Publish configuration for event PHYEND */ 835 __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT */ 836 __IM uint32_t RESERVED9[3]; 837 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 838 __IM uint32_t RESERVED10[64]; 839 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 840 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 841 __IM uint32_t RESERVED11[61]; 842 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 843 __IM uint32_t RESERVED12; 844 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 845 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 846 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 847 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 848 __IM uint32_t RESERVED13[13]; 849 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 850 __IM uint32_t RESERVED14[2]; 851 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 852 __IM uint32_t RESERVED15[42]; 853 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 854 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 855 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 856 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 857 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 858 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 859 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 860 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 861 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 862 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 863 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 864 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 865 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 866 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 867 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 868 __IM uint32_t RESERVED16; 869 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 870 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 871 __IM uint32_t RESERVED17; 872 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 873 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 874 __IM uint32_t RESERVED18[2]; 875 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 876 __IM uint32_t RESERVED19[39]; 877 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 878 n */ 879 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 880 n */ 881 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 882 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 883 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 884 __IM uint32_t RESERVED20; 885 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 886 __IM uint32_t RESERVED21[3]; 887 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 888 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 889 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 890 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 891 __IM uint32_t RESERVED22[164]; 892 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 893 (AOD) */ 894 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 895 __IM uint32_t RESERVED23[2]; 896 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 897 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 898 __IM uint32_t RESERVED24[4]; 899 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 900 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 901 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 902 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 903 __IM uint32_t RESERVED25[424]; 904 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 905 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 906 907 908 909 /* =========================================================================================================================== */ 910 /* ================ RNG_NS ================ */ 911 /* =========================================================================================================================== */ 912 913 914 /** 915 * @brief Random Number Generator (RNG_NS) 916 */ 917 918 typedef struct { /*!< (@ 0x41009000) RNG_NS Structure */ 919 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 920 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 921 __IM uint32_t RESERVED[30]; 922 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 923 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 924 __IM uint32_t RESERVED1[30]; 925 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 926 written to the VALUE register */ 927 __IM uint32_t RESERVED2[31]; 928 __IOM uint32_t PUBLISH_VALRDY; /*!< (@ 0x00000180) Publish configuration for event VALRDY */ 929 __IM uint32_t RESERVED3[31]; 930 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 931 __IM uint32_t RESERVED4[64]; 932 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 933 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 934 __IM uint32_t RESERVED5[126]; 935 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 936 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 937 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 938 939 940 941 /* =========================================================================================================================== */ 942 /* ================ GPIOTE_NS ================ */ 943 /* =========================================================================================================================== */ 944 945 946 /** 947 * @brief GPIO Tasks and Events (GPIOTE_NS) 948 */ 949 950 typedef struct { /*!< (@ 0x4100A000) GPIOTE_NS Structure */ 951 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 952 specified in CONFIG[n].PSEL. Action on pin 953 is configured in CONFIG[n].POLARITY. */ 954 __IM uint32_t RESERVED[4]; 955 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 956 specified in CONFIG[n].PSEL. Action on pin 957 is to set it high. */ 958 __IM uint32_t RESERVED1[4]; 959 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 960 specified in CONFIG[n].PSEL. Action on pin 961 is to set it low. */ 962 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 963 for task OUT[n] */ 964 __IM uint32_t RESERVED2[4]; 965 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 966 for task SET[n] */ 967 __IM uint32_t RESERVED3[4]; 968 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 969 for task CLR[n] */ 970 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 971 pin specified in CONFIG[n].PSEL */ 972 __IM uint32_t RESERVED4[23]; 973 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 974 with SENSE mechanism enabled */ 975 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 976 for event IN[n] */ 977 __IM uint32_t RESERVED5[23]; 978 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 979 __IM uint32_t RESERVED6[65]; 980 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 981 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 982 __IM uint32_t RESERVED7[126]; 983 __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) 984 with rising or falling edge detection on 985 the pin. */ 986 __IM uint32_t RESERVED8[2]; 987 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 988 SET[n], and CLR[n] tasks and IN[n] event */ 989 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 990 991 992 993 /* =========================================================================================================================== */ 994 /* ================ WDT_NS ================ */ 995 /* =========================================================================================================================== */ 996 997 998 /** 999 * @brief Watchdog Timer (WDT_NS) 1000 */ 1001 1002 typedef struct { /*!< (@ 0x4100B000) WDT_NS Structure */ 1003 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1004 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the watchdog timer. */ 1005 __IM uint32_t RESERVED[30]; 1006 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1007 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1008 __IM uint32_t RESERVED1[30]; 1009 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1010 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ 1011 __IM uint32_t RESERVED2[30]; 1012 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1013 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1014 __IM uint32_t RESERVED3[95]; 1015 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1016 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1017 __IM uint32_t RESERVED4[6]; 1018 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 1019 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 1020 __IM uint32_t RESERVED5[53]; 1021 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1022 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1023 __IM uint32_t RESERVED6[63]; 1024 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1025 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1026 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1027 __IM uint32_t RESERVED7[4]; 1028 __OM uint32_t TSEN; /*!< (@ 0x00000520) Task Stop Enable */ 1029 __IM uint32_t RESERVED8[55]; 1030 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1031 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1032 1033 1034 1035 /* =========================================================================================================================== */ 1036 /* ================ TIMER0_NS ================ */ 1037 /* =========================================================================================================================== */ 1038 1039 1040 /** 1041 * @brief Timer/Counter 0 (TIMER0_NS) 1042 */ 1043 1044 typedef struct { /*!< (@ 0x4100C000) TIMER0_NS Structure */ 1045 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1046 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1047 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1048 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1049 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1050 __IM uint32_t RESERVED[11]; 1051 __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1052 CC[n] register */ 1053 __IM uint32_t RESERVED1[8]; 1054 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1055 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1056 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1057 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1058 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1059 for task SHUTDOWN */ 1060 __IM uint32_t RESERVED2[11]; 1061 __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1062 for task CAPTURE[n] */ 1063 __IM uint32_t RESERVED3[24]; 1064 __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1065 match */ 1066 __IM uint32_t RESERVED4[24]; 1067 __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1068 for event COMPARE[n] */ 1069 __IM uint32_t RESERVED5[8]; 1070 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1071 __IM uint32_t RESERVED6[63]; 1072 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1073 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1074 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1075 __IM uint32_t RESERVED7[126]; 1076 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1077 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1078 __IM uint32_t RESERVED8; 1079 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1080 __IM uint32_t RESERVED9[11]; 1081 __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1082 n */ 1083 __IM uint32_t RESERVED10[8]; 1084 __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 1085 for Capture/Compare channel n */ 1086 } NRF_TIMER_Type; /*!< Size = 1440 (0x5a0) */ 1087 1088 1089 1090 /* =========================================================================================================================== */ 1091 /* ================ ECB_NS ================ */ 1092 /* =========================================================================================================================== */ 1093 1094 1095 /** 1096 * @brief AES ECB Mode Encryption (ECB_NS) 1097 */ 1098 1099 typedef struct { /*!< (@ 0x4100D000) ECB_NS Structure */ 1100 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1101 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1102 __IM uint32_t RESERVED[30]; 1103 __IOM uint32_t SUBSCRIBE_STARTECB; /*!< (@ 0x00000080) Subscribe configuration for task STARTECB */ 1104 __IOM uint32_t SUBSCRIBE_STOPECB; /*!< (@ 0x00000084) Subscribe configuration for task STOPECB */ 1105 __IM uint32_t RESERVED1[30]; 1106 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1107 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1108 task or due to an error */ 1109 __IM uint32_t RESERVED2[30]; 1110 __IOM uint32_t PUBLISH_ENDECB; /*!< (@ 0x00000180) Publish configuration for event ENDECB */ 1111 __IOM uint32_t PUBLISH_ERRORECB; /*!< (@ 0x00000184) Publish configuration for event ERRORECB */ 1112 __IM uint32_t RESERVED3[95]; 1113 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1114 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1115 __IM uint32_t RESERVED4[126]; 1116 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1117 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1118 1119 1120 1121 /* =========================================================================================================================== */ 1122 /* ================ AAR_NS ================ */ 1123 /* =========================================================================================================================== */ 1124 1125 1126 /** 1127 * @brief Accelerated Address Resolver (AAR_NS) 1128 */ 1129 1130 typedef struct { /*!< (@ 0x4100E000) AAR_NS Structure */ 1131 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1132 in the IRK data structure */ 1133 __IM uint32_t RESERVED; 1134 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1135 __IM uint32_t RESERVED1[29]; 1136 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1137 __IM uint32_t RESERVED2; 1138 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1139 __IM uint32_t RESERVED3[29]; 1140 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1141 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1142 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1143 __IM uint32_t RESERVED4[29]; 1144 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ 1145 __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ 1146 __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ 1147 __IM uint32_t RESERVED5[94]; 1148 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1149 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1150 __IM uint32_t RESERVED6[61]; 1151 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1152 __IM uint32_t RESERVED7[63]; 1153 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1154 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1155 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1156 __IM uint32_t RESERVED8; 1157 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1158 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1159 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1160 1161 1162 1163 /* =========================================================================================================================== */ 1164 /* ================ CCM_NS ================ */ 1165 /* =========================================================================================================================== */ 1166 1167 1168 /** 1169 * @brief AES CCM mode encryption (CCM_NS) 1170 */ 1171 1172 typedef struct { /*!< (@ 0x4100E000) CCM_NS Structure */ 1173 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1174 will stop by itself when completed. */ 1175 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1176 stop by itself when completed. */ 1177 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1178 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1179 the contents of the RATEOVERRIDE register 1180 for any ongoing encryption/decryption */ 1181 __IM uint32_t RESERVED[28]; 1182 __IOM uint32_t SUBSCRIBE_KSGEN; /*!< (@ 0x00000080) Subscribe configuration for task KSGEN */ 1183 __IOM uint32_t SUBSCRIBE_CRYPT; /*!< (@ 0x00000084) Subscribe configuration for task CRYPT */ 1184 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1185 __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE */ 1186 __IM uint32_t RESERVED1[28]; 1187 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1188 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1189 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1190 __IM uint32_t RESERVED2[29]; 1191 __IOM uint32_t PUBLISH_ENDKSGEN; /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN */ 1192 __IOM uint32_t PUBLISH_ENDCRYPT; /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT */ 1193 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Deprecated register - Publish configuration for 1194 event ERROR */ 1195 __IM uint32_t RESERVED3[29]; 1196 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1197 __IM uint32_t RESERVED4[64]; 1198 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1199 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1200 __IM uint32_t RESERVED5[61]; 1201 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1202 __IM uint32_t RESERVED6[63]; 1203 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1204 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1205 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 1206 and the NONCE vector */ 1207 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1208 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1209 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1210 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1211 = Extended */ 1212 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1213 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 1214 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 1215 1216 1217 1218 /* =========================================================================================================================== */ 1219 /* ================ DPPIC_NS ================ */ 1220 /* =========================================================================================================================== */ 1221 1222 1223 /** 1224 * @brief Distributed programmable peripheral interconnect controller (DPPIC_NS) 1225 */ 1226 1227 typedef struct { /*!< (@ 0x4100F000) DPPIC_NS Structure */ 1228 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1229 __IM uint32_t RESERVED[20]; 1230 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1231 __IM uint32_t RESERVED1[276]; 1232 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1233 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1234 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1235 __IM uint32_t RESERVED2[189]; 1236 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1237 Writes to this register are ignored if either 1238 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1239 is enabled */ 1240 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1241 1242 1243 1244 /* =========================================================================================================================== */ 1245 /* ================ TEMP_NS ================ */ 1246 /* =========================================================================================================================== */ 1247 1248 1249 /** 1250 * @brief Temperature Sensor (TEMP_NS) 1251 */ 1252 1253 typedef struct { /*!< (@ 0x41010000) TEMP_NS Structure */ 1254 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1255 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1256 __IM uint32_t RESERVED[30]; 1257 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1258 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1259 __IM uint32_t RESERVED1[30]; 1260 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1261 __IM uint32_t RESERVED2[31]; 1262 __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ 1263 __IM uint32_t RESERVED3[96]; 1264 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1265 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1266 __IM uint32_t RESERVED4[127]; 1267 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1268 __IM uint32_t RESERVED5[5]; 1269 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1270 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1271 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1272 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1273 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1274 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1275 __IM uint32_t RESERVED6[2]; 1276 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1277 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1278 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1279 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1280 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1281 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1282 __IM uint32_t RESERVED7[2]; 1283 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1284 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1285 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1286 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1287 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1288 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1289 1290 1291 1292 /* =========================================================================================================================== */ 1293 /* ================ RTC0_NS ================ */ 1294 /* =========================================================================================================================== */ 1295 1296 1297 /** 1298 * @brief Real-time counter 0 (RTC0_NS) 1299 */ 1300 1301 typedef struct { /*!< (@ 0x41011000) RTC0_NS Structure */ 1302 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1303 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1304 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1305 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1306 __IM uint32_t RESERVED[12]; 1307 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 1308 CC[n] register */ 1309 __IM uint32_t RESERVED1[12]; 1310 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1311 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1312 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1313 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1314 __IM uint32_t RESERVED2[12]; 1315 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1316 for task CAPTURE[n] */ 1317 __IM uint32_t RESERVED3[12]; 1318 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1319 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1320 __IM uint32_t RESERVED4[14]; 1321 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1322 match */ 1323 __IM uint32_t RESERVED5[12]; 1324 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1325 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1326 __IM uint32_t RESERVED6[14]; 1327 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1328 for event COMPARE[n] */ 1329 __IM uint32_t RESERVED7[12]; 1330 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1331 __IM uint32_t RESERVED8[64]; 1332 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1333 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1334 __IM uint32_t RESERVED9[13]; 1335 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1336 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1337 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1338 __IM uint32_t RESERVED10[110]; 1339 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1340 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1341 Must be written when RTC is stopped. */ 1342 __IM uint32_t RESERVED11[13]; 1343 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1344 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1345 1346 1347 1348 /* =========================================================================================================================== */ 1349 /* ================ IPC_NS ================ */ 1350 /* =========================================================================================================================== */ 1351 1352 1353 /** 1354 * @brief Interprocessor communication (IPC_NS) 1355 */ 1356 1357 typedef struct { /*!< (@ 0x41012000) IPC_NS Structure */ 1358 __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 1359 channel enabled in SEND_CNF[n] */ 1360 __IM uint32_t RESERVED[16]; 1361 __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1362 for task SEND[n] */ 1363 __IM uint32_t RESERVED1[16]; 1364 __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Description collection: Event received on one 1365 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 1366 __IM uint32_t RESERVED2[16]; 1367 __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1368 for event RECEIVE[n] */ 1369 __IM uint32_t RESERVED3[80]; 1370 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1371 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1372 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1373 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1374 __IM uint32_t RESERVED4[128]; 1375 __IOM uint32_t SEND_CNF[16]; /*!< (@ 0x00000510) Description collection: Send event configuration 1376 for TASKS_SEND[n] */ 1377 __IM uint32_t RESERVED5[16]; 1378 __IOM uint32_t RECEIVE_CNF[16]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1379 for EVENTS_RECEIVE[n] */ 1380 __IM uint32_t RESERVED6[16]; 1381 __IOM uint32_t GPMEM[2]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 1382 } NRF_IPC_Type; /*!< Size = 1560 (0x618) */ 1383 1384 1385 1386 /* =========================================================================================================================== */ 1387 /* ================ SPIM0_NS ================ */ 1388 /* =========================================================================================================================== */ 1389 1390 1391 /** 1392 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0_NS) 1393 */ 1394 1395 typedef struct { /*!< (@ 0x41013000) SPIM0_NS Structure */ 1396 __IM uint32_t RESERVED[4]; 1397 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1398 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1399 __IM uint32_t RESERVED1; 1400 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1401 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1402 __IM uint32_t RESERVED2[27]; 1403 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1404 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1405 __IM uint32_t RESERVED3; 1406 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1407 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1408 __IM uint32_t RESERVED4[24]; 1409 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1410 __IM uint32_t RESERVED5[2]; 1411 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1412 __IM uint32_t RESERVED6; 1413 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1414 __IM uint32_t RESERVED7; 1415 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1416 __IM uint32_t RESERVED8[10]; 1417 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1418 __IM uint32_t RESERVED9[13]; 1419 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1420 __IM uint32_t RESERVED10[2]; 1421 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1422 __IM uint32_t RESERVED11; 1423 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1424 __IM uint32_t RESERVED12; 1425 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1426 __IM uint32_t RESERVED13[10]; 1427 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1428 __IM uint32_t RESERVED14[12]; 1429 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1430 __IM uint32_t RESERVED15[64]; 1431 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1432 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1433 __IM uint32_t RESERVED16[61]; 1434 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1435 in this register is set to STALL by hardware 1436 whenever a stall occurres and can be cleared 1437 (set to NOSTALL) by the CPU. */ 1438 __IM uint32_t RESERVED17[63]; 1439 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1440 __IM uint32_t RESERVED18; 1441 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1442 __IM uint32_t RESERVED19[3]; 1443 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1444 source selected. */ 1445 __IM uint32_t RESERVED20[3]; 1446 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1447 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1448 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1449 __IM uint32_t RESERVED21[2]; 1450 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1451 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1452 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1453 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1454 __IM uint32_t RESERVED22[19]; 1455 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1456 been transmitted in the case when RXD.MAXCNT 1457 is greater than TXD.MAXCNT */ 1458 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1459 1460 1461 1462 /* =========================================================================================================================== */ 1463 /* ================ SPIS0_NS ================ */ 1464 /* =========================================================================================================================== */ 1465 1466 1467 /** 1468 * @brief SPI Slave (SPIS0_NS) 1469 */ 1470 1471 typedef struct { /*!< (@ 0x41013000) SPIS0_NS Structure */ 1472 __IM uint32_t RESERVED[9]; 1473 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1474 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1475 to acquire it */ 1476 __IM uint32_t RESERVED1[30]; 1477 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1478 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1479 __IM uint32_t RESERVED2[22]; 1480 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1481 __IM uint32_t RESERVED3[2]; 1482 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1483 __IM uint32_t RESERVED4[5]; 1484 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1485 __IM uint32_t RESERVED5[22]; 1486 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1487 __IM uint32_t RESERVED6[2]; 1488 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1489 __IM uint32_t RESERVED7[5]; 1490 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1491 __IM uint32_t RESERVED8[21]; 1492 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1493 __IM uint32_t RESERVED9[64]; 1494 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1495 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1496 __IM uint32_t RESERVED10[61]; 1497 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1498 __IM uint32_t RESERVED11[15]; 1499 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1500 __IM uint32_t RESERVED12[47]; 1501 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1502 __IM uint32_t RESERVED13; 1503 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1504 __IM uint32_t RESERVED14[7]; 1505 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1506 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1507 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1508 __IM uint32_t RESERVED15; 1509 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1510 of an ignored transaction. */ 1511 __IM uint32_t RESERVED16[24]; 1512 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1513 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1514 1515 1516 1517 /* =========================================================================================================================== */ 1518 /* ================ TWIM0_NS ================ */ 1519 /* =========================================================================================================================== */ 1520 1521 1522 /** 1523 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0_NS) 1524 */ 1525 1526 typedef struct { /*!< (@ 0x41013000) TWIM0_NS Structure */ 1527 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1528 __IM uint32_t RESERVED; 1529 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1530 __IM uint32_t RESERVED1[2]; 1531 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1532 TWI master is not suspended. */ 1533 __IM uint32_t RESERVED2; 1534 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1535 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1536 __IM uint32_t RESERVED3[23]; 1537 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1538 __IM uint32_t RESERVED4; 1539 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1540 __IM uint32_t RESERVED5[2]; 1541 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1542 __IM uint32_t RESERVED6; 1543 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1544 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1545 __IM uint32_t RESERVED7[24]; 1546 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1547 __IM uint32_t RESERVED8[7]; 1548 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1549 __IM uint32_t RESERVED9[8]; 1550 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1551 now suspended. */ 1552 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1553 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1554 __IM uint32_t RESERVED10[2]; 1555 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1556 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1557 byte */ 1558 __IM uint32_t RESERVED11[8]; 1559 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1560 __IM uint32_t RESERVED12[7]; 1561 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1562 __IM uint32_t RESERVED13[8]; 1563 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1564 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1565 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1566 __IM uint32_t RESERVED14[2]; 1567 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1568 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1569 __IM uint32_t RESERVED15[7]; 1570 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1571 __IM uint32_t RESERVED16[63]; 1572 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1573 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1574 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1575 __IM uint32_t RESERVED17[110]; 1576 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1577 __IM uint32_t RESERVED18[14]; 1578 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1579 __IM uint32_t RESERVED19; 1580 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1581 __IM uint32_t RESERVED20[5]; 1582 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1583 source selected. */ 1584 __IM uint32_t RESERVED21[3]; 1585 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1586 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1587 __IM uint32_t RESERVED22[13]; 1588 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1589 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1590 1591 1592 1593 /* =========================================================================================================================== */ 1594 /* ================ TWIS0_NS ================ */ 1595 /* =========================================================================================================================== */ 1596 1597 1598 /** 1599 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0_NS) 1600 */ 1601 1602 typedef struct { /*!< (@ 0x41013000) TWIS0_NS Structure */ 1603 __IM uint32_t RESERVED[5]; 1604 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1605 __IM uint32_t RESERVED1; 1606 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1607 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1608 __IM uint32_t RESERVED2[3]; 1609 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1610 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1611 __IM uint32_t RESERVED3[23]; 1612 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1613 __IM uint32_t RESERVED4; 1614 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1615 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1616 __IM uint32_t RESERVED5[3]; 1617 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1618 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1619 __IM uint32_t RESERVED6[19]; 1620 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1621 __IM uint32_t RESERVED7[7]; 1622 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1623 __IM uint32_t RESERVED8[9]; 1624 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1625 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1626 __IM uint32_t RESERVED9[4]; 1627 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1628 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1629 __IM uint32_t RESERVED10[6]; 1630 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1631 __IM uint32_t RESERVED11[7]; 1632 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1633 __IM uint32_t RESERVED12[9]; 1634 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1635 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1636 __IM uint32_t RESERVED13[4]; 1637 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1638 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1639 __IM uint32_t RESERVED14[5]; 1640 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1641 __IM uint32_t RESERVED15[63]; 1642 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1643 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1644 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1645 __IM uint32_t RESERVED16[113]; 1646 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1647 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1648 a match */ 1649 __IM uint32_t RESERVED17[10]; 1650 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1651 __IM uint32_t RESERVED18; 1652 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1653 __IM uint32_t RESERVED19[9]; 1654 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1655 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1656 __IM uint32_t RESERVED20[13]; 1657 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1658 __IM uint32_t RESERVED21; 1659 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1660 mechanism */ 1661 __IM uint32_t RESERVED22[10]; 1662 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1663 of an over-read of the transmit buffer. */ 1664 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1665 1666 1667 1668 /* =========================================================================================================================== */ 1669 /* ================ UARTE0_NS ================ */ 1670 /* =========================================================================================================================== */ 1671 1672 1673 /** 1674 * @brief UART with EasyDMA (UARTE0_NS) 1675 */ 1676 1677 typedef struct { /*!< (@ 0x41013000) UARTE0_NS Structure */ 1678 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1679 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1680 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1681 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1682 __IM uint32_t RESERVED[7]; 1683 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1684 __IM uint32_t RESERVED1[20]; 1685 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1686 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1687 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1688 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1689 __IM uint32_t RESERVED2[7]; 1690 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1691 __IM uint32_t RESERVED3[20]; 1692 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1693 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1694 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1695 transferred to Data RAM) */ 1696 __IM uint32_t RESERVED4; 1697 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1698 __IM uint32_t RESERVED5[2]; 1699 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1700 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1701 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1702 __IM uint32_t RESERVED6[7]; 1703 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1704 __IM uint32_t RESERVED7; 1705 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1706 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1707 __IM uint32_t RESERVED8; 1708 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1709 __IM uint32_t RESERVED9[9]; 1710 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1711 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1712 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1713 __IM uint32_t RESERVED10; 1714 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1715 __IM uint32_t RESERVED11[2]; 1716 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1717 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1718 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1719 __IM uint32_t RESERVED12[7]; 1720 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1721 __IM uint32_t RESERVED13; 1722 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1723 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1724 __IM uint32_t RESERVED14; 1725 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1726 __IM uint32_t RESERVED15[9]; 1727 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1728 __IM uint32_t RESERVED16[63]; 1729 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1730 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1731 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1732 __IM uint32_t RESERVED17[93]; 1733 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1734 one to clear. */ 1735 __IM uint32_t RESERVED18[31]; 1736 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1737 __IM uint32_t RESERVED19; 1738 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1739 __IM uint32_t RESERVED20[3]; 1740 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1741 selected. */ 1742 __IM uint32_t RESERVED21[3]; 1743 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1744 __IM uint32_t RESERVED22; 1745 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1746 __IM uint32_t RESERVED23[7]; 1747 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1748 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1749 1750 1751 1752 /* =========================================================================================================================== */ 1753 /* ================ EGU0_NS ================ */ 1754 /* =========================================================================================================================== */ 1755 1756 1757 /** 1758 * @brief Event generator unit (EGU0_NS) 1759 */ 1760 1761 typedef struct { /*!< (@ 0x41014000) EGU0_NS Structure */ 1762 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1763 the corresponding TRIGGERED[n] event */ 1764 __IM uint32_t RESERVED[16]; 1765 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1766 for task TRIGGER[n] */ 1767 __IM uint32_t RESERVED1[16]; 1768 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1769 by triggering the corresponding TRIGGER[n] 1770 task */ 1771 __IM uint32_t RESERVED2[16]; 1772 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1773 for event TRIGGERED[n] */ 1774 __IM uint32_t RESERVED3[80]; 1775 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1776 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1777 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1778 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1779 1780 1781 1782 /* =========================================================================================================================== */ 1783 /* ================ SWI0_NS ================ */ 1784 /* =========================================================================================================================== */ 1785 1786 1787 /** 1788 * @brief Software interrupt 0 (SWI0_NS) 1789 */ 1790 1791 typedef struct { /*!< (@ 0x4101A000) SWI0_NS Structure */ 1792 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1793 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1794 1795 1796 1797 /* =========================================================================================================================== */ 1798 /* ================ APPMUTEX_NS ================ */ 1799 /* =========================================================================================================================== */ 1800 1801 1802 /** 1803 * @brief MUTEX 0 (APPMUTEX_NS) 1804 */ 1805 1806 typedef struct { /*!< (@ 0x40030000) APPMUTEX_NS Structure */ 1807 __IM uint32_t RESERVED[256]; 1808 __IOM uint32_t MUTEX[16]; /*!< (@ 0x00000400) Description collection: Mutex register */ 1809 } NRF_MUTEX_Type; /*!< Size = 1088 (0x440) */ 1810 1811 1812 1813 /* =========================================================================================================================== */ 1814 /* ================ ACL_NS ================ */ 1815 /* =========================================================================================================================== */ 1816 1817 1818 /** 1819 * @brief Access control lists (ACL_NS) 1820 */ 1821 1822 typedef struct { /*!< (@ 0x41080000) ACL_NS Structure */ 1823 __IM uint32_t RESERVED[512]; 1824 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 1825 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 1826 1827 1828 1829 /* =========================================================================================================================== */ 1830 /* ================ NVMC_NS ================ */ 1831 /* =========================================================================================================================== */ 1832 1833 1834 /** 1835 * @brief Non-volatile memory controller (NVMC_NS) 1836 */ 1837 1838 typedef struct { /*!< (@ 0x41080000) NVMC_NS Structure */ 1839 __IM uint32_t RESERVED[256]; 1840 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1841 __IM uint32_t RESERVED1; 1842 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1843 __IM uint32_t RESERVED2[62]; 1844 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1845 __IM uint32_t RESERVED3; 1846 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1847 __IM uint32_t RESERVED4[3]; 1848 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1849 __IM uint32_t RESERVED5[8]; 1850 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1851 __IM uint32_t RESERVED6; 1852 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1853 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1854 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 1855 1856 1857 1858 /* =========================================================================================================================== */ 1859 /* ================ VMC_NS ================ */ 1860 /* =========================================================================================================================== */ 1861 1862 1863 /** 1864 * @brief Volatile Memory controller (VMC_NS) 1865 */ 1866 1867 typedef struct { /*!< (@ 0x41081000) VMC_NS Structure */ 1868 __IM uint32_t RESERVED[384]; 1869 __IOM VMC_RAM_Type RAM[4]; /*!< (@ 0x00000600) Unspecified */ 1870 } NRF_VMC_Type; /*!< Size = 1600 (0x640) */ 1871 1872 1873 1874 /* =========================================================================================================================== */ 1875 /* ================ P0_NS ================ */ 1876 /* =========================================================================================================================== */ 1877 1878 1879 /** 1880 * @brief GPIO Port 0 (P0_NS) 1881 */ 1882 1883 typedef struct { /*!< (@ 0x418C0500) P0_NS Structure */ 1884 __IM uint32_t RESERVED; 1885 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 1886 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 1887 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 1888 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 1889 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 1890 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 1891 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 1892 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 1893 have met the criteria set in the PIN_CNF[n].SENSE 1894 registers */ 1895 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 1896 and LDETECT mode (For non-secure pin only) */ 1897 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 1898 and LDETECT mode (For secure pin only) */ 1899 __IM uint32_t RESERVED1[117]; 1900 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 1901 pins */ 1902 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 1903 1904 1905 /** @} */ /* End of group Device_Peripheral_peripherals */ 1906 1907 1908 /* =========================================================================================================================== */ 1909 /* ================ Device Specific Peripheral Address Map ================ */ 1910 /* =========================================================================================================================== */ 1911 1912 1913 /** @addtogroup Device_Peripheral_peripheralAddr 1914 * @{ 1915 */ 1916 1917 #define NRF_FICR_NS_BASE 0x01FF0000UL 1918 #define NRF_UICR_NS_BASE 0x01FF8000UL 1919 #define NRF_CTI_NS_BASE 0xE0042000UL 1920 #define NRF_DCNF_NS_BASE 0x41000000UL 1921 #define NRF_VREQCTRL_NS_BASE 0x41004000UL 1922 #define NRF_CLOCK_NS_BASE 0x41005000UL 1923 #define NRF_POWER_NS_BASE 0x41005000UL 1924 #define NRF_RESET_NS_BASE 0x41005000UL 1925 #define NRF_CTRLAP_NS_BASE 0x41006000UL 1926 #define NRF_RADIO_NS_BASE 0x41008000UL 1927 #define NRF_RNG_NS_BASE 0x41009000UL 1928 #define NRF_GPIOTE_NS_BASE 0x4100A000UL 1929 #define NRF_WDT_NS_BASE 0x4100B000UL 1930 #define NRF_TIMER0_NS_BASE 0x4100C000UL 1931 #define NRF_ECB_NS_BASE 0x4100D000UL 1932 #define NRF_AAR_NS_BASE 0x4100E000UL 1933 #define NRF_CCM_NS_BASE 0x4100E000UL 1934 #define NRF_DPPIC_NS_BASE 0x4100F000UL 1935 #define NRF_TEMP_NS_BASE 0x41010000UL 1936 #define NRF_RTC0_NS_BASE 0x41011000UL 1937 #define NRF_IPC_NS_BASE 0x41012000UL 1938 #define NRF_SPIM0_NS_BASE 0x41013000UL 1939 #define NRF_SPIS0_NS_BASE 0x41013000UL 1940 #define NRF_TWIM0_NS_BASE 0x41013000UL 1941 #define NRF_TWIS0_NS_BASE 0x41013000UL 1942 #define NRF_UARTE0_NS_BASE 0x41013000UL 1943 #define NRF_EGU0_NS_BASE 0x41014000UL 1944 #define NRF_RTC1_NS_BASE 0x41016000UL 1945 #define NRF_TIMER1_NS_BASE 0x41018000UL 1946 #define NRF_TIMER2_NS_BASE 0x41019000UL 1947 #define NRF_SWI0_NS_BASE 0x4101A000UL 1948 #define NRF_SWI1_NS_BASE 0x4101B000UL 1949 #define NRF_SWI2_NS_BASE 0x4101C000UL 1950 #define NRF_SWI3_NS_BASE 0x4101D000UL 1951 #define NRF_APPMUTEX_NS_BASE 0x40030000UL 1952 #define NRF_APPMUTEX_S_BASE 0x50030000UL 1953 #define NRF_ACL_NS_BASE 0x41080000UL 1954 #define NRF_NVMC_NS_BASE 0x41080000UL 1955 #define NRF_VMC_NS_BASE 0x41081000UL 1956 #define NRF_P0_NS_BASE 0x418C0500UL 1957 #define NRF_P1_NS_BASE 0x418C0800UL 1958 1959 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1960 1961 1962 /* =========================================================================================================================== */ 1963 /* ================ Peripheral declaration ================ */ 1964 /* =========================================================================================================================== */ 1965 1966 1967 /** @addtogroup Device_Peripheral_declaration 1968 * @{ 1969 */ 1970 1971 #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) 1972 #define NRF_UICR_NS ((NRF_UICR_Type*) NRF_UICR_NS_BASE) 1973 #define NRF_CTI_NS ((NRF_CTI_Type*) NRF_CTI_NS_BASE) 1974 #define NRF_DCNF_NS ((NRF_DCNF_Type*) NRF_DCNF_NS_BASE) 1975 #define NRF_VREQCTRL_NS ((NRF_VREQCTRL_Type*) NRF_VREQCTRL_NS_BASE) 1976 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 1977 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 1978 #define NRF_RESET_NS ((NRF_RESET_Type*) NRF_RESET_NS_BASE) 1979 #define NRF_CTRLAP_NS ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_NS_BASE) 1980 #define NRF_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIO_NS_BASE) 1981 #define NRF_RNG_NS ((NRF_RNG_Type*) NRF_RNG_NS_BASE) 1982 #define NRF_GPIOTE_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE_NS_BASE) 1983 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 1984 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 1985 #define NRF_ECB_NS ((NRF_ECB_Type*) NRF_ECB_NS_BASE) 1986 #define NRF_AAR_NS ((NRF_AAR_Type*) NRF_AAR_NS_BASE) 1987 #define NRF_CCM_NS ((NRF_CCM_Type*) NRF_CCM_NS_BASE) 1988 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 1989 #define NRF_TEMP_NS ((NRF_TEMP_Type*) NRF_TEMP_NS_BASE) 1990 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 1991 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 1992 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 1993 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 1994 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 1995 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 1996 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 1997 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 1998 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 1999 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2000 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2001 #define NRF_SWI0_NS ((NRF_SWI_Type*) NRF_SWI0_NS_BASE) 2002 #define NRF_SWI1_NS ((NRF_SWI_Type*) NRF_SWI1_NS_BASE) 2003 #define NRF_SWI2_NS ((NRF_SWI_Type*) NRF_SWI2_NS_BASE) 2004 #define NRF_SWI3_NS ((NRF_SWI_Type*) NRF_SWI3_NS_BASE) 2005 #define NRF_APPMUTEX_NS ((NRF_MUTEX_Type*) NRF_APPMUTEX_NS_BASE) 2006 #define NRF_APPMUTEX_S ((NRF_MUTEX_Type*) NRF_APPMUTEX_S_BASE) 2007 #define NRF_ACL_NS ((NRF_ACL_Type*) NRF_ACL_NS_BASE) 2008 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2009 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2010 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2011 #define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) 2012 2013 /** @} */ /* End of group Device_Peripheral_declaration */ 2014 2015 2016 #ifdef __cplusplus 2017 } 2018 #endif 2019 2020 #endif /* NRF5340_NETWORK_H */ 2021 2022 2023 /** @} */ /* End of group nrf5340_network */ 2024 2025 /** @} */ /* End of group Nordic Semiconductor */ 2026