1 //***************************************************************************** 2 // 3 // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_PWM_H__ 41 #define __HW_PWM_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the PWM register offsets. 46 // 47 //***************************************************************************** 48 #define PWM_O_CTL 0x00000000 // PWM Master Control 49 #define PWM_O_SYNC 0x00000004 // PWM Time Base Sync 50 #define PWM_O_ENABLE 0x00000008 // PWM Output Enable 51 #define PWM_O_INVERT 0x0000000C // PWM Output Inversion 52 #define PWM_O_FAULT 0x00000010 // PWM Output Fault 53 #define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable 54 #define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status 55 #define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear 56 #define PWM_O_STATUS 0x00000020 // PWM Status 57 #define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value 58 #define PWM_O_ENUPD 0x00000028 // PWM Enable Update 59 #define PWM_O_0_CTL 0x00000040 // PWM0 Control 60 #define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger 61 // Enable 62 #define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status 63 #define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear 64 #define PWM_O_0_LOAD 0x00000050 // PWM0 Load 65 #define PWM_O_0_COUNT 0x00000054 // PWM0 Counter 66 #define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A 67 #define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B 68 #define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control 69 #define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control 70 #define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control 71 #define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay 72 #define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band 73 // Falling-Edge-Delay 74 #define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 75 #define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 76 #define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period 77 #define PWM_O_1_CTL 0x00000080 // PWM1 Control 78 #define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger 79 // Enable 80 #define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status 81 #define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear 82 #define PWM_O_1_LOAD 0x00000090 // PWM1 Load 83 #define PWM_O_1_COUNT 0x00000094 // PWM1 Counter 84 #define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A 85 #define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B 86 #define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control 87 #define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control 88 #define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control 89 #define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay 90 #define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band 91 // Falling-Edge-Delay 92 #define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 93 #define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 94 #define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period 95 #define PWM_O_2_CTL 0x000000C0 // PWM2 Control 96 #define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger 97 // Enable 98 #define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status 99 #define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear 100 #define PWM_O_2_LOAD 0x000000D0 // PWM2 Load 101 #define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter 102 #define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A 103 #define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B 104 #define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control 105 #define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control 106 #define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control 107 #define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay 108 #define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band 109 // Falling-Edge-Delay 110 #define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 111 #define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 112 #define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period 113 #define PWM_O_3_CTL 0x00000100 // PWM3 Control 114 #define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger 115 // Enable 116 #define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status 117 #define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear 118 #define PWM_O_3_LOAD 0x00000110 // PWM3 Load 119 #define PWM_O_3_COUNT 0x00000114 // PWM3 Counter 120 #define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A 121 #define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B 122 #define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control 123 #define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control 124 #define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control 125 #define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay 126 #define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band 127 // Falling-Edge-Delay 128 #define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 129 #define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 130 #define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period 131 #define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense 132 #define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 133 #define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 134 #define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense 135 #define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 136 #define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 137 #define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense 138 #define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 139 #define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 140 #define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense 141 #define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 142 #define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 143 #define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties 144 #define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration 145 146 //***************************************************************************** 147 // 148 // The following are defines for the bit fields in the PWM_O_CTL register. 149 // 150 //***************************************************************************** 151 #define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 152 #define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 153 #define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 154 #define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 155 156 //***************************************************************************** 157 // 158 // The following are defines for the bit fields in the PWM_O_SYNC register. 159 // 160 //***************************************************************************** 161 #define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter 162 #define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter 163 #define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter 164 #define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter 165 166 //***************************************************************************** 167 // 168 // The following are defines for the bit fields in the PWM_O_ENABLE register. 169 // 170 //***************************************************************************** 171 #define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable 172 #define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable 173 #define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable 174 #define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable 175 #define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable 176 #define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable 177 #define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable 178 #define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable 179 180 //***************************************************************************** 181 // 182 // The following are defines for the bit fields in the PWM_O_INVERT register. 183 // 184 //***************************************************************************** 185 #define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal 186 #define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal 187 #define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal 188 #define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal 189 #define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal 190 #define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal 191 #define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal 192 #define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal 193 194 //***************************************************************************** 195 // 196 // The following are defines for the bit fields in the PWM_O_FAULT register. 197 // 198 //***************************************************************************** 199 #define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault 200 #define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault 201 #define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault 202 #define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault 203 #define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault 204 #define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault 205 #define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault 206 #define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the PWM_O_INTEN register. 211 // 212 //***************************************************************************** 213 #define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 214 #define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 215 #define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 216 #define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable 217 #define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 218 #define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable 219 #define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable 220 #define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable 221 #define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable 222 223 //***************************************************************************** 224 // 225 // The following are defines for the bit fields in the PWM_O_RIS register. 226 // 227 //***************************************************************************** 228 #define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 229 #define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 230 #define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 231 #define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 232 #define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted 233 #define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted 234 #define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted 235 #define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted 236 #define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted 237 238 //***************************************************************************** 239 // 240 // The following are defines for the bit fields in the PWM_O_ISC register. 241 // 242 //***************************************************************************** 243 #define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted 244 #define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted 245 #define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted 246 #define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted 247 #define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted 248 #define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status 249 #define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status 250 #define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status 251 #define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status 252 253 //***************************************************************************** 254 // 255 // The following are defines for the bit fields in the PWM_O_STATUS register. 256 // 257 //***************************************************************************** 258 #define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status 259 #define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status 260 #define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status 261 #define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status 262 263 //***************************************************************************** 264 // 265 // The following are defines for the bit fields in the PWM_O_FAULTVAL register. 266 // 267 //***************************************************************************** 268 #define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value 269 #define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value 270 #define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value 271 #define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value 272 #define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value 273 #define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value 274 #define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value 275 #define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value 276 277 //***************************************************************************** 278 // 279 // The following are defines for the bit fields in the PWM_O_ENUPD register. 280 // 281 //***************************************************************************** 282 #define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode 283 #define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate 284 #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized 285 #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized 286 #define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode 287 #define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate 288 #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized 289 #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized 290 #define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode 291 #define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate 292 #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized 293 #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized 294 #define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode 295 #define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate 296 #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized 297 #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized 298 #define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode 299 #define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate 300 #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized 301 #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized 302 #define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode 303 #define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate 304 #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized 305 #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized 306 #define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode 307 #define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate 308 #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized 309 #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized 310 #define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode 311 #define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate 312 #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized 313 #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized 314 315 //***************************************************************************** 316 // 317 // The following are defines for the bit fields in the PWM_O_0_CTL register. 318 // 319 //***************************************************************************** 320 #define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input 321 #define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 322 #define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source 323 #define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for 324 // the PWMnDBFALL register 325 #define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate 326 #define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 327 #define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 328 #define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 329 #define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate 330 #define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 331 #define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 332 #define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 333 #define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate 334 #define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 335 #define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 336 #define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 337 #define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate 338 #define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 339 #define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 340 #define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 341 #define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate 342 #define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 343 #define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 344 #define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 345 #define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 346 #define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode 347 #define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode 348 #define PWM_0_CTL_MODE 0x00000002 // Counter Mode 349 #define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable 350 351 //***************************************************************************** 352 // 353 // The following are defines for the bit fields in the PWM_O_0_INTEN register. 354 // 355 //***************************************************************************** 356 #define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B 357 // Down 358 #define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B 359 // Up 360 #define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A 361 // Down 362 #define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A 363 // Up 364 #define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load 365 #define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 366 #define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator 367 // B Down 368 #define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator 369 // B Up 370 #define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator 371 // A Down 372 #define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator 373 // A Up 374 #define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load 375 #define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 376 377 //***************************************************************************** 378 // 379 // The following are defines for the bit fields in the PWM_O_0_RIS register. 380 // 381 //***************************************************************************** 382 #define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 383 // Status 384 #define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 385 #define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 386 // Status 387 #define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 388 #define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 389 #define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 390 391 //***************************************************************************** 392 // 393 // The following are defines for the bit fields in the PWM_O_0_ISC register. 394 // 395 //***************************************************************************** 396 #define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 397 #define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 398 #define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 399 #define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 400 #define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 401 #define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 402 403 //***************************************************************************** 404 // 405 // The following are defines for the bit fields in the PWM_O_0_LOAD register. 406 // 407 //***************************************************************************** 408 #define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value 409 #define PWM_0_LOAD_S 0 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the PWM_O_0_COUNT register. 414 // 415 //***************************************************************************** 416 #define PWM_0_COUNT_M 0x0000FFFF // Counter Value 417 #define PWM_0_COUNT_S 0 418 419 //***************************************************************************** 420 // 421 // The following are defines for the bit fields in the PWM_O_0_CMPA register. 422 // 423 //***************************************************************************** 424 #define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value 425 #define PWM_0_CMPA_S 0 426 427 //***************************************************************************** 428 // 429 // The following are defines for the bit fields in the PWM_O_0_CMPB register. 430 // 431 //***************************************************************************** 432 #define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value 433 #define PWM_0_CMPB_S 0 434 435 //***************************************************************************** 436 // 437 // The following are defines for the bit fields in the PWM_O_0_GENA register. 438 // 439 //***************************************************************************** 440 #define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 441 #define PWM_0_GENA_ACTCMPBD_NONE \ 442 0x00000000 // Do nothing 443 #define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal 444 #define PWM_0_GENA_ACTCMPBD_ZERO \ 445 0x00000800 // Set the output signal to 0 446 #define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 447 #define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 448 #define PWM_0_GENA_ACTCMPBU_NONE \ 449 0x00000000 // Do nothing 450 #define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal 451 #define PWM_0_GENA_ACTCMPBU_ZERO \ 452 0x00000200 // Set the output signal to 0 453 #define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 454 #define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 455 #define PWM_0_GENA_ACTCMPAD_NONE \ 456 0x00000000 // Do nothing 457 #define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal 458 #define PWM_0_GENA_ACTCMPAD_ZERO \ 459 0x00000080 // Set the output signal to 0 460 #define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 461 #define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 462 #define PWM_0_GENA_ACTCMPAU_NONE \ 463 0x00000000 // Do nothing 464 #define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal 465 #define PWM_0_GENA_ACTCMPAU_ZERO \ 466 0x00000020 // Set the output signal to 0 467 #define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 468 #define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load 469 #define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 470 #define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal 471 #define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 472 #define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 473 #define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 474 #define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing 475 #define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal 476 #define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 477 #define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 478 479 //***************************************************************************** 480 // 481 // The following are defines for the bit fields in the PWM_O_0_GENB register. 482 // 483 //***************************************************************************** 484 #define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 485 #define PWM_0_GENB_ACTCMPBD_NONE \ 486 0x00000000 // Do nothing 487 #define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal 488 #define PWM_0_GENB_ACTCMPBD_ZERO \ 489 0x00000800 // Set the output signal to 0 490 #define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 491 #define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 492 #define PWM_0_GENB_ACTCMPBU_NONE \ 493 0x00000000 // Do nothing 494 #define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal 495 #define PWM_0_GENB_ACTCMPBU_ZERO \ 496 0x00000200 // Set the output signal to 0 497 #define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 498 #define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 499 #define PWM_0_GENB_ACTCMPAD_NONE \ 500 0x00000000 // Do nothing 501 #define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal 502 #define PWM_0_GENB_ACTCMPAD_ZERO \ 503 0x00000080 // Set the output signal to 0 504 #define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 505 #define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 506 #define PWM_0_GENB_ACTCMPAU_NONE \ 507 0x00000000 // Do nothing 508 #define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal 509 #define PWM_0_GENB_ACTCMPAU_ZERO \ 510 0x00000020 // Set the output signal to 0 511 #define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 512 #define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load 513 #define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 514 #define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal 515 #define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 516 #define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 517 #define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 518 #define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing 519 #define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal 520 #define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 521 #define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 522 523 //***************************************************************************** 524 // 525 // The following are defines for the bit fields in the PWM_O_0_DBCTL register. 526 // 527 //***************************************************************************** 528 #define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 529 530 //***************************************************************************** 531 // 532 // The following are defines for the bit fields in the PWM_O_0_DBRISE register. 533 // 534 //***************************************************************************** 535 #define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay 536 #define PWM_0_DBRISE_DELAY_S 0 537 538 //***************************************************************************** 539 // 540 // The following are defines for the bit fields in the PWM_O_0_DBFALL register. 541 // 542 //***************************************************************************** 543 #define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay 544 #define PWM_0_DBFALL_DELAY_S 0 545 546 //***************************************************************************** 547 // 548 // The following are defines for the bit fields in the PWM_O_0_FLTSRC0 549 // register. 550 // 551 //***************************************************************************** 552 #define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 553 #define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input 554 #define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input 555 #define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 556 557 //***************************************************************************** 558 // 559 // The following are defines for the bit fields in the PWM_O_0_FLTSRC1 560 // register. 561 // 562 //***************************************************************************** 563 #define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 564 #define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 565 #define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 566 #define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 567 #define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 568 #define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 569 #define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 570 #define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 571 572 //***************************************************************************** 573 // 574 // The following are defines for the bit fields in the PWM_O_0_MINFLTPER 575 // register. 576 // 577 //***************************************************************************** 578 #define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period 579 #define PWM_0_MINFLTPER_S 0 580 581 //***************************************************************************** 582 // 583 // The following are defines for the bit fields in the PWM_O_1_CTL register. 584 // 585 //***************************************************************************** 586 #define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input 587 #define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 588 #define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source 589 #define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for 590 // the PWMnDBFALL register 591 #define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate 592 #define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 593 #define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 594 #define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 595 #define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate 596 #define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 597 #define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 598 #define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 599 #define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate 600 #define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 601 #define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 602 #define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 603 #define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate 604 #define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 605 #define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 606 #define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 607 #define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate 608 #define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 609 #define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 610 #define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 611 #define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 612 #define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode 613 #define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode 614 #define PWM_1_CTL_MODE 0x00000002 // Counter Mode 615 #define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable 616 617 //***************************************************************************** 618 // 619 // The following are defines for the bit fields in the PWM_O_1_INTEN register. 620 // 621 //***************************************************************************** 622 #define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B 623 // Down 624 #define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B 625 // Up 626 #define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A 627 // Down 628 #define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A 629 // Up 630 #define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load 631 #define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 632 #define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator 633 // B Down 634 #define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator 635 // B Up 636 #define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator 637 // A Down 638 #define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator 639 // A Up 640 #define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load 641 #define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 642 643 //***************************************************************************** 644 // 645 // The following are defines for the bit fields in the PWM_O_1_RIS register. 646 // 647 //***************************************************************************** 648 #define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 649 // Status 650 #define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 651 #define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 652 // Status 653 #define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 654 #define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 655 #define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 656 657 //***************************************************************************** 658 // 659 // The following are defines for the bit fields in the PWM_O_1_ISC register. 660 // 661 //***************************************************************************** 662 #define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 663 #define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 664 #define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 665 #define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 666 #define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 667 #define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 668 669 //***************************************************************************** 670 // 671 // The following are defines for the bit fields in the PWM_O_1_LOAD register. 672 // 673 //***************************************************************************** 674 #define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value 675 #define PWM_1_LOAD_LOAD_S 0 676 677 //***************************************************************************** 678 // 679 // The following are defines for the bit fields in the PWM_O_1_COUNT register. 680 // 681 //***************************************************************************** 682 #define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value 683 #define PWM_1_COUNT_COUNT_S 0 684 685 //***************************************************************************** 686 // 687 // The following are defines for the bit fields in the PWM_O_1_CMPA register. 688 // 689 //***************************************************************************** 690 #define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value 691 #define PWM_1_CMPA_COMPA_S 0 692 693 //***************************************************************************** 694 // 695 // The following are defines for the bit fields in the PWM_O_1_CMPB register. 696 // 697 //***************************************************************************** 698 #define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value 699 #define PWM_1_CMPB_COMPB_S 0 700 701 //***************************************************************************** 702 // 703 // The following are defines for the bit fields in the PWM_O_1_GENA register. 704 // 705 //***************************************************************************** 706 #define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 707 #define PWM_1_GENA_ACTCMPBD_NONE \ 708 0x00000000 // Do nothing 709 #define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal 710 #define PWM_1_GENA_ACTCMPBD_ZERO \ 711 0x00000800 // Set the output signal to 0 712 #define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 713 #define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 714 #define PWM_1_GENA_ACTCMPBU_NONE \ 715 0x00000000 // Do nothing 716 #define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal 717 #define PWM_1_GENA_ACTCMPBU_ZERO \ 718 0x00000200 // Set the output signal to 0 719 #define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 720 #define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 721 #define PWM_1_GENA_ACTCMPAD_NONE \ 722 0x00000000 // Do nothing 723 #define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal 724 #define PWM_1_GENA_ACTCMPAD_ZERO \ 725 0x00000080 // Set the output signal to 0 726 #define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 727 #define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 728 #define PWM_1_GENA_ACTCMPAU_NONE \ 729 0x00000000 // Do nothing 730 #define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal 731 #define PWM_1_GENA_ACTCMPAU_ZERO \ 732 0x00000020 // Set the output signal to 0 733 #define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 734 #define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load 735 #define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 736 #define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal 737 #define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 738 #define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 739 #define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 740 #define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing 741 #define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert the output signal 742 #define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 743 #define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 744 745 //***************************************************************************** 746 // 747 // The following are defines for the bit fields in the PWM_O_1_GENB register. 748 // 749 //***************************************************************************** 750 #define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 751 #define PWM_1_GENB_ACTCMPBD_NONE \ 752 0x00000000 // Do nothing 753 #define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal 754 #define PWM_1_GENB_ACTCMPBD_ZERO \ 755 0x00000800 // Set the output signal to 0 756 #define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 757 #define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 758 #define PWM_1_GENB_ACTCMPBU_NONE \ 759 0x00000000 // Do nothing 760 #define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal 761 #define PWM_1_GENB_ACTCMPBU_ZERO \ 762 0x00000200 // Set the output signal to 0 763 #define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 764 #define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 765 #define PWM_1_GENB_ACTCMPAD_NONE \ 766 0x00000000 // Do nothing 767 #define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal 768 #define PWM_1_GENB_ACTCMPAD_ZERO \ 769 0x00000080 // Set the output signal to 0 770 #define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 771 #define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 772 #define PWM_1_GENB_ACTCMPAU_NONE \ 773 0x00000000 // Do nothing 774 #define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal 775 #define PWM_1_GENB_ACTCMPAU_ZERO \ 776 0x00000020 // Set the output signal to 0 777 #define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 778 #define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load 779 #define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 780 #define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal 781 #define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 782 #define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 783 #define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 784 #define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing 785 #define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert the output signal 786 #define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 787 #define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 788 789 //***************************************************************************** 790 // 791 // The following are defines for the bit fields in the PWM_O_1_DBCTL register. 792 // 793 //***************************************************************************** 794 #define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 795 796 //***************************************************************************** 797 // 798 // The following are defines for the bit fields in the PWM_O_1_DBRISE register. 799 // 800 //***************************************************************************** 801 #define PWM_1_DBRISE_RISEDELAY_M \ 802 0x00000FFF // Dead-Band Rise Delay 803 #define PWM_1_DBRISE_RISEDELAY_S \ 804 0 805 806 //***************************************************************************** 807 // 808 // The following are defines for the bit fields in the PWM_O_1_DBFALL register. 809 // 810 //***************************************************************************** 811 #define PWM_1_DBFALL_FALLDELAY_M \ 812 0x00000FFF // Dead-Band Fall Delay 813 #define PWM_1_DBFALL_FALLDELAY_S \ 814 0 815 816 //***************************************************************************** 817 // 818 // The following are defines for the bit fields in the PWM_O_1_FLTSRC0 819 // register. 820 // 821 //***************************************************************************** 822 #define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 823 #define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input 824 #define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input 825 #define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 826 827 //***************************************************************************** 828 // 829 // The following are defines for the bit fields in the PWM_O_1_FLTSRC1 830 // register. 831 // 832 //***************************************************************************** 833 #define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 834 #define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 835 #define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 836 #define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 837 #define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 838 #define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 839 #define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 840 #define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 841 842 //***************************************************************************** 843 // 844 // The following are defines for the bit fields in the PWM_O_1_MINFLTPER 845 // register. 846 // 847 //***************************************************************************** 848 #define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period 849 #define PWM_1_MINFLTPER_MFP_S 0 850 851 //***************************************************************************** 852 // 853 // The following are defines for the bit fields in the PWM_O_2_CTL register. 854 // 855 //***************************************************************************** 856 #define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input 857 #define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 858 #define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source 859 #define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for 860 // the PWMnDBFALL register 861 #define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate 862 #define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 863 #define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 864 #define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 865 #define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate 866 #define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 867 #define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 868 #define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 869 #define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate 870 #define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 871 #define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 872 #define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 873 #define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate 874 #define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 875 #define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 876 #define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 877 #define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate 878 #define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 879 #define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 880 #define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 881 #define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 882 #define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode 883 #define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode 884 #define PWM_2_CTL_MODE 0x00000002 // Counter Mode 885 #define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable 886 887 //***************************************************************************** 888 // 889 // The following are defines for the bit fields in the PWM_O_2_INTEN register. 890 // 891 //***************************************************************************** 892 #define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B 893 // Down 894 #define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B 895 // Up 896 #define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A 897 // Down 898 #define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A 899 // Up 900 #define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load 901 #define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 902 #define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator 903 // B Down 904 #define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator 905 // B Up 906 #define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator 907 // A Down 908 #define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator 909 // A Up 910 #define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load 911 #define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 912 913 //***************************************************************************** 914 // 915 // The following are defines for the bit fields in the PWM_O_2_RIS register. 916 // 917 //***************************************************************************** 918 #define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 919 // Status 920 #define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 921 #define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 922 // Status 923 #define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 924 #define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 925 #define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 926 927 //***************************************************************************** 928 // 929 // The following are defines for the bit fields in the PWM_O_2_ISC register. 930 // 931 //***************************************************************************** 932 #define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 933 #define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 934 #define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 935 #define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 936 #define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 937 #define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 938 939 //***************************************************************************** 940 // 941 // The following are defines for the bit fields in the PWM_O_2_LOAD register. 942 // 943 //***************************************************************************** 944 #define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value 945 #define PWM_2_LOAD_LOAD_S 0 946 947 //***************************************************************************** 948 // 949 // The following are defines for the bit fields in the PWM_O_2_COUNT register. 950 // 951 //***************************************************************************** 952 #define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value 953 #define PWM_2_COUNT_COUNT_S 0 954 955 //***************************************************************************** 956 // 957 // The following are defines for the bit fields in the PWM_O_2_CMPA register. 958 // 959 //***************************************************************************** 960 #define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value 961 #define PWM_2_CMPA_COMPA_S 0 962 963 //***************************************************************************** 964 // 965 // The following are defines for the bit fields in the PWM_O_2_CMPB register. 966 // 967 //***************************************************************************** 968 #define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value 969 #define PWM_2_CMPB_COMPB_S 0 970 971 //***************************************************************************** 972 // 973 // The following are defines for the bit fields in the PWM_O_2_GENA register. 974 // 975 //***************************************************************************** 976 #define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 977 #define PWM_2_GENA_ACTCMPBD_NONE \ 978 0x00000000 // Do nothing 979 #define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal 980 #define PWM_2_GENA_ACTCMPBD_ZERO \ 981 0x00000800 // Set the output signal to 0 982 #define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 983 #define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 984 #define PWM_2_GENA_ACTCMPBU_NONE \ 985 0x00000000 // Do nothing 986 #define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal 987 #define PWM_2_GENA_ACTCMPBU_ZERO \ 988 0x00000200 // Set the output signal to 0 989 #define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 990 #define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 991 #define PWM_2_GENA_ACTCMPAD_NONE \ 992 0x00000000 // Do nothing 993 #define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal 994 #define PWM_2_GENA_ACTCMPAD_ZERO \ 995 0x00000080 // Set the output signal to 0 996 #define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 997 #define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 998 #define PWM_2_GENA_ACTCMPAU_NONE \ 999 0x00000000 // Do nothing 1000 #define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal 1001 #define PWM_2_GENA_ACTCMPAU_ZERO \ 1002 0x00000020 // Set the output signal to 0 1003 #define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 1004 #define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load 1005 #define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 1006 #define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal 1007 #define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 1008 #define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 1009 #define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 1010 #define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing 1011 #define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert the output signal 1012 #define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 1013 #define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 1014 1015 //***************************************************************************** 1016 // 1017 // The following are defines for the bit fields in the PWM_O_2_GENB register. 1018 // 1019 //***************************************************************************** 1020 #define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 1021 #define PWM_2_GENB_ACTCMPBD_NONE \ 1022 0x00000000 // Do nothing 1023 #define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal 1024 #define PWM_2_GENB_ACTCMPBD_ZERO \ 1025 0x00000800 // Set the output signal to 0 1026 #define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 1027 #define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 1028 #define PWM_2_GENB_ACTCMPBU_NONE \ 1029 0x00000000 // Do nothing 1030 #define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal 1031 #define PWM_2_GENB_ACTCMPBU_ZERO \ 1032 0x00000200 // Set the output signal to 0 1033 #define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 1034 #define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 1035 #define PWM_2_GENB_ACTCMPAD_NONE \ 1036 0x00000000 // Do nothing 1037 #define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal 1038 #define PWM_2_GENB_ACTCMPAD_ZERO \ 1039 0x00000080 // Set the output signal to 0 1040 #define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 1041 #define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 1042 #define PWM_2_GENB_ACTCMPAU_NONE \ 1043 0x00000000 // Do nothing 1044 #define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal 1045 #define PWM_2_GENB_ACTCMPAU_ZERO \ 1046 0x00000020 // Set the output signal to 0 1047 #define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 1048 #define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load 1049 #define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 1050 #define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal 1051 #define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 1052 #define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 1053 #define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 1054 #define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing 1055 #define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert the output signal 1056 #define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 1057 #define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 1058 1059 //***************************************************************************** 1060 // 1061 // The following are defines for the bit fields in the PWM_O_2_DBCTL register. 1062 // 1063 //***************************************************************************** 1064 #define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 1065 1066 //***************************************************************************** 1067 // 1068 // The following are defines for the bit fields in the PWM_O_2_DBRISE register. 1069 // 1070 //***************************************************************************** 1071 #define PWM_2_DBRISE_RISEDELAY_M \ 1072 0x00000FFF // Dead-Band Rise Delay 1073 #define PWM_2_DBRISE_RISEDELAY_S \ 1074 0 1075 1076 //***************************************************************************** 1077 // 1078 // The following are defines for the bit fields in the PWM_O_2_DBFALL register. 1079 // 1080 //***************************************************************************** 1081 #define PWM_2_DBFALL_FALLDELAY_M \ 1082 0x00000FFF // Dead-Band Fall Delay 1083 #define PWM_2_DBFALL_FALLDELAY_S \ 1084 0 1085 1086 //***************************************************************************** 1087 // 1088 // The following are defines for the bit fields in the PWM_O_2_FLTSRC0 1089 // register. 1090 // 1091 //***************************************************************************** 1092 #define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 1093 #define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input 1094 #define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input 1095 #define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 1096 1097 //***************************************************************************** 1098 // 1099 // The following are defines for the bit fields in the PWM_O_2_FLTSRC1 1100 // register. 1101 // 1102 //***************************************************************************** 1103 #define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 1104 #define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 1105 #define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 1106 #define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 1107 #define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 1108 #define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 1109 #define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 1110 #define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 1111 1112 //***************************************************************************** 1113 // 1114 // The following are defines for the bit fields in the PWM_O_2_MINFLTPER 1115 // register. 1116 // 1117 //***************************************************************************** 1118 #define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period 1119 #define PWM_2_MINFLTPER_MFP_S 0 1120 1121 //***************************************************************************** 1122 // 1123 // The following are defines for the bit fields in the PWM_O_3_CTL register. 1124 // 1125 //***************************************************************************** 1126 #define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input 1127 #define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 1128 #define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source 1129 #define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for 1130 // the PWMnDBFALL register 1131 #define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate 1132 #define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 1133 #define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 1134 #define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 1135 #define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate 1136 #define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 1137 #define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 1138 #define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 1139 #define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate 1140 #define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 1141 #define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 1142 #define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 1143 #define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate 1144 #define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 1145 #define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 1146 #define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 1147 #define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate 1148 #define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 1149 #define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 1150 #define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 1151 #define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 1152 #define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode 1153 #define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode 1154 #define PWM_3_CTL_MODE 0x00000002 // Counter Mode 1155 #define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable 1156 1157 //***************************************************************************** 1158 // 1159 // The following are defines for the bit fields in the PWM_O_3_INTEN register. 1160 // 1161 //***************************************************************************** 1162 #define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B 1163 // Down 1164 #define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B 1165 // Up 1166 #define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A 1167 // Down 1168 #define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A 1169 // Up 1170 #define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load 1171 #define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 1172 #define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator 1173 // B Down 1174 #define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator 1175 // B Up 1176 #define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator 1177 // A Down 1178 #define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator 1179 // A Up 1180 #define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load 1181 #define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 1182 1183 //***************************************************************************** 1184 // 1185 // The following are defines for the bit fields in the PWM_O_3_RIS register. 1186 // 1187 //***************************************************************************** 1188 #define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 1189 // Status 1190 #define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 1191 #define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 1192 // Status 1193 #define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 1194 #define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 1195 #define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 1196 1197 //***************************************************************************** 1198 // 1199 // The following are defines for the bit fields in the PWM_O_3_ISC register. 1200 // 1201 //***************************************************************************** 1202 #define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 1203 #define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 1204 #define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 1205 #define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 1206 #define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 1207 #define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 1208 1209 //***************************************************************************** 1210 // 1211 // The following are defines for the bit fields in the PWM_O_3_LOAD register. 1212 // 1213 //***************************************************************************** 1214 #define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value 1215 #define PWM_3_LOAD_LOAD_S 0 1216 1217 //***************************************************************************** 1218 // 1219 // The following are defines for the bit fields in the PWM_O_3_COUNT register. 1220 // 1221 //***************************************************************************** 1222 #define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value 1223 #define PWM_3_COUNT_COUNT_S 0 1224 1225 //***************************************************************************** 1226 // 1227 // The following are defines for the bit fields in the PWM_O_3_CMPA register. 1228 // 1229 //***************************************************************************** 1230 #define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value 1231 #define PWM_3_CMPA_COMPA_S 0 1232 1233 //***************************************************************************** 1234 // 1235 // The following are defines for the bit fields in the PWM_O_3_CMPB register. 1236 // 1237 //***************************************************************************** 1238 #define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value 1239 #define PWM_3_CMPB_COMPB_S 0 1240 1241 //***************************************************************************** 1242 // 1243 // The following are defines for the bit fields in the PWM_O_3_GENA register. 1244 // 1245 //***************************************************************************** 1246 #define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 1247 #define PWM_3_GENA_ACTCMPBD_NONE \ 1248 0x00000000 // Do nothing 1249 #define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal 1250 #define PWM_3_GENA_ACTCMPBD_ZERO \ 1251 0x00000800 // Set the output signal to 0 1252 #define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 1253 #define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 1254 #define PWM_3_GENA_ACTCMPBU_NONE \ 1255 0x00000000 // Do nothing 1256 #define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal 1257 #define PWM_3_GENA_ACTCMPBU_ZERO \ 1258 0x00000200 // Set the output signal to 0 1259 #define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 1260 #define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 1261 #define PWM_3_GENA_ACTCMPAD_NONE \ 1262 0x00000000 // Do nothing 1263 #define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal 1264 #define PWM_3_GENA_ACTCMPAD_ZERO \ 1265 0x00000080 // Set the output signal to 0 1266 #define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 1267 #define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 1268 #define PWM_3_GENA_ACTCMPAU_NONE \ 1269 0x00000000 // Do nothing 1270 #define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal 1271 #define PWM_3_GENA_ACTCMPAU_ZERO \ 1272 0x00000020 // Set the output signal to 0 1273 #define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 1274 #define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load 1275 #define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 1276 #define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal 1277 #define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 1278 #define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 1279 #define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 1280 #define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing 1281 #define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert the output signal 1282 #define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 1283 #define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 1284 1285 //***************************************************************************** 1286 // 1287 // The following are defines for the bit fields in the PWM_O_3_GENB register. 1288 // 1289 //***************************************************************************** 1290 #define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 1291 #define PWM_3_GENB_ACTCMPBD_NONE \ 1292 0x00000000 // Do nothing 1293 #define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal 1294 #define PWM_3_GENB_ACTCMPBD_ZERO \ 1295 0x00000800 // Set the output signal to 0 1296 #define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 1297 #define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 1298 #define PWM_3_GENB_ACTCMPBU_NONE \ 1299 0x00000000 // Do nothing 1300 #define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal 1301 #define PWM_3_GENB_ACTCMPBU_ZERO \ 1302 0x00000200 // Set the output signal to 0 1303 #define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 1304 #define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 1305 #define PWM_3_GENB_ACTCMPAD_NONE \ 1306 0x00000000 // Do nothing 1307 #define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal 1308 #define PWM_3_GENB_ACTCMPAD_ZERO \ 1309 0x00000080 // Set the output signal to 0 1310 #define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 1311 #define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 1312 #define PWM_3_GENB_ACTCMPAU_NONE \ 1313 0x00000000 // Do nothing 1314 #define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal 1315 #define PWM_3_GENB_ACTCMPAU_ZERO \ 1316 0x00000020 // Set the output signal to 0 1317 #define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 1318 #define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load 1319 #define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 1320 #define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal 1321 #define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 1322 #define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 1323 #define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 1324 #define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing 1325 #define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert the output signal 1326 #define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 1327 #define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 1328 1329 //***************************************************************************** 1330 // 1331 // The following are defines for the bit fields in the PWM_O_3_DBCTL register. 1332 // 1333 //***************************************************************************** 1334 #define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 1335 1336 //***************************************************************************** 1337 // 1338 // The following are defines for the bit fields in the PWM_O_3_DBRISE register. 1339 // 1340 //***************************************************************************** 1341 #define PWM_3_DBRISE_RISEDELAY_M \ 1342 0x00000FFF // Dead-Band Rise Delay 1343 #define PWM_3_DBRISE_RISEDELAY_S \ 1344 0 1345 1346 //***************************************************************************** 1347 // 1348 // The following are defines for the bit fields in the PWM_O_3_DBFALL register. 1349 // 1350 //***************************************************************************** 1351 #define PWM_3_DBFALL_FALLDELAY_M \ 1352 0x00000FFF // Dead-Band Fall Delay 1353 #define PWM_3_DBFALL_FALLDELAY_S \ 1354 0 1355 1356 //***************************************************************************** 1357 // 1358 // The following are defines for the bit fields in the PWM_O_3_FLTSRC0 1359 // register. 1360 // 1361 //***************************************************************************** 1362 #define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 1363 #define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 1364 #define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 1365 #define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 1366 1367 //***************************************************************************** 1368 // 1369 // The following are defines for the bit fields in the PWM_O_3_FLTSRC1 1370 // register. 1371 // 1372 //***************************************************************************** 1373 #define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 1374 #define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 1375 #define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 1376 #define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 1377 #define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 1378 #define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 1379 #define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 1380 #define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 1381 1382 //***************************************************************************** 1383 // 1384 // The following are defines for the bit fields in the PWM_O_3_MINFLTPER 1385 // register. 1386 // 1387 //***************************************************************************** 1388 #define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period 1389 #define PWM_3_MINFLTPER_MFP_S 0 1390 1391 //***************************************************************************** 1392 // 1393 // The following are defines for the bit fields in the PWM_O_0_FLTSEN register. 1394 // 1395 //***************************************************************************** 1396 #define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 1397 #define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 1398 #define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 1399 #define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 1400 1401 //***************************************************************************** 1402 // 1403 // The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 1404 // register. 1405 // 1406 //***************************************************************************** 1407 #define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 1408 #define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 1409 #define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 1410 #define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 1411 1412 //***************************************************************************** 1413 // 1414 // The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 1415 // register. 1416 // 1417 //***************************************************************************** 1418 #define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 1419 #define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 1420 #define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 1421 #define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 1422 #define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 1423 #define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 1424 #define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 1425 #define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 1426 1427 //***************************************************************************** 1428 // 1429 // The following are defines for the bit fields in the PWM_O_1_FLTSEN register. 1430 // 1431 //***************************************************************************** 1432 #define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 1433 #define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 1434 #define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 1435 #define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 1436 1437 //***************************************************************************** 1438 // 1439 // The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 1440 // register. 1441 // 1442 //***************************************************************************** 1443 #define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 1444 #define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 1445 #define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 1446 #define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 1447 1448 //***************************************************************************** 1449 // 1450 // The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 1451 // register. 1452 // 1453 //***************************************************************************** 1454 #define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 1455 #define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 1456 #define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 1457 #define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 1458 #define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 1459 #define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 1460 #define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 1461 #define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 1462 1463 //***************************************************************************** 1464 // 1465 // The following are defines for the bit fields in the PWM_O_2_FLTSEN register. 1466 // 1467 //***************************************************************************** 1468 #define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 1469 #define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 1470 #define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 1471 #define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 1472 1473 //***************************************************************************** 1474 // 1475 // The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 1476 // register. 1477 // 1478 //***************************************************************************** 1479 #define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 1480 #define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 1481 #define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 1482 #define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 1483 1484 //***************************************************************************** 1485 // 1486 // The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 1487 // register. 1488 // 1489 //***************************************************************************** 1490 #define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 1491 #define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 1492 #define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 1493 #define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 1494 #define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 1495 #define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 1496 #define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 1497 #define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 1498 1499 //***************************************************************************** 1500 // 1501 // The following are defines for the bit fields in the PWM_O_3_FLTSEN register. 1502 // 1503 //***************************************************************************** 1504 #define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 1505 #define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 1506 #define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 1507 #define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 1508 1509 //***************************************************************************** 1510 // 1511 // The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 1512 // register. 1513 // 1514 //***************************************************************************** 1515 #define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 1516 #define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 1517 #define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 1518 #define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 1519 1520 //***************************************************************************** 1521 // 1522 // The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 1523 // register. 1524 // 1525 //***************************************************************************** 1526 #define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 1527 #define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 1528 #define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 1529 #define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 1530 #define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 1531 #define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 1532 #define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 1533 #define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 1534 1535 //***************************************************************************** 1536 // 1537 // The following are defines for the bit fields in the PWM_O_PP register. 1538 // 1539 //***************************************************************************** 1540 #define PWM_PP_GCNT_M 0x0000000F // Generators 1541 #define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs 1542 #define PWM_PP_ESYNC 0x00000100 // Extended Synchronization 1543 #define PWM_PP_EFAULT 0x00000200 // Extended Fault 1544 #define PWM_PP_ONE 0x00000400 // One-Shot Mode 1545 #define PWM_PP_GCNT_S 0 1546 #define PWM_PP_FCNT_S 4 1547 1548 //***************************************************************************** 1549 // 1550 // The following are defines for the bit fields in the PWM_O_PC register. 1551 // 1552 //***************************************************************************** 1553 #define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor 1554 #define PWM_PC_PWMDIV_2 0x00000000 // /2 1555 #define PWM_PC_PWMDIV_4 0x00000001 // /4 1556 #define PWM_PC_PWMDIV_8 0x00000002 // /8 1557 #define PWM_PC_PWMDIV_16 0x00000003 // /16 1558 #define PWM_PC_PWMDIV_32 0x00000004 // /32 1559 #define PWM_PC_PWMDIV_64 0x00000007 // /64 (default) 1560 #define PWM_PC_USEPWMDIV 0x00000100 // Enable PWM Clock Divisor 1561 1562 //***************************************************************************** 1563 // 1564 // The following are defines for the PWM Generator standard offsets. 1565 // 1566 //***************************************************************************** 1567 #define PWM_O_X_CTL 0x00000000 // Gen Control Reg 1568 #define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg 1569 #define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg 1570 #define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg 1571 #define PWM_O_X_LOAD 0x00000010 // Gen Load Reg 1572 #define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg 1573 #define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg 1574 #define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg 1575 #define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg 1576 #define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg 1577 #define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg 1578 #define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg 1579 #define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg 1580 #define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition 1581 #define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition 1582 #define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension 1583 #define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base 1584 #define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base 1585 #define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base 1586 #define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base 1587 1588 //***************************************************************************** 1589 // 1590 // The following are defines for the bit fields in the PWM_O_X_CTL register. 1591 // 1592 //***************************************************************************** 1593 #define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input 1594 #define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 1595 #define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source 1596 #define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode 1597 #define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate 1598 #define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 1599 #define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 1600 #define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 1601 #define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate 1602 #define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 1603 #define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 1604 #define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 1605 #define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate 1606 #define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 1607 #define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 1608 #define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 1609 #define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate 1610 #define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 1611 #define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 1612 #define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 1613 #define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate 1614 #define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 1615 #define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 1616 #define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 1617 #define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 1618 #define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode 1619 #define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode 1620 #define PWM_X_CTL_MODE 0x00000002 // Counter Mode 1621 #define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable 1622 1623 //***************************************************************************** 1624 // 1625 // The following are defines for the bit fields in the PWM_O_X_INTEN register. 1626 // 1627 //***************************************************************************** 1628 #define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB 1629 // Down 1630 #define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up 1631 #define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA 1632 // Down 1633 #define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up 1634 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD 1635 #define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 1636 #define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB 1637 // Down 1638 #define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB 1639 // Up 1640 #define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA 1641 // Down 1642 #define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA 1643 // Up 1644 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD 1645 #define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 1646 1647 //***************************************************************************** 1648 // 1649 // The following are defines for the bit fields in the PWM_O_X_RIS register. 1650 // 1651 //***************************************************************************** 1652 #define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 1653 // Status 1654 #define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 1655 #define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 1656 // Status 1657 #define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 1658 #define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 1659 #define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 1660 1661 //***************************************************************************** 1662 // 1663 // The following are defines for the bit fields in the PWM_O_X_ISC register. 1664 // 1665 //***************************************************************************** 1666 #define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 1667 #define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 1668 #define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 1669 #define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 1670 #define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 1671 #define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 1672 1673 //***************************************************************************** 1674 // 1675 // The following are defines for the bit fields in the PWM_O_X_LOAD register. 1676 // 1677 //***************************************************************************** 1678 #define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value 1679 #define PWM_X_LOAD_S 0 1680 1681 //***************************************************************************** 1682 // 1683 // The following are defines for the bit fields in the PWM_O_X_COUNT register. 1684 // 1685 //***************************************************************************** 1686 #define PWM_X_COUNT_M 0x0000FFFF // Counter Value 1687 #define PWM_X_COUNT_S 0 1688 1689 //***************************************************************************** 1690 // 1691 // The following are defines for the bit fields in the PWM_O_X_CMPA register. 1692 // 1693 //***************************************************************************** 1694 #define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value 1695 #define PWM_X_CMPA_S 0 1696 1697 //***************************************************************************** 1698 // 1699 // The following are defines for the bit fields in the PWM_O_X_CMPB register. 1700 // 1701 //***************************************************************************** 1702 #define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value 1703 #define PWM_X_CMPB_S 0 1704 1705 //***************************************************************************** 1706 // 1707 // The following are defines for the bit fields in the PWM_O_X_GENA register. 1708 // 1709 //***************************************************************************** 1710 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 1711 #define PWM_X_GENA_ACTCMPBD_NONE \ 1712 0x00000000 // Do nothing 1713 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA 1714 #define PWM_X_GENA_ACTCMPBD_ZERO \ 1715 0x00000800 // Drive pwmA Low 1716 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High 1717 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 1718 #define PWM_X_GENA_ACTCMPBU_NONE \ 1719 0x00000000 // Do nothing 1720 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA 1721 #define PWM_X_GENA_ACTCMPBU_ZERO \ 1722 0x00000200 // Drive pwmA Low 1723 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High 1724 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 1725 #define PWM_X_GENA_ACTCMPAD_NONE \ 1726 0x00000000 // Do nothing 1727 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA 1728 #define PWM_X_GENA_ACTCMPAD_ZERO \ 1729 0x00000080 // Drive pwmA Low 1730 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High 1731 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 1732 #define PWM_X_GENA_ACTCMPAU_NONE \ 1733 0x00000000 // Do nothing 1734 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA 1735 #define PWM_X_GENA_ACTCMPAU_ZERO \ 1736 0x00000020 // Drive pwmA Low 1737 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High 1738 #define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD 1739 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 1740 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA 1741 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low 1742 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High 1743 #define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 1744 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing 1745 #define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA 1746 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low 1747 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High 1748 1749 //***************************************************************************** 1750 // 1751 // The following are defines for the bit fields in the PWM_O_X_GENB register. 1752 // 1753 //***************************************************************************** 1754 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 1755 #define PWM_X_GENB_ACTCMPBD_NONE \ 1756 0x00000000 // Do nothing 1757 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB 1758 #define PWM_X_GENB_ACTCMPBD_ZERO \ 1759 0x00000800 // Drive pwmB Low 1760 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High 1761 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 1762 #define PWM_X_GENB_ACTCMPBU_NONE \ 1763 0x00000000 // Do nothing 1764 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB 1765 #define PWM_X_GENB_ACTCMPBU_ZERO \ 1766 0x00000200 // Drive pwmB Low 1767 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High 1768 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 1769 #define PWM_X_GENB_ACTCMPAD_NONE \ 1770 0x00000000 // Do nothing 1771 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB 1772 #define PWM_X_GENB_ACTCMPAD_ZERO \ 1773 0x00000080 // Drive pwmB Low 1774 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High 1775 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 1776 #define PWM_X_GENB_ACTCMPAU_NONE \ 1777 0x00000000 // Do nothing 1778 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB 1779 #define PWM_X_GENB_ACTCMPAU_ZERO \ 1780 0x00000020 // Drive pwmB Low 1781 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High 1782 #define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD 1783 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 1784 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB 1785 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low 1786 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High 1787 #define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 1788 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing 1789 #define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB 1790 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low 1791 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High 1792 1793 //***************************************************************************** 1794 // 1795 // The following are defines for the bit fields in the PWM_O_X_DBCTL register. 1796 // 1797 //***************************************************************************** 1798 #define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 1799 1800 //***************************************************************************** 1801 // 1802 // The following are defines for the bit fields in the PWM_O_X_DBRISE register. 1803 // 1804 //***************************************************************************** 1805 #define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay 1806 #define PWM_X_DBRISE_DELAY_S 0 1807 1808 //***************************************************************************** 1809 // 1810 // The following are defines for the bit fields in the PWM_O_X_DBFALL register. 1811 // 1812 //***************************************************************************** 1813 #define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay 1814 #define PWM_X_DBFALL_DELAY_S 0 1815 1816 //***************************************************************************** 1817 // 1818 // The following are defines for the bit fields in the PWM_O_X_FLTSRC0 1819 // register. 1820 // 1821 //***************************************************************************** 1822 #define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 1823 #define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input 1824 #define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input 1825 #define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input 1826 1827 //***************************************************************************** 1828 // 1829 // The following are defines for the bit fields in the PWM_O_X_FLTSRC1 1830 // register. 1831 // 1832 //***************************************************************************** 1833 #define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 1834 #define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 1835 #define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 1836 #define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 1837 #define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 1838 #define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 1839 #define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 1840 #define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 1841 1842 //***************************************************************************** 1843 // 1844 // The following are defines for the bit fields in the PWM_O_X_MINFLTPER 1845 // register. 1846 // 1847 //***************************************************************************** 1848 #define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period 1849 #define PWM_X_MINFLTPER_S 0 1850 1851 //***************************************************************************** 1852 // 1853 // The following are defines for the PWM Generator extended offsets. 1854 // 1855 //***************************************************************************** 1856 #define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense 1857 #define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status 1858 #define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status 1859 #define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base 1860 #define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base 1861 #define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base 1862 #define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base 1863 1864 //***************************************************************************** 1865 // 1866 // The following are defines for the bit fields in the PWM_O_X_FLTSEN register. 1867 // 1868 //***************************************************************************** 1869 #define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 1870 #define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 1871 #define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 1872 #define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 1873 1874 //***************************************************************************** 1875 // 1876 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 1877 // register. 1878 // 1879 //***************************************************************************** 1880 #define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 1881 #define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 1882 #define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 1883 #define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 1884 1885 //***************************************************************************** 1886 // 1887 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 1888 // register. 1889 // 1890 //***************************************************************************** 1891 #define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 1892 #define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 1893 #define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 1894 #define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 1895 #define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 1896 #define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 1897 #define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 1898 #define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 1899 1900 //***************************************************************************** 1901 // 1902 // The following definitions are deprecated. 1903 // 1904 //***************************************************************************** 1905 #ifndef DEPRECATED 1906 1907 //***************************************************************************** 1908 // 1909 // The following are deprecated defines for the bit fields in the PWM_O_CTL 1910 // register. 1911 // 1912 //***************************************************************************** 1913 #define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 1914 #define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 1915 #define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 1916 1917 //***************************************************************************** 1918 // 1919 // The following are deprecated defines for the bit fields in the PWM_O_STATUS 1920 // register. 1921 // 1922 //***************************************************************************** 1923 #define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status 1924 1925 //***************************************************************************** 1926 // 1927 // The following are deprecated defines for the PWM Interrupt Register bit 1928 // definitions. 1929 // 1930 //***************************************************************************** 1931 #define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending 1932 1933 //***************************************************************************** 1934 // 1935 // The following are deprecated defines for the PWM_X Interrupt Status Register 1936 // bit definitions. 1937 // 1938 //***************************************************************************** 1939 #define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd 1940 #define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd 1941 #define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd 1942 #define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd 1943 #define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd 1944 #define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received 1945 1946 //***************************************************************************** 1947 // 1948 // The following are deprecated defines for the PWM_X Generator A/B Control 1949 // Register bit definitions. 1950 // 1951 //***************************************************************************** 1952 #define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D 1953 #define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U 1954 #define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D 1955 #define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U 1956 #define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD 1957 #define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 1958 1959 //***************************************************************************** 1960 // 1961 // The following are deprecated defines for the PWM_X Generator A/B Control 1962 // Register action definitions. 1963 // 1964 //***************************************************************************** 1965 #define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one 1966 #define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero 1967 #define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal 1968 #define PWM_GEN_ACT_NONE 0x00000000 // Do nothing 1969 #define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action 1970 #define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action 1971 #define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action 1972 #define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action 1973 #define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action 1974 #define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action 1975 1976 //***************************************************************************** 1977 // 1978 // The following are deprecated defines for the PWM_X Dead Band Control 1979 // Register bit definitions. 1980 // 1981 //***************************************************************************** 1982 #define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion 1983 1984 //***************************************************************************** 1985 // 1986 // The following are deprecated defines for the PWM Register reset values. 1987 // 1988 //***************************************************************************** 1989 #define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator 1990 #define PWM_RV_STATUS 0x00000000 // Status 1991 #define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing 1992 #define PWM_RV_X_RIS 0x00000000 // Raw interrupt status 1993 #define PWM_RV_X_CTL 0x00000000 // Master control of the PWM 1994 // generator block 1995 #define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators 1996 #define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay 1997 // count 1998 #define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable 1999 #define PWM_RV_X_LOAD 0x00000000 // The load value for the counter 2000 #define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A 2001 #define PWM_RV_CTL 0x00000000 // Master control of the PWM module 2002 #define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM 2003 // output pins 2004 #define PWM_RV_RIS 0x00000000 // Raw interrupt status 2005 #define PWM_RV_X_CMPA 0x00000000 // The comparator A value 2006 #define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output 2007 // pins 2008 #define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay 2009 // count 2010 #define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output 2011 // pins 2012 #define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B 2013 #define PWM_RV_X_CMPB 0x00000000 // The comparator B value 2014 #define PWM_RV_ISC 0x00000000 // Interrupt status and clearing 2015 #define PWM_RV_INTEN 0x00000000 // Interrupt enable 2016 #define PWM_RV_X_COUNT 0x00000000 // The current counter value 2017 2018 #endif 2019 2020 #endif // __HW_PWM_H__ 2021