1 //*****************************************************************************
2 //
3 // hw_qei.h - Macros used when accessing the QEI hardware.
4 //
5 // Copyright (c) 2005-2012 Texas Instruments Incorporated.  All rights reserved.
6 // Software License Agreement
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35 //
36 // This is part of revision 9453 of the Stellaris Firmware Development Package.
37 //
38 //*****************************************************************************
39 
40 #ifndef __HW_QEI_H__
41 #define __HW_QEI_H__
42 
43 //*****************************************************************************
44 //
45 // The following are defines for the QEI register offsets.
46 //
47 //*****************************************************************************
48 #define QEI_O_CTL               0x00000000  // QEI Control
49 #define QEI_O_STAT              0x00000004  // QEI Status
50 #define QEI_O_POS               0x00000008  // QEI Position
51 #define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
52 #define QEI_O_LOAD              0x00000010  // QEI Timer Load
53 #define QEI_O_TIME              0x00000014  // QEI Timer
54 #define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
55 #define QEI_O_SPEED             0x0000001C  // QEI Velocity
56 #define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
57 #define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
58 #define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
59 
60 //*****************************************************************************
61 //
62 // The following are defines for the bit fields in the QEI_O_CTL register.
63 //
64 //*****************************************************************************
65 #define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
66 #define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
67 #define QEI_CTL_STALLEN         0x00001000  // Stall QEI
68 #define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
69 #define QEI_CTL_INVB            0x00000400  // Invert PhB
70 #define QEI_CTL_INVA            0x00000200  // Invert PhA
71 #define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
72 #define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
73 #define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
74 #define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
75 #define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
76 #define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
77 #define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
78 #define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
79 #define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
80 #define QEI_CTL_VELEN           0x00000020  // Capture Velocity
81 #define QEI_CTL_RESMODE         0x00000010  // Reset Mode
82 #define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
83 #define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
84 #define QEI_CTL_SWAP            0x00000002  // Swap Signals
85 #define QEI_CTL_ENABLE          0x00000001  // Enable QEI
86 #define QEI_CTL_FILTCNT_S       16
87 
88 //*****************************************************************************
89 //
90 // The following are defines for the bit fields in the QEI_O_STAT register.
91 //
92 //*****************************************************************************
93 #define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
94 #define QEI_STAT_ERROR          0x00000001  // Error Detected
95 
96 //*****************************************************************************
97 //
98 // The following are defines for the bit fields in the QEI_O_POS register.
99 //
100 //*****************************************************************************
101 #define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
102                                             // Value
103 #define QEI_POS_S               0
104 
105 //*****************************************************************************
106 //
107 // The following are defines for the bit fields in the QEI_O_MAXPOS register.
108 //
109 //*****************************************************************************
110 #define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
111                                             // Value
112 #define QEI_MAXPOS_S            0
113 
114 //*****************************************************************************
115 //
116 // The following are defines for the bit fields in the QEI_O_LOAD register.
117 //
118 //*****************************************************************************
119 #define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
120 #define QEI_LOAD_S              0
121 
122 //*****************************************************************************
123 //
124 // The following are defines for the bit fields in the QEI_O_TIME register.
125 //
126 //*****************************************************************************
127 #define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
128 #define QEI_TIME_S              0
129 
130 //*****************************************************************************
131 //
132 // The following are defines for the bit fields in the QEI_O_COUNT register.
133 //
134 //*****************************************************************************
135 #define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
136 #define QEI_COUNT_S             0
137 
138 //*****************************************************************************
139 //
140 // The following are defines for the bit fields in the QEI_O_SPEED register.
141 //
142 //*****************************************************************************
143 #define QEI_SPEED_M             0xFFFFFFFF  // Velocity
144 #define QEI_SPEED_S             0
145 
146 //*****************************************************************************
147 //
148 // The following are defines for the bit fields in the QEI_O_INTEN register.
149 //
150 //*****************************************************************************
151 #define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
152 #define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
153                                             // Enable
154 #define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
155 #define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
156                                             // Enable
157 
158 //*****************************************************************************
159 //
160 // The following are defines for the bit fields in the QEI_O_RIS register.
161 //
162 //*****************************************************************************
163 #define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
164 #define QEI_RIS_DIR             0x00000004  // Direction Change Detected
165 #define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
166 #define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
167 
168 //*****************************************************************************
169 //
170 // The following are defines for the bit fields in the QEI_O_ISC register.
171 //
172 //*****************************************************************************
173 #define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
174 #define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
175 #define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
176 #define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
177 
178 //*****************************************************************************
179 //
180 // The following definitions are deprecated.
181 //
182 //*****************************************************************************
183 #ifndef DEPRECATED
184 
185 //*****************************************************************************
186 //
187 // The following are deprecated defines for the bit fields in the QEI_ISC
188 // register.
189 //
190 //*****************************************************************************
191 #define QEI_INT_ERROR           0x00000008  // Phase error detected
192 #define QEI_INT_DIR             0x00000004  // Direction change
193 #define QEI_INT_TIMER           0x00000002  // Velocity timer expired
194 #define QEI_INT_INDEX           0x00000001  // Index pulse detected
195 
196 //*****************************************************************************
197 //
198 // The following are deprecated defines for the reset values for the QEI
199 // registers.
200 //
201 //*****************************************************************************
202 #define QEI_RV_POS              0x00000000  // Current position register
203 #define QEI_RV_LOAD             0x00000000  // Velocity timer load register
204 #define QEI_RV_CTL              0x00000000  // Configuration and control reg
205 #define QEI_RV_RIS              0x00000000  // Raw interrupt status register
206 #define QEI_RV_ISC              0x00000000  // Interrupt status register
207 #define QEI_RV_SPEED            0x00000000  // Velocity speed register
208 #define QEI_RV_INTEN            0x00000000  // Interrupt enable register
209 #define QEI_RV_STAT             0x00000000  // Status register
210 #define QEI_RV_COUNT            0x00000000  // Velocity pulse count register
211 #define QEI_RV_MAXPOS           0x00000000  // Maximum position register
212 #define QEI_RV_TIME             0x00000000  // Velocity timer register
213 
214 #endif
215 
216 #endif // __HW_QEI_H__
217