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Searched refs:REG32 (Results 1 – 25 of 31) sorted by relevance

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/lk-master/platform/armemu/
A Ddebug.c36 *REG32(DEBUG_REGDUMP) = 1; in debug_dump_regs()
40 *REG32(DEBUG_HALT) = 1; in platform_halt()
45 *REG32(DEBUG_MEMDUMPADDR) = (unsigned int)mem; in debug_dump_memory_bytes()
46 *REG32(DEBUG_MEMDUMPLEN) = len; in debug_dump_memory_bytes()
47 *REG32(DEBUG_MEMDUMP_BYTE) = 1; in debug_dump_memory_bytes()
53 *REG32(DEBUG_MEMDUMPADDR) = (unsigned int)mem; in debug_dump_memory_halfwords()
54 *REG32(DEBUG_MEMDUMPLEN) = len; in debug_dump_memory_halfwords()
55 *REG32(DEBUG_MEMDUMP_HALFWORD) = 1; in debug_dump_memory_halfwords()
62 *REG32(DEBUG_MEMDUMPLEN) = len; in debug_dump_memory_words()
63 *REG32(DEBUG_MEMDUMP_WORD) = 1; in debug_dump_memory_words()
[all …]
A Dblkdev.c23 *REG32(BDEV_CMD_ADDR) = (uint32_t)buf; in read_block()
25 *REG32(BDEV_CMD_LEN) = count * dev->block_size; in read_block()
27 *REG32(BDEV_CMD) = BDEV_CMD_READ; in read_block()
29 uint32_t err = *REG32(BDEV_CMD) & BDEV_CMD_ERRMASK; in read_block()
38 *REG32(BDEV_CMD_ADDR) = (uint32_t)buf; in write_block()
40 *REG32(BDEV_CMD_LEN) = count * dev->block_size; in write_block()
42 *REG32(BDEV_CMD) = BDEV_CMD_WRITE; in write_block()
44 uint32_t err = *REG32(BDEV_CMD) & BDEV_CMD_ERRMASK; in write_block()
54 if ((*REG32(SYSINFO_FEATURES) & SYSINFO_FEATURE_BLOCKDEV) == 0) in platform_init_blkdev()
A Dinterrupts.c29 *REG32(PIC_MASK_LATCH) = 0xffffffff; in platform_init_interrupts()
38 *REG32(PIC_MASK_LATCH) = 1 << vector; in mask_interrupt()
49 *REG32(PIC_UNMASK_LATCH) = 1 << vector; in unmask_interrupt()
56 unsigned int vector = *REG32(PIC_CURRENT_NUM); in platform_irq()
A Ddisplay.c25 return *REG32(SYSINFO_FEATURES) & SYSINFO_FEATURE_DISPLAY; in has_display()
33 display_w = *REG32(DISPLAY_WIDTH); in platform_init_display()
34 display_h = *REG32(DISPLAY_HEIGHT); in platform_init_display()
/lk-master/platform/zynq/
A Dgpio.c36 uint32_t mask = *REG32(GPIO_INT_MASK(bank)); in gpio_int_handler()
37 uint32_t stat = *REG32(GPIO_INT_STAT(bank)); in gpio_int_handler()
57 *REG32(GPIO_INT_STAT(bank)) = stat; in gpio_int_handler()
122 *REG32(GPIO_OEN(bank)) = 0x00000000; in zynq_gpio_init()
123 *REG32(GPIO_DIRM(bank)) = 0xFFFFFFFF; in zynq_gpio_init()
224 *REG32(reg) = (~(1 << bit) << 16) | (!!on << bit); in gpio_set()
233 return ((*REG32(GPIO_DATA_RO(bank)) & (1 << bit)) > 0); in gpio_get()
238 … printf("DIRM_%u (0x%08x): 0x%08x\n", bank, GPIO_DIRM(bank), *REG32(GPIO_DIRM(bank))); in cmd_zynq_gpio()
239 … printf("OEN_%u (0x%08x): 0x%08x\n", bank, GPIO_OEN(bank), *REG32(GPIO_OEN(bank))); in cmd_zynq_gpio()
242 … printf("DATA_%u (0x%08x): 0x%08x\n", bank, GPIO_DATA(bank), *REG32(GPIO_DATA(bank))); in cmd_zynq_gpio()
[all …]
A Dclocks.c260 uint32_t ctrl = *REG32(clk_reg); in zynq_set_clock()
270 *REG32(clk_reg) = ctrl; in zynq_set_clock()
274 uint32_t ctrl = *REG32(clk_reg); in zynq_set_clock()
278 *REG32(clk_reg) = ctrl; in zynq_set_clock()
296 LTRACEF("clkreg 0x%x\n", *REG32(clk_reg)); in zynq_get_clock()
300 if ((*REG32(clk_reg) & (1 << enable_bitpos)) == 0) { in zynq_get_clock()
308 switch (BITS_SHIFT(*REG32(clk_reg), 5, 4)) { in zynq_get_clock()
322 uint32_t divisor = BITS_SHIFT(*REG32(clk_reg), 13, 8); in zynq_get_clock()
328 divisor2 = BITS_SHIFT(*REG32(clk_reg), 25, 20); in zynq_get_clock()
A Dplatform.c51 while (iters-- && !(*REG32(addr) & mask)) ; in reg_poll()
176 *REG32(zynq_ddr_cfg[i]) = zynq_ddr_cfg[i+1]; in zynq_ddr_init()
183 *REG32(DDRC_CTRL) |= DDRC_CTRL_OUT_OF_RESET; in zynq_ddr_init()
187 *REG32(0XF8007000) = *REG32(0xF8007000) & ~0x20000000U; in zynq_ddr_init()
339 *REG32(SLCR_BASE + 0xa1c) = 0x020202; in platform_early_init()
495 printf("\t%02u: 0x%08x", i, *REG32((uintptr_t)&SLCR->MIO_PIN_00 + (i * 4))); in cmd_zynq()
A Dtimer.c28 #define TIMREG(reg) (*REG32(TTC0_BASE + (reg)))
A Duart.c26 #define UART_REG(base, reg) (*REG32((base) + (reg)))
/lk-master/platform/bcm28xx/
A Dintc.c107 *REG32(reg) = 1 << (vector % 32); in mask_interrupt()
139 *REG32(reg) = 1 << (vector % 32); in unmask_interrupt()
169 uint32_t pend = *REG32(INTC_LOCAL_IRQ_PEND0 + cpu * 4); in platform_irq()
183 pend = *REG32(INTC_PEND0); in platform_irq()
194 pend = *REG32(INTC_PEND1); in platform_irq()
203 pend = *REG32(INTC_PEND2); in platform_irq()
221 pend = *REG32(INTC_LOCAL_MAILBOX0_CLR0 + 0x10 * cpu); in platform_irq()
225 *REG32(INTC_LOCAL_MAILBOX0_CLR0 + 0x10 * cpu) = pend; in platform_irq()
263 *REG32(INTC_DISABLE1) = 0xffffffff; in intc_init()
264 *REG32(INTC_DISABLE2) = 0xffffffff; in intc_init()
[all …]
A Dgpio.c17 #define GPIOREG(base, nr) (REG32(base) + (nr / BITS_PER_REG))
26 volatile uint32_t *reg = REG32(GPIO_GPFSEL0) + register_number; in gpio_config()
A Duart.c35 #define UARTREG(base, reg) (*REG32((base) + (reg)))
/lk-master/platform/qemu-virt-riscv/
A Dplic.c39 *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32)); in plic_early_init()
40 *REG32(PLIC_PRIORITY(i)) = 1; in plic_early_init()
44 *REG32(PLIC_THRESHOLD(riscv_current_hart())) = 0; in plic_early_init()
51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()
71 uint32_t vector = *REG32(PLIC_CLAIM(riscv_current_hart())); in riscv_platform_irq()
88 *REG32(PLIC_COMPLETE(riscv_current_hart())) = vector; in riscv_platform_irq()
/lk-master/platform/sifive/
A Dplic.c39 *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32)); in plic_early_init()
40 *REG32(PLIC_PRIORITY(i)) = 1; in plic_early_init()
44 *REG32(PLIC_THRESHOLD(riscv_current_hart())) = 0; in plic_early_init()
51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()
71 uint32_t vector = *REG32(PLIC_CLAIM(riscv_current_hart())); in riscv_platform_irq()
88 *REG32(PLIC_COMPLETE(riscv_current_hart())) = vector; in riscv_platform_irq()
/lk-master/top/include/lk/
A Dreg.h14 #define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr)) macro
19 #define RMWREG32(addr, startbit, width, val) *REG32(addr) = (*REG32(addr) & ~(((1<<(width)) - 1) <<…
23 #define writel(v, a) (*REG32(a) = (v))
24 #define readl(a) (*REG32(a))
/lk-master/platform/alterasoc/
A Dplatform.c66 printf("stat 0x%x\n", *REG32(0xffd05000)); in platform_early_init()
77 *REG32(0xffd05010) = 0; in platform_early_init()
A Duart.c37 #define UARTREG(base, reg) (*REG32((base) + (reg)))
/lk-master/arch/riscv/include/arch/riscv/
A Dclint.h34 *REG32(CLINT_MSIP(target_hart)) = 1; in clint_ipi_send()
41 *REG32(CLINT_MSIP(target_hart)) = 0; in clint_ipi_clear()
/lk-master/platform/stm32f7xx/
A Dinit.c249 stm32_unique_id[0] = *REG32(0x1ff0f420); in platform_early_init()
250 stm32_unique_id[1] = *REG32(0x1ff0f424); in platform_early_init()
251 stm32_unique_id[2] = *REG32(0x1ff0f428); in platform_early_init()
/lk-master/dev/timer/arm_cortex_a9/
A Darm_cortex_a9_timer.c36 #define TIMREG(reg) (*REG32(scu_control_base + PRIV_TIMER_OFFSET + (reg)))
47 #define GTIMREG(reg) (*REG32(scu_control_base + GLOBAL_TIMER_OFFSET + (reg)))
/lk-master/platform/microblaze/
A Duartlite.c41 #define UART_REG(reg) (*REG32(UARTLITE_BASEADDR + (reg) * 4))
A Dtimer.c39 #define TIMER_REG(reg) (*REG32(TIMER_BASEADDR + (reg) * 4))
A Dintc.c31 #define INTC_REG(reg) (*REG32(INTC_BASEADDR + (reg) * 4))
/lk-master/arch/arm/arm/
A Darch.c70 *REG32(scu_base) |= (1<<0); /* enable SCU */ in arch_early_init()
107 uint32_t scu_config = *REG32(scu_base + 4); in arch_init()
/lk-master/arch/arm/include/arch/
A Darch_ops.h87 return *REG32(DWT_CYCCNT); in arch_cycle_count()

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