1 /****************************************************************************** 2 * Filename: hw_rfc_dbell_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_RFC_DBELL_H__ 38 #define __HW_RFC_DBELL_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // RFC_DBELL component 44 // 45 //***************************************************************************** 46 // Doorbell Command Register 47 #define RFC_DBELL_O_CMDR 0x00000000 48 49 // Doorbell Command Status Register 50 #define RFC_DBELL_O_CMDSTA 0x00000004 51 52 // Interrupt Flags From RF Hardware Modules 53 #define RFC_DBELL_O_RFHWIFG 0x00000008 54 55 // Interrupt Enable For RF Hardware Modules 56 #define RFC_DBELL_O_RFHWIEN 0x0000000C 57 58 // Interrupt Flags For Command and Packet Engine Generated Interrupts 59 #define RFC_DBELL_O_RFCPEIFG 0x00000010 60 61 // Interrupt Enable For Command and Packet Engine Generated Interrupts 62 #define RFC_DBELL_O_RFCPEIEN 0x00000014 63 64 // Interrupt Vector Selection For Command and Packet Engine Generated 65 // Interrupts 66 #define RFC_DBELL_O_RFCPEISL 0x00000018 67 68 // Doorbell Command Acknowledgement Interrupt Flag 69 #define RFC_DBELL_O_RFACKIFG 0x0000001C 70 71 // RF Core General Purpose Output Control 72 #define RFC_DBELL_O_SYSGPOCTL 0x00000020 73 74 //***************************************************************************** 75 // 76 // Register: RFC_DBELL_O_CMDR 77 // 78 //***************************************************************************** 79 // Field: [31:0] CMD 80 // 81 // Command register. Raises an interrupt to the Command and packet engine (CPE) 82 // upon write. 83 #define RFC_DBELL_CMDR_CMD_W 32 84 #define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF 85 #define RFC_DBELL_CMDR_CMD_S 0 86 87 //***************************************************************************** 88 // 89 // Register: RFC_DBELL_O_CMDSTA 90 // 91 //***************************************************************************** 92 // Field: [31:0] STAT 93 // 94 // Status of the last command used 95 #define RFC_DBELL_CMDSTA_STAT_W 32 96 #define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF 97 #define RFC_DBELL_CMDSTA_STAT_S 0 98 99 //***************************************************************************** 100 // 101 // Register: RFC_DBELL_O_RFHWIFG 102 // 103 //***************************************************************************** 104 // Field: [19] RATCH7 105 // 106 // Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one 107 // has no effect. 108 #define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 109 #define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 110 #define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 111 #define RFC_DBELL_RFHWIFG_RATCH7_S 19 112 113 // Field: [18] RATCH6 114 // 115 // Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one 116 // has no effect. 117 #define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 118 #define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 119 #define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 120 #define RFC_DBELL_RFHWIFG_RATCH6_S 18 121 122 // Field: [17] RATCH5 123 // 124 // Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one 125 // has no effect. 126 #define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 127 #define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 128 #define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 129 #define RFC_DBELL_RFHWIFG_RATCH5_S 17 130 131 // Field: [16] RATCH4 132 // 133 // Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one 134 // has no effect. 135 #define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 136 #define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 137 #define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 138 #define RFC_DBELL_RFHWIFG_RATCH4_S 16 139 140 // Field: [15] RATCH3 141 // 142 // Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one 143 // has no effect. 144 #define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 145 #define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 146 #define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 147 #define RFC_DBELL_RFHWIFG_RATCH3_S 15 148 149 // Field: [14] RATCH2 150 // 151 // Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one 152 // has no effect. 153 #define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 154 #define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 155 #define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 156 #define RFC_DBELL_RFHWIFG_RATCH2_S 14 157 158 // Field: [13] RATCH1 159 // 160 // Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one 161 // has no effect. 162 #define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 163 #define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 164 #define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 165 #define RFC_DBELL_RFHWIFG_RATCH1_S 13 166 167 // Field: [12] RATCH0 168 // 169 // Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one 170 // has no effect. 171 #define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 172 #define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 173 #define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 174 #define RFC_DBELL_RFHWIFG_RATCH0_S 12 175 176 // Field: [11] RFESOFT2 177 // 178 // RF engine software defined interrupt 2 flag. Write zero to clear flag. Write 179 // to one has no effect. 180 #define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 181 #define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 182 #define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 183 #define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 184 185 // Field: [10] RFESOFT1 186 // 187 // RF engine software defined interrupt 1 flag. Write zero to clear flag. Write 188 // to one has no effect. 189 #define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 190 #define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 191 #define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 192 #define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 193 194 // Field: [9] RFESOFT0 195 // 196 // RF engine software defined interrupt 0 flag. Write zero to clear flag. Write 197 // to one has no effect. 198 #define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 199 #define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 200 #define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 201 #define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 202 203 // Field: [8] RFEDONE 204 // 205 // RF engine command done interrupt flag. Write zero to clear flag. Write to 206 // one has no effect. 207 #define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 208 #define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 209 #define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 210 #define RFC_DBELL_RFHWIFG_RFEDONE_S 8 211 212 // Field: [6] TRCTK 213 // 214 // Debug tracer system tick interrupt flag. Write zero to clear flag. Write to 215 // one has no effect. 216 #define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 217 #define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 218 #define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 219 #define RFC_DBELL_RFHWIFG_TRCTK_S 6 220 221 // Field: [5] MDMSOFT 222 // 223 // Modem synchronization word detection interrupt flag. This interrupt will be 224 // raised by modem when the synchronization word is received. The CPE may 225 // decide to reject the packet based on its header (protocol specific). Write 226 // zero to clear flag. Write to one has no effect. 227 #define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 228 #define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 229 #define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 230 #define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 231 232 // Field: [4] MDMOUT 233 // 234 // Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has 235 // no effect. 236 #define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 237 #define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 238 #define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 239 #define RFC_DBELL_RFHWIFG_MDMOUT_S 4 240 241 // Field: [3] MDMIN 242 // 243 // Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has 244 // no effect. 245 #define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 246 #define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 247 #define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 248 #define RFC_DBELL_RFHWIFG_MDMIN_S 3 249 250 // Field: [2] MDMDONE 251 // 252 // Modem command done interrupt flag. Write zero to clear flag. Write to one 253 // has no effect. 254 #define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 255 #define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 256 #define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 257 #define RFC_DBELL_RFHWIFG_MDMDONE_S 2 258 259 // Field: [1] FSCA 260 // 261 // Frequency synthesizer calibration accelerator interrupt flag. Write zero to 262 // clear flag. Write to one has no effect. 263 #define RFC_DBELL_RFHWIFG_FSCA 0x00000002 264 #define RFC_DBELL_RFHWIFG_FSCA_BITN 1 265 #define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 266 #define RFC_DBELL_RFHWIFG_FSCA_S 1 267 268 //***************************************************************************** 269 // 270 // Register: RFC_DBELL_O_RFHWIEN 271 // 272 //***************************************************************************** 273 // Field: [19] RATCH7 274 // 275 // Interrupt enable for RFHWIFG.RATCH7. 276 #define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 277 #define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 278 #define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 279 #define RFC_DBELL_RFHWIEN_RATCH7_S 19 280 281 // Field: [18] RATCH6 282 // 283 // Interrupt enable for RFHWIFG.RATCH6. 284 #define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 285 #define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 286 #define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 287 #define RFC_DBELL_RFHWIEN_RATCH6_S 18 288 289 // Field: [17] RATCH5 290 // 291 // Interrupt enable for RFHWIFG.RATCH5. 292 #define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 293 #define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 294 #define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 295 #define RFC_DBELL_RFHWIEN_RATCH5_S 17 296 297 // Field: [16] RATCH4 298 // 299 // Interrupt enable for RFHWIFG.RATCH4. 300 #define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 301 #define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 302 #define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 303 #define RFC_DBELL_RFHWIEN_RATCH4_S 16 304 305 // Field: [15] RATCH3 306 // 307 // Interrupt enable for RFHWIFG.RATCH3. 308 #define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 309 #define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 310 #define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 311 #define RFC_DBELL_RFHWIEN_RATCH3_S 15 312 313 // Field: [14] RATCH2 314 // 315 // Interrupt enable for RFHWIFG.RATCH2. 316 #define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 317 #define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 318 #define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 319 #define RFC_DBELL_RFHWIEN_RATCH2_S 14 320 321 // Field: [13] RATCH1 322 // 323 // Interrupt enable for RFHWIFG.RATCH1. 324 #define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 325 #define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 326 #define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 327 #define RFC_DBELL_RFHWIEN_RATCH1_S 13 328 329 // Field: [12] RATCH0 330 // 331 // Interrupt enable for RFHWIFG.RATCH0. 332 #define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 333 #define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 334 #define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 335 #define RFC_DBELL_RFHWIEN_RATCH0_S 12 336 337 // Field: [11] RFESOFT2 338 // 339 // Interrupt enable for RFHWIFG.RFESOFT2. 340 #define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 341 #define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 342 #define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 343 #define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 344 345 // Field: [10] RFESOFT1 346 // 347 // Interrupt enable for RFHWIFG.RFESOFT1. 348 #define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 349 #define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 350 #define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 351 #define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 352 353 // Field: [9] RFESOFT0 354 // 355 // Interrupt enable for RFHWIFG.RFESOFT0. 356 #define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 357 #define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 358 #define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 359 #define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 360 361 // Field: [8] RFEDONE 362 // 363 // Interrupt enable for RFHWIFG.RFEDONE. 364 #define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 365 #define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 366 #define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 367 #define RFC_DBELL_RFHWIEN_RFEDONE_S 8 368 369 // Field: [6] TRCTK 370 // 371 // Interrupt enable for RFHWIFG.TRCTK. 372 #define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 373 #define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 374 #define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 375 #define RFC_DBELL_RFHWIEN_TRCTK_S 6 376 377 // Field: [5] MDMSOFT 378 // 379 // Interrupt enable for RFHWIFG.MDMSOFT. 380 #define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 381 #define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 382 #define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 383 #define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 384 385 // Field: [4] MDMOUT 386 // 387 // Interrupt enable for RFHWIFG.MDMOUT. 388 #define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 389 #define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 390 #define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 391 #define RFC_DBELL_RFHWIEN_MDMOUT_S 4 392 393 // Field: [3] MDMIN 394 // 395 // Interrupt enable for RFHWIFG.MDMIN. 396 #define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 397 #define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 398 #define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 399 #define RFC_DBELL_RFHWIEN_MDMIN_S 3 400 401 // Field: [2] MDMDONE 402 // 403 // Interrupt enable for RFHWIFG.MDMDONE. 404 #define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 405 #define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 406 #define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 407 #define RFC_DBELL_RFHWIEN_MDMDONE_S 2 408 409 // Field: [1] FSCA 410 // 411 // Interrupt enable for RFHWIFG.FSCA. 412 #define RFC_DBELL_RFHWIEN_FSCA 0x00000002 413 #define RFC_DBELL_RFHWIEN_FSCA_BITN 1 414 #define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 415 #define RFC_DBELL_RFHWIEN_FSCA_S 1 416 417 //***************************************************************************** 418 // 419 // Register: RFC_DBELL_O_RFCPEIFG 420 // 421 //***************************************************************************** 422 // Field: [31] INTERNAL_ERROR 423 // 424 // Interrupt flag 31. The command and packet engine (CPE) has observed an 425 // unexpected error. A reset of the CPE is needed. This can be done by 426 // switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero 427 // to clear flag. Write to one has no effect. 428 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 429 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 430 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 431 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 432 433 // Field: [30] BOOT_DONE 434 // 435 // Interrupt flag 30. The command and packet engine (CPE) boot is finished. 436 // Write zero to clear flag. Write to one has no effect. 437 #define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 438 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 439 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 440 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 441 442 // Field: [29] MODULES_UNLOCKED 443 // 444 // Interrupt flag 29. As part of command and packet engine (CPE) boot process, 445 // it has opened access to RF Core modules and memories. Write zero to clear 446 // flag. Write to one has no effect. 447 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 448 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 449 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 450 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 451 452 // Field: [28] SYNTH_NO_LOCK 453 // 454 // Interrupt flag 28. The phase-locked loop in frequency synthesizer has 455 // reported loss of lock. Write zero to clear flag. Write to one has no effect. 456 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 457 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 458 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 459 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 460 461 // Field: [27] IRQ27 462 // 463 // Interrupt flag 27. Write zero to clear flag. Write to one has no effect. 464 #define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 465 #define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 466 #define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 467 #define RFC_DBELL_RFCPEIFG_IRQ27_S 27 468 469 // Field: [26] RX_ABORTED 470 // 471 // Interrupt flag 26. Packet reception stopped before packet was done. Write 472 // zero to clear flag. Write to one has no effect. 473 #define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 474 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 475 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 476 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 477 478 // Field: [25] RX_N_DATA_WRITTEN 479 // 480 // Interrupt flag 25. Specified number of bytes written to partial read Rx 481 // buffer. Write zero to clear flag. Write to one has no effect. 482 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 483 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 484 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 485 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 486 487 // Field: [24] RX_DATA_WRITTEN 488 // 489 // Interrupt flag 24. Data written to partial read Rx buffer. Write zero to 490 // clear flag. Write to one has no effect. 491 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 492 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 493 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 494 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 495 496 // Field: [23] RX_ENTRY_DONE 497 // 498 // Interrupt flag 23. Rx queue data entry changing state to finished. Write 499 // zero to clear flag. Write to one has no effect. 500 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 501 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 502 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 503 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 504 505 // Field: [22] RX_BUF_FULL 506 // 507 // Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: 508 // Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame 509 // received that did not fit in the Rx queue. Write zero to clear flag. Write 510 // to one has no effect. 511 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 512 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 513 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 514 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 515 516 // Field: [21] RX_CTRL_ACK 517 // 518 // Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, 519 // not to be ignored, then acknowledgement sent. Write zero to clear flag. 520 // Write to one has no effect. 521 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 522 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 523 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 524 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 525 526 // Field: [20] RX_CTRL 527 // 528 // Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, 529 // not to be ignored. Write zero to clear flag. Write to one has no effect. 530 #define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 531 #define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 532 #define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 533 #define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 534 535 // Field: [19] RX_EMPTY 536 // 537 // Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be 538 // ignored, no payload. Write zero to clear flag. Write to one has no effect. 539 #define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 540 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 541 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 542 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 543 544 // Field: [18] RX_IGNORED 545 // 546 // Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet 547 // received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received 548 // with ignore flag set. Write zero to clear flag. Write to one has no effect. 549 #define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 550 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 551 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 552 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 553 554 // Field: [17] RX_NOK 555 // 556 // Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received 557 // with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write 558 // zero to clear flag. Write to one has no effect. 559 #define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 560 #define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 561 #define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 562 #define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 563 564 // Field: [16] RX_OK 565 // 566 // Interrupt flag 16. Packet received correctly. BLE mode: Packet received with 567 // CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received 568 // with CRC OK. Write zero to clear flag. Write to one has no effect. 569 #define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 570 #define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 571 #define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 572 #define RFC_DBELL_RFCPEIFG_RX_OK_S 16 573 574 // Field: [15] IRQ15 575 // 576 // Interrupt flag 15. Write zero to clear flag. Write to one has no effect. 577 #define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 578 #define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 579 #define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 580 #define RFC_DBELL_RFCPEIFG_IRQ15_S 15 581 582 // Field: [14] IRQ14 583 // 584 // Interrupt flag 14. Write zero to clear flag. Write to one has no effect. 585 #define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 586 #define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 587 #define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 588 #define RFC_DBELL_RFCPEIFG_IRQ14_S 14 589 590 // Field: [13] IRQ13 591 // 592 // Interrupt flag 13. Write zero to clear flag. Write to one has no effect. 593 #define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 594 #define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 595 #define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 596 #define RFC_DBELL_RFCPEIFG_IRQ13_S 13 597 598 // Field: [12] IRQ12 599 // 600 // Interrupt flag 12. Write zero to clear flag. Write to one has no effect. 601 #define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 602 #define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 603 #define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 604 #define RFC_DBELL_RFCPEIFG_IRQ12_S 12 605 606 // Field: [11] TX_BUFFER_CHANGED 607 // 608 // Interrupt flag 11. BLE mode only: A buffer change is complete after 609 // CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. 610 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 611 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 612 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 613 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 614 615 // Field: [10] TX_ENTRY_DONE 616 // 617 // Interrupt flag 10. Tx queue data entry state changed to finished. Write zero 618 // to clear flag. Write to one has no effect. 619 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 620 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 621 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 622 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 623 624 // Field: [9] TX_RETRANS 625 // 626 // Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear 627 // flag. Write to one has no effect. 628 #define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 629 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 630 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 631 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 632 633 // Field: [8] TX_CTRL_ACK_ACK 634 // 635 // Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted 636 // LL control packet, and acknowledgement transmitted for that packet. Write 637 // zero to clear flag. Write to one has no effect. 638 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 639 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 640 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 641 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 642 643 // Field: [7] TX_CTRL_ACK 644 // 645 // Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL 646 // control packet. Write zero to clear flag. Write to one has no effect. 647 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 648 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 649 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 650 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 651 652 // Field: [6] TX_CTRL 653 // 654 // Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to 655 // clear flag. Write to one has no effect. 656 #define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 657 #define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 658 #define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 659 #define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 660 661 // Field: [5] TX_ACK 662 // 663 // Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted 664 // packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to 665 // clear flag. Write to one has no effect. 666 #define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 667 #define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 668 #define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 669 #define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 670 671 // Field: [4] TX_DONE 672 // 673 // Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been 674 // transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero 675 // to clear flag. Write to one has no effect. 676 #define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 677 #define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 678 #define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 679 #define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 680 681 // Field: [3] LAST_FG_COMMAND_DONE 682 // 683 // Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio 684 // operation command in a chain of commands has finished. Write zero to clear 685 // flag. Write to one has no effect. 686 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 687 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 688 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 689 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 690 691 // Field: [2] FG_COMMAND_DONE 692 // 693 // Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation 694 // command has finished. Write zero to clear flag. Write to one has no effect. 695 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 696 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 697 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 698 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 699 700 // Field: [1] LAST_COMMAND_DONE 701 // 702 // Interrupt flag 1. The last radio operation command in a chain of commands 703 // has finished. (IEEE 802.15.4 mode: The last background level radio operation 704 // command in a chain of commands has finished.) Write zero to clear flag. 705 // Write to one has no effect. 706 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 707 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 708 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 709 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 710 711 // Field: [0] COMMAND_DONE 712 // 713 // Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A 714 // background level radio operation command has finished.) Write zero to clear 715 // flag. Write to one has no effect. 716 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 717 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 718 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 719 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 720 721 //***************************************************************************** 722 // 723 // Register: RFC_DBELL_O_RFCPEIEN 724 // 725 //***************************************************************************** 726 // Field: [31] INTERNAL_ERROR 727 // 728 // Interrupt enable for RFCPEIFG.INTERNAL_ERROR. 729 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 730 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 731 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 732 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 733 734 // Field: [30] BOOT_DONE 735 // 736 // Interrupt enable for RFCPEIFG.BOOT_DONE. 737 #define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 738 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 739 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 740 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 741 742 // Field: [29] MODULES_UNLOCKED 743 // 744 // Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. 745 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 746 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 747 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 748 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 749 750 // Field: [28] SYNTH_NO_LOCK 751 // 752 // Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. 753 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 754 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 755 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 756 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 757 758 // Field: [27] IRQ27 759 // 760 // Interrupt enable for RFCPEIFG.IRQ27. 761 #define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 762 #define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 763 #define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 764 #define RFC_DBELL_RFCPEIEN_IRQ27_S 27 765 766 // Field: [26] RX_ABORTED 767 // 768 // Interrupt enable for RFCPEIFG.RX_ABORTED. 769 #define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 770 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 771 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 772 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 773 774 // Field: [25] RX_N_DATA_WRITTEN 775 // 776 // Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. 777 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 778 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 779 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 780 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 781 782 // Field: [24] RX_DATA_WRITTEN 783 // 784 // Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. 785 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 786 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 787 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 788 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 789 790 // Field: [23] RX_ENTRY_DONE 791 // 792 // Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. 793 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 794 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 795 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 796 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 797 798 // Field: [22] RX_BUF_FULL 799 // 800 // Interrupt enable for RFCPEIFG.RX_BUF_FULL. 801 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 802 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 803 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 804 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 805 806 // Field: [21] RX_CTRL_ACK 807 // 808 // Interrupt enable for RFCPEIFG.RX_CTRL_ACK. 809 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 810 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 811 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 812 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 813 814 // Field: [20] RX_CTRL 815 // 816 // Interrupt enable for RFCPEIFG.RX_CTRL. 817 #define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 818 #define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 819 #define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 820 #define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 821 822 // Field: [19] RX_EMPTY 823 // 824 // Interrupt enable for RFCPEIFG.RX_EMPTY. 825 #define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 826 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 827 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 828 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 829 830 // Field: [18] RX_IGNORED 831 // 832 // Interrupt enable for RFCPEIFG.RX_IGNORED. 833 #define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 834 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 835 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 836 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 837 838 // Field: [17] RX_NOK 839 // 840 // Interrupt enable for RFCPEIFG.RX_NOK. 841 #define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 842 #define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 843 #define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 844 #define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 845 846 // Field: [16] RX_OK 847 // 848 // Interrupt enable for RFCPEIFG.RX_OK. 849 #define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 850 #define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 851 #define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 852 #define RFC_DBELL_RFCPEIEN_RX_OK_S 16 853 854 // Field: [15] IRQ15 855 // 856 // Interrupt enable for RFCPEIFG.IRQ15. 857 #define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 858 #define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 859 #define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 860 #define RFC_DBELL_RFCPEIEN_IRQ15_S 15 861 862 // Field: [14] IRQ14 863 // 864 // Interrupt enable for RFCPEIFG.IRQ14. 865 #define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 866 #define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 867 #define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 868 #define RFC_DBELL_RFCPEIEN_IRQ14_S 14 869 870 // Field: [13] IRQ13 871 // 872 // Interrupt enable for RFCPEIFG.IRQ13. 873 #define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 874 #define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 875 #define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 876 #define RFC_DBELL_RFCPEIEN_IRQ13_S 13 877 878 // Field: [12] IRQ12 879 // 880 // Interrupt enable for RFCPEIFG.IRQ12. 881 #define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 882 #define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 883 #define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 884 #define RFC_DBELL_RFCPEIEN_IRQ12_S 12 885 886 // Field: [11] TX_BUFFER_CHANGED 887 // 888 // Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. 889 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 890 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 891 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 892 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 893 894 // Field: [10] TX_ENTRY_DONE 895 // 896 // Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. 897 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 898 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 899 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 900 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 901 902 // Field: [9] TX_RETRANS 903 // 904 // Interrupt enable for RFCPEIFG.TX_RETRANS. 905 #define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 906 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 907 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 908 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 909 910 // Field: [8] TX_CTRL_ACK_ACK 911 // 912 // Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. 913 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 914 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 915 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 916 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 917 918 // Field: [7] TX_CTRL_ACK 919 // 920 // Interrupt enable for RFCPEIFG.TX_CTRL_ACK. 921 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 922 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 923 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 924 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 925 926 // Field: [6] TX_CTRL 927 // 928 // Interrupt enable for RFCPEIFG.TX_CTRL. 929 #define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 930 #define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 931 #define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 932 #define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 933 934 // Field: [5] TX_ACK 935 // 936 // Interrupt enable for RFCPEIFG.TX_ACK. 937 #define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 938 #define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 939 #define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 940 #define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 941 942 // Field: [4] TX_DONE 943 // 944 // Interrupt enable for RFCPEIFG.TX_DONE. 945 #define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 946 #define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 947 #define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 948 #define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 949 950 // Field: [3] LAST_FG_COMMAND_DONE 951 // 952 // Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. 953 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 954 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 955 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 956 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 957 958 // Field: [2] FG_COMMAND_DONE 959 // 960 // Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. 961 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 962 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 963 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 964 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 965 966 // Field: [1] LAST_COMMAND_DONE 967 // 968 // Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. 969 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 970 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 971 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 972 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 973 974 // Field: [0] COMMAND_DONE 975 // 976 // Interrupt enable for RFCPEIFG.COMMAND_DONE. 977 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 978 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 979 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 980 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 981 982 //***************************************************************************** 983 // 984 // Register: RFC_DBELL_O_RFCPEISL 985 // 986 //***************************************************************************** 987 // Field: [31] INTERNAL_ERROR 988 // 989 // Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt 990 // should use. 991 // ENUMs: 992 // CPE1 Associate this interrupt line with INT_RF_CPE1 993 // interrupt vector 994 // CPE0 Associate this interrupt line with INT_RF_CPE0 995 // interrupt vector 996 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 997 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 998 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 999 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 1000 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 1001 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 1002 1003 // Field: [30] BOOT_DONE 1004 // 1005 // Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should 1006 // use. 1007 // ENUMs: 1008 // CPE1 Associate this interrupt line with INT_RF_CPE1 1009 // interrupt vector 1010 // CPE0 Associate this interrupt line with INT_RF_CPE0 1011 // interrupt vector 1012 #define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 1013 #define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 1014 #define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 1015 #define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 1016 #define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 1017 #define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 1018 1019 // Field: [29] MODULES_UNLOCKED 1020 // 1021 // Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt 1022 // should use. 1023 // ENUMs: 1024 // CPE1 Associate this interrupt line with INT_RF_CPE1 1025 // interrupt vector 1026 // CPE0 Associate this interrupt line with INT_RF_CPE0 1027 // interrupt vector 1028 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 1029 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 1030 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 1031 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 1032 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 1033 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 1034 1035 // Field: [28] SYNTH_NO_LOCK 1036 // 1037 // Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt 1038 // should use. 1039 // ENUMs: 1040 // CPE1 Associate this interrupt line with INT_RF_CPE1 1041 // interrupt vector 1042 // CPE0 Associate this interrupt line with INT_RF_CPE0 1043 // interrupt vector 1044 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 1045 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 1046 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 1047 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 1048 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 1049 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 1050 1051 // Field: [27] IRQ27 1052 // 1053 // Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. 1054 // ENUMs: 1055 // CPE1 Associate this interrupt line with INT_RF_CPE1 1056 // interrupt vector 1057 // CPE0 Associate this interrupt line with INT_RF_CPE0 1058 // interrupt vector 1059 #define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 1060 #define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 1061 #define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 1062 #define RFC_DBELL_RFCPEISL_IRQ27_S 27 1063 #define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 1064 #define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 1065 1066 // Field: [26] RX_ABORTED 1067 // 1068 // Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should 1069 // use. 1070 // ENUMs: 1071 // CPE1 Associate this interrupt line with INT_RF_CPE1 1072 // interrupt vector 1073 // CPE0 Associate this interrupt line with INT_RF_CPE0 1074 // interrupt vector 1075 #define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 1076 #define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 1077 #define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 1078 #define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 1079 #define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 1080 #define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 1081 1082 // Field: [25] RX_N_DATA_WRITTEN 1083 // 1084 // Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt 1085 // should use. 1086 // ENUMs: 1087 // CPE1 Associate this interrupt line with INT_RF_CPE1 1088 // interrupt vector 1089 // CPE0 Associate this interrupt line with INT_RF_CPE0 1090 // interrupt vector 1091 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 1092 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 1093 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 1094 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 1095 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 1096 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 1097 1098 // Field: [24] RX_DATA_WRITTEN 1099 // 1100 // Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt 1101 // should use. 1102 // ENUMs: 1103 // CPE1 Associate this interrupt line with INT_RF_CPE1 1104 // interrupt vector 1105 // CPE0 Associate this interrupt line with INT_RF_CPE0 1106 // interrupt vector 1107 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 1108 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 1109 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 1110 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 1111 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 1112 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 1113 1114 // Field: [23] RX_ENTRY_DONE 1115 // 1116 // Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt 1117 // should use. 1118 // ENUMs: 1119 // CPE1 Associate this interrupt line with INT_RF_CPE1 1120 // interrupt vector 1121 // CPE0 Associate this interrupt line with INT_RF_CPE0 1122 // interrupt vector 1123 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 1124 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 1125 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 1126 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 1127 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 1128 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 1129 1130 // Field: [22] RX_BUF_FULL 1131 // 1132 // Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should 1133 // use. 1134 // ENUMs: 1135 // CPE1 Associate this interrupt line with INT_RF_CPE1 1136 // interrupt vector 1137 // CPE0 Associate this interrupt line with INT_RF_CPE0 1138 // interrupt vector 1139 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 1140 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 1141 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 1142 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 1143 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 1144 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 1145 1146 // Field: [21] RX_CTRL_ACK 1147 // 1148 // Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should 1149 // use. 1150 // ENUMs: 1151 // CPE1 Associate this interrupt line with INT_RF_CPE1 1152 // interrupt vector 1153 // CPE0 Associate this interrupt line with INT_RF_CPE0 1154 // interrupt vector 1155 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 1156 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 1157 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 1158 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 1159 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 1160 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 1161 1162 // Field: [20] RX_CTRL 1163 // 1164 // Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. 1165 // ENUMs: 1166 // CPE1 Associate this interrupt line with INT_RF_CPE1 1167 // interrupt vector 1168 // CPE0 Associate this interrupt line with INT_RF_CPE0 1169 // interrupt vector 1170 #define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 1171 #define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 1172 #define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 1173 #define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 1174 #define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 1175 #define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 1176 1177 // Field: [19] RX_EMPTY 1178 // 1179 // Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should 1180 // use. 1181 // ENUMs: 1182 // CPE1 Associate this interrupt line with INT_RF_CPE1 1183 // interrupt vector 1184 // CPE0 Associate this interrupt line with INT_RF_CPE0 1185 // interrupt vector 1186 #define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 1187 #define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 1188 #define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 1189 #define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 1190 #define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 1191 #define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 1192 1193 // Field: [18] RX_IGNORED 1194 // 1195 // Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should 1196 // use. 1197 // ENUMs: 1198 // CPE1 Associate this interrupt line with INT_RF_CPE1 1199 // interrupt vector 1200 // CPE0 Associate this interrupt line with INT_RF_CPE0 1201 // interrupt vector 1202 #define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 1203 #define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 1204 #define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 1205 #define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 1206 #define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 1207 #define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 1208 1209 // Field: [17] RX_NOK 1210 // 1211 // Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. 1212 // ENUMs: 1213 // CPE1 Associate this interrupt line with INT_RF_CPE1 1214 // interrupt vector 1215 // CPE0 Associate this interrupt line with INT_RF_CPE0 1216 // interrupt vector 1217 #define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 1218 #define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 1219 #define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 1220 #define RFC_DBELL_RFCPEISL_RX_NOK_S 17 1221 #define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 1222 #define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 1223 1224 // Field: [16] RX_OK 1225 // 1226 // Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. 1227 // ENUMs: 1228 // CPE1 Associate this interrupt line with INT_RF_CPE1 1229 // interrupt vector 1230 // CPE0 Associate this interrupt line with INT_RF_CPE0 1231 // interrupt vector 1232 #define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 1233 #define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 1234 #define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 1235 #define RFC_DBELL_RFCPEISL_RX_OK_S 16 1236 #define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 1237 #define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 1238 1239 // Field: [15] IRQ15 1240 // 1241 // Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. 1242 // ENUMs: 1243 // CPE1 Associate this interrupt line with INT_RF_CPE1 1244 // interrupt vector 1245 // CPE0 Associate this interrupt line with INT_RF_CPE0 1246 // interrupt vector 1247 #define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 1248 #define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 1249 #define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 1250 #define RFC_DBELL_RFCPEISL_IRQ15_S 15 1251 #define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 1252 #define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 1253 1254 // Field: [14] IRQ14 1255 // 1256 // Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. 1257 // ENUMs: 1258 // CPE1 Associate this interrupt line with INT_RF_CPE1 1259 // interrupt vector 1260 // CPE0 Associate this interrupt line with INT_RF_CPE0 1261 // interrupt vector 1262 #define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 1263 #define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 1264 #define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 1265 #define RFC_DBELL_RFCPEISL_IRQ14_S 14 1266 #define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 1267 #define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 1268 1269 // Field: [13] IRQ13 1270 // 1271 // Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt should use. 1272 // ENUMs: 1273 // CPE1 Associate this interrupt line with INT_RF_CPE1 1274 // interrupt vector 1275 // CPE0 Associate this interrupt line with INT_RF_CPE0 1276 // interrupt vector 1277 #define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 1278 #define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 1279 #define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 1280 #define RFC_DBELL_RFCPEISL_IRQ13_S 13 1281 #define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 1282 #define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 1283 1284 // Field: [12] IRQ12 1285 // 1286 // Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt should use. 1287 // ENUMs: 1288 // CPE1 Associate this interrupt line with INT_RF_CPE1 1289 // interrupt vector 1290 // CPE0 Associate this interrupt line with INT_RF_CPE0 1291 // interrupt vector 1292 #define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 1293 #define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 1294 #define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 1295 #define RFC_DBELL_RFCPEISL_IRQ12_S 12 1296 #define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 1297 #define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 1298 1299 // Field: [11] TX_BUFFER_CHANGED 1300 // 1301 // Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt 1302 // should use. 1303 // ENUMs: 1304 // CPE1 Associate this interrupt line with INT_RF_CPE1 1305 // interrupt vector 1306 // CPE0 Associate this interrupt line with INT_RF_CPE0 1307 // interrupt vector 1308 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 1309 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 1310 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 1311 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 1312 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 1313 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 1314 1315 // Field: [10] TX_ENTRY_DONE 1316 // 1317 // Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt 1318 // should use. 1319 // ENUMs: 1320 // CPE1 Associate this interrupt line with INT_RF_CPE1 1321 // interrupt vector 1322 // CPE0 Associate this interrupt line with INT_RF_CPE0 1323 // interrupt vector 1324 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 1325 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 1326 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 1327 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 1328 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 1329 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 1330 1331 // Field: [9] TX_RETRANS 1332 // 1333 // Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should 1334 // use. 1335 // ENUMs: 1336 // CPE1 Associate this interrupt line with INT_RF_CPE1 1337 // interrupt vector 1338 // CPE0 Associate this interrupt line with INT_RF_CPE0 1339 // interrupt vector 1340 #define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 1341 #define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 1342 #define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 1343 #define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 1344 #define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 1345 #define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 1346 1347 // Field: [8] TX_CTRL_ACK_ACK 1348 // 1349 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt 1350 // should use. 1351 // ENUMs: 1352 // CPE1 Associate this interrupt line with INT_RF_CPE1 1353 // interrupt vector 1354 // CPE0 Associate this interrupt line with INT_RF_CPE0 1355 // interrupt vector 1356 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 1357 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 1358 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 1359 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 1360 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 1361 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 1362 1363 // Field: [7] TX_CTRL_ACK 1364 // 1365 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should 1366 // use. 1367 // ENUMs: 1368 // CPE1 Associate this interrupt line with INT_RF_CPE1 1369 // interrupt vector 1370 // CPE0 Associate this interrupt line with INT_RF_CPE0 1371 // interrupt vector 1372 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 1373 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 1374 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 1375 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 1376 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 1377 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 1378 1379 // Field: [6] TX_CTRL 1380 // 1381 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. 1382 // ENUMs: 1383 // CPE1 Associate this interrupt line with INT_RF_CPE1 1384 // interrupt vector 1385 // CPE0 Associate this interrupt line with INT_RF_CPE0 1386 // interrupt vector 1387 #define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 1388 #define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 1389 #define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 1390 #define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 1391 #define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 1392 #define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 1393 1394 // Field: [5] TX_ACK 1395 // 1396 // Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. 1397 // ENUMs: 1398 // CPE1 Associate this interrupt line with INT_RF_CPE1 1399 // interrupt vector 1400 // CPE0 Associate this interrupt line with INT_RF_CPE0 1401 // interrupt vector 1402 #define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 1403 #define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 1404 #define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 1405 #define RFC_DBELL_RFCPEISL_TX_ACK_S 5 1406 #define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 1407 #define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 1408 1409 // Field: [4] TX_DONE 1410 // 1411 // Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. 1412 // ENUMs: 1413 // CPE1 Associate this interrupt line with INT_RF_CPE1 1414 // interrupt vector 1415 // CPE0 Associate this interrupt line with INT_RF_CPE0 1416 // interrupt vector 1417 #define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 1418 #define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 1419 #define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 1420 #define RFC_DBELL_RFCPEISL_TX_DONE_S 4 1421 #define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 1422 #define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 1423 1424 // Field: [3] LAST_FG_COMMAND_DONE 1425 // 1426 // Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE 1427 // interrupt should use. 1428 // ENUMs: 1429 // CPE1 Associate this interrupt line with INT_RF_CPE1 1430 // interrupt vector 1431 // CPE0 Associate this interrupt line with INT_RF_CPE0 1432 // interrupt vector 1433 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 1434 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 1435 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 1436 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 1437 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 1438 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 1439 1440 // Field: [2] FG_COMMAND_DONE 1441 // 1442 // Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt 1443 // should use. 1444 // ENUMs: 1445 // CPE1 Associate this interrupt line with INT_RF_CPE1 1446 // interrupt vector 1447 // CPE0 Associate this interrupt line with INT_RF_CPE0 1448 // interrupt vector 1449 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 1450 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 1451 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 1452 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 1453 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 1454 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 1455 1456 // Field: [1] LAST_COMMAND_DONE 1457 // 1458 // Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt 1459 // should use. 1460 // ENUMs: 1461 // CPE1 Associate this interrupt line with INT_RF_CPE1 1462 // interrupt vector 1463 // CPE0 Associate this interrupt line with INT_RF_CPE0 1464 // interrupt vector 1465 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 1466 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 1467 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 1468 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 1469 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 1470 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 1471 1472 // Field: [0] COMMAND_DONE 1473 // 1474 // Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should 1475 // use. 1476 // ENUMs: 1477 // CPE1 Associate this interrupt line with INT_RF_CPE1 1478 // interrupt vector 1479 // CPE0 Associate this interrupt line with INT_RF_CPE0 1480 // interrupt vector 1481 #define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 1482 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 1483 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 1484 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 1485 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 1486 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 1487 1488 //***************************************************************************** 1489 // 1490 // Register: RFC_DBELL_O_RFACKIFG 1491 // 1492 //***************************************************************************** 1493 // Field: [0] ACKFLAG 1494 // 1495 // Interrupt flag for Command ACK 1496 #define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 1497 #define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 1498 #define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 1499 #define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 1500 1501 //***************************************************************************** 1502 // 1503 // Register: RFC_DBELL_O_SYSGPOCTL 1504 // 1505 //***************************************************************************** 1506 // Field: [15:12] GPOCTL3 1507 // 1508 // RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO 1509 // line 3. 1510 // ENUMs: 1511 // RATGPO3 RAT GPO line 3 1512 // RATGPO2 RAT GPO line 2 1513 // RATGPO1 RAT GPO line 1 1514 // RATGPO0 RAT GPO line 0 1515 // RFEGPO3 RFE GPO line 3 1516 // RFEGPO2 RFE GPO line 2 1517 // RFEGPO1 RFE GPO line 1 1518 // RFEGPO0 RFE GPO line 0 1519 // MCEGPO3 MCE GPO line 3 1520 // MCEGPO2 MCE GPO line 2 1521 // MCEGPO1 MCE GPO line 1 1522 // MCEGPO0 MCE GPO line 0 1523 // CPEGPO3 CPE GPO line 3 1524 // CPEGPO2 CPE GPO line 2 1525 // CPEGPO1 CPE GPO line 1 1526 // CPEGPO0 CPE GPO line 0 1527 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 1528 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 1529 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 1530 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 1531 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 1532 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 1533 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 1534 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 1535 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 1536 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 1537 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 1538 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 1539 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 1540 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 1541 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 1542 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 1543 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 1544 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 1545 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 1546 1547 // Field: [11:8] GPOCTL2 1548 // 1549 // RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO 1550 // line 2. 1551 // ENUMs: 1552 // RATGPO3 RAT GPO line 3 1553 // RATGPO2 RAT GPO line 2 1554 // RATGPO1 RAT GPO line 1 1555 // RATGPO0 RAT GPO line 0 1556 // RFEGPO3 RFE GPO line 3 1557 // RFEGPO2 RFE GPO line 2 1558 // RFEGPO1 RFE GPO line 1 1559 // RFEGPO0 RFE GPO line 0 1560 // MCEGPO3 MCE GPO line 3 1561 // MCEGPO2 MCE GPO line 2 1562 // MCEGPO1 MCE GPO line 1 1563 // MCEGPO0 MCE GPO line 0 1564 // CPEGPO3 CPE GPO line 3 1565 // CPEGPO2 CPE GPO line 2 1566 // CPEGPO1 CPE GPO line 1 1567 // CPEGPO0 CPE GPO line 0 1568 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 1569 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 1570 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 1571 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 1572 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 1573 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 1574 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 1575 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 1576 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 1577 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 1578 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 1579 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 1580 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 1581 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 1582 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 1583 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 1584 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 1585 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 1586 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 1587 1588 // Field: [7:4] GPOCTL1 1589 // 1590 // RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO 1591 // line 1. 1592 // ENUMs: 1593 // RATGPO3 RAT GPO line 3 1594 // RATGPO2 RAT GPO line 2 1595 // RATGPO1 RAT GPO line 1 1596 // RATGPO0 RAT GPO line 0 1597 // RFEGPO3 RFE GPO line 3 1598 // RFEGPO2 RFE GPO line 2 1599 // RFEGPO1 RFE GPO line 1 1600 // RFEGPO0 RFE GPO line 0 1601 // MCEGPO3 MCE GPO line 3 1602 // MCEGPO2 MCE GPO line 2 1603 // MCEGPO1 MCE GPO line 1 1604 // MCEGPO0 MCE GPO line 0 1605 // CPEGPO3 CPE GPO line 3 1606 // CPEGPO2 CPE GPO line 2 1607 // CPEGPO1 CPE GPO line 1 1608 // CPEGPO0 CPE GPO line 0 1609 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 1610 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 1611 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 1612 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 1613 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 1614 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 1615 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 1616 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 1617 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 1618 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 1619 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 1620 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 1621 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 1622 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 1623 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 1624 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 1625 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 1626 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 1627 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 1628 1629 // Field: [3:0] GPOCTL0 1630 // 1631 // RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO 1632 // line 0. 1633 // ENUMs: 1634 // RATGPO3 RAT GPO line 3 1635 // RATGPO2 RAT GPO line 2 1636 // RATGPO1 RAT GPO line 1 1637 // RATGPO0 RAT GPO line 0 1638 // RFEGPO3 RFE GPO line 3 1639 // RFEGPO2 RFE GPO line 2 1640 // RFEGPO1 RFE GPO line 1 1641 // RFEGPO0 RFE GPO line 0 1642 // MCEGPO3 MCE GPO line 3 1643 // MCEGPO2 MCE GPO line 2 1644 // MCEGPO1 MCE GPO line 1 1645 // MCEGPO0 MCE GPO line 0 1646 // CPEGPO3 CPE GPO line 3 1647 // CPEGPO2 CPE GPO line 2 1648 // CPEGPO1 CPE GPO line 1 1649 // CPEGPO0 CPE GPO line 0 1650 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 1651 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F 1652 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 1653 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F 1654 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E 1655 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D 1656 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C 1657 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B 1658 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A 1659 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 1660 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 1661 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 1662 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 1663 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 1664 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 1665 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 1666 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 1667 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 1668 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 1669 1670 1671 #endif // __RFC_DBELL__ 1672