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Searched refs:RISCV_CSR_XIE (Results 1 – 3 of 3) sorted by relevance

/lk-master/arch/riscv/
A Dtime.c29 riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE); in platform_set_oneshot_timer()
35 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE); in platform_set_oneshot_timer()
63 riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE); in platform_stop_timer()
69 riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE); in riscv_timer_exception()
A Darch.c56 riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE | RISCV_CSR_XIE_TIE | RISCV_CSR_XIE_EIE); in riscv_early_init_percpu()
79 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE); in riscv_init_percpu()
83 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE); in riscv_init_percpu()
/lk-master/arch/riscv/include/arch/
A Driscv.h40 #define RISCV_CSR_XIE (0x004 | RISCV_CSR_XMODE_BITS) macro

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