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Searched refs:RISCV_CSR_XMODE_BITS (Results 1 – 1 of 1) sorted by relevance

/lk-master/arch/riscv/include/arch/
A Driscv.h29 #define RISCV_CSR_XMODE_BITS (RISCV_XMODE_OFFSET << 8) macro
39 #define RISCV_CSR_XSTATUS (0x000 | RISCV_CSR_XMODE_BITS)
40 #define RISCV_CSR_XIE (0x004 | RISCV_CSR_XMODE_BITS)
41 #define RISCV_CSR_XTVEC (0x005 | RISCV_CSR_XMODE_BITS)
42 #define RISCV_CSR_XSCRATCH (0x040 | RISCV_CSR_XMODE_BITS)
43 #define RISCV_CSR_XEPC (0x041 | RISCV_CSR_XMODE_BITS)
44 #define RISCV_CSR_XCAUSE (0x042 | RISCV_CSR_XMODE_BITS)
45 #define RISCV_CSR_XTVAL (0x043 | RISCV_CSR_XMODE_BITS)
46 #define RISCV_CSR_XIP (0x044 | RISCV_CSR_XMODE_BITS)

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