1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of SDMMC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_LL_SDMMC_H 40 #define __STM32F7xx_LL_SDMMC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_Driver 50 * @{ 51 */ 52 53 /** @addtogroup SDMMC_LL 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief SDMMC Configuration Structure definition 64 */ 65 typedef struct { 66 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 67 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 68 69 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 70 enabled or disabled. 71 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 72 73 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 74 disabled when the bus is idle. 75 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 76 77 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 78 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 79 80 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 81 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 82 83 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 84 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 85 86 } SDMMC_InitTypeDef; 87 88 89 /** 90 * @brief SDMMC Command Control structure 91 */ 92 typedef struct { 93 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 94 to a card as part of a command message. If a command 95 contains an argument, it must be loaded into this register 96 before writing the command to the command register. */ 97 98 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 99 Max_Data = 64 */ 100 101 uint32_t Response; /*!< Specifies the SDMMC response type. 102 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 103 104 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 105 enabled or disabled. 106 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 107 108 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 109 is enabled or disabled. 110 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 111 } SDMMC_CmdInitTypeDef; 112 113 114 /** 115 * @brief SDMMC Data Control structure 116 */ 117 typedef struct { 118 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 119 120 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 121 122 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 123 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 124 125 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 126 is a read or write. 127 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 128 129 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 130 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 131 132 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 133 is enabled or disabled. 134 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 135 } SDMMC_DataInitTypeDef; 136 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 143 * @{ 144 */ 145 146 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 147 * @{ 148 */ 149 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000) 150 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 151 152 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 153 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 154 /** 155 * @} 156 */ 157 158 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 159 * @{ 160 */ 161 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) 162 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 163 164 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 165 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 166 /** 167 * @} 168 */ 169 170 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 171 * @{ 172 */ 173 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) 174 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 175 176 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 177 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 178 /** 179 * @} 180 */ 181 182 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 183 * @{ 184 */ 185 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000) 186 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 187 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 188 189 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 190 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 191 ((WIDE) == SDMMC_BUS_WIDE_8B)) 192 /** 193 * @} 194 */ 195 196 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 197 * @{ 198 */ 199 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) 200 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 201 202 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 203 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 204 /** 205 * @} 206 */ 207 208 /** @defgroup SDMMC_LL_Clock_Division Clock Division 209 * @{ 210 */ 211 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) 212 /** 213 * @} 214 */ 215 216 /** @defgroup SDMMC_LL_Command_Index Command Index 217 * @{ 218 */ 219 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) 220 /** 221 * @} 222 */ 223 224 /** @defgroup SDMMC_LL_Response_Type Response Type 225 * @{ 226 */ 227 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000) 228 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 229 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 230 231 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 232 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 233 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 234 /** 235 * @} 236 */ 237 238 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 239 * @{ 240 */ 241 #define SDMMC_WAIT_NO ((uint32_t)0x00000000) 242 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 243 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 244 245 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 246 ((WAIT) == SDMMC_WAIT_IT) || \ 247 ((WAIT) == SDMMC_WAIT_PEND)) 248 /** 249 * @} 250 */ 251 252 /** @defgroup SDMMC_LL_CPSM_State CPSM State 253 * @{ 254 */ 255 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000) 256 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 257 258 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 259 ((CPSM) == SDMMC_CPSM_ENABLE)) 260 /** 261 * @} 262 */ 263 264 /** @defgroup SDMMC_LL_Response_Registers Response Register 265 * @{ 266 */ 267 #define SDMMC_RESP1 ((uint32_t)0x00000000) 268 #define SDMMC_RESP2 ((uint32_t)0x00000004) 269 #define SDMMC_RESP3 ((uint32_t)0x00000008) 270 #define SDMMC_RESP4 ((uint32_t)0x0000000C) 271 272 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 273 ((RESP) == SDMMC_RESP2) || \ 274 ((RESP) == SDMMC_RESP3) || \ 275 ((RESP) == SDMMC_RESP4)) 276 /** 277 * @} 278 */ 279 280 /** @defgroup SDMMC_LL_Data_Length Data Lenght 281 * @{ 282 */ 283 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) 284 /** 285 * @} 286 */ 287 288 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 289 * @{ 290 */ 291 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) 292 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 293 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 294 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 295 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 296 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 297 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 298 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 299 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 300 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 301 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 302 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 303 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 304 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 305 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 306 307 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 308 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 309 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 310 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 311 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 312 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 313 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 314 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 315 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 316 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 317 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 318 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 319 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 320 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 321 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 322 /** 323 * @} 324 */ 325 326 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 327 * @{ 328 */ 329 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) 330 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 331 332 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 333 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 334 /** 335 * @} 336 */ 337 338 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 339 * @{ 340 */ 341 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) 342 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 343 344 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 345 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 346 /** 347 * @} 348 */ 349 350 /** @defgroup SDMMC_LL_DPSM_State DPSM State 351 * @{ 352 */ 353 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000) 354 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 355 356 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 357 ((DPSM) == SDMMC_DPSM_ENABLE)) 358 /** 359 * @} 360 */ 361 362 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 363 * @{ 364 */ 365 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) 366 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 367 368 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 369 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 370 /** 371 * @} 372 */ 373 374 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 375 * @{ 376 */ 377 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL 378 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL 379 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT 380 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT 381 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR 382 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR 383 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND 384 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT 385 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND 386 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND 387 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT 388 #define SDMMC_IT_TXACT SDMMC_STA_TXACT 389 #define SDMMC_IT_RXACT SDMMC_STA_RXACT 390 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE 391 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF 392 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF 393 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF 394 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE 395 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE 396 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL 397 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL 398 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT 399 /** 400 * @} 401 */ 402 403 /** @defgroup SDMMC_LL_Flags Flags 404 * @{ 405 */ 406 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 407 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 408 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 409 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 410 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 411 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 412 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 413 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 414 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 415 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 416 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 417 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 418 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 419 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 420 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 421 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 422 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 423 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 424 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 425 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 426 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 427 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 428 /** 429 * @} 430 */ 431 432 /** 433 * @} 434 */ 435 436 /* Exported macro ------------------------------------------------------------*/ 437 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 438 * @{ 439 */ 440 441 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 442 * @brief SDMMC_LL registers bit address in the alias region 443 * @{ 444 */ 445 /* ---------------------- SDMMC registers bit mask --------------------------- */ 446 /* --- CLKCR Register ---*/ 447 /* CLKCR register clear mask */ 448 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 449 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 450 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 451 452 /* --- DCTRL Register ---*/ 453 /* SDMMC DCTRL Clear Mask */ 454 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 455 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 456 457 /* --- CMD Register ---*/ 458 /* CMD Register clear mask */ 459 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 460 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 461 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 462 463 /* SDMMC Initialization Frequency (400KHz max) */ 464 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) 465 466 /* SDMMC Data Transfer Frequency (25MHz max) */ 467 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) 468 469 /** 470 * @} 471 */ 472 473 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 474 * @brief macros to handle interrupts and specific clock configurations 475 * @{ 476 */ 477 478 /** 479 * @brief Enable the SDMMC device. 480 * @param __INSTANCE__: SDMMC Instance 481 * @retval None 482 */ 483 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 484 485 /** 486 * @brief Disable the SDMMC device. 487 * @param __INSTANCE__: SDMMC Instance 488 * @retval None 489 */ 490 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 491 492 /** 493 * @brief Enable the SDMMC DMA transfer. 494 * @param __INSTANCE__: SDMMC Instance 495 * @retval None 496 */ 497 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 498 /** 499 * @brief Disable the SDMMC DMA transfer. 500 * @param __INSTANCE__: SDMMC Instance 501 * @retval None 502 */ 503 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 504 505 /** 506 * @brief Enable the SDMMC device interrupt. 507 * @param __INSTANCE__ : Pointer to SDMMC register base 508 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. 509 * This parameter can be one or a combination of the following values: 510 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 511 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 512 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 513 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 514 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 515 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 516 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 517 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 518 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 519 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 520 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 521 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 522 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 523 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 524 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 525 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 526 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 527 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 528 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 529 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 530 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 531 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 532 * @retval None 533 */ 534 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 535 536 /** 537 * @brief Disable the SDMMC device interrupt. 538 * @param __INSTANCE__ : Pointer to SDMMC register base 539 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. 540 * This parameter can be one or a combination of the following values: 541 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 542 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 543 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 544 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 545 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 546 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 547 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 548 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 549 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 550 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 551 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 552 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 553 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 554 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 555 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 556 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 557 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 558 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 559 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 560 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 561 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 562 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 563 * @retval None 564 */ 565 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 566 567 /** 568 * @brief Checks whether the specified SDMMC flag is set or not. 569 * @param __INSTANCE__ : Pointer to SDMMC register base 570 * @param __FLAG__: specifies the flag to check. 571 * This parameter can be one of the following values: 572 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 573 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 574 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 575 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 576 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 577 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 578 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 579 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 580 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 581 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 582 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 583 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 584 * @arg SDMMC_FLAG_RXACT: Data receive in progress 585 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 586 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 587 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 588 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 589 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 590 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 591 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 592 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 593 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received 594 * @retval The new state of SDMMC_FLAG (SET or RESET). 595 */ 596 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) 597 598 599 /** 600 * @brief Clears the SDMMC pending flags. 601 * @param __INSTANCE__ : Pointer to SDMMC register base 602 * @param __FLAG__: specifies the flag to clear. 603 * This parameter can be one or a combination of the following values: 604 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 605 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 606 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 607 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 608 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 609 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 610 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 611 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 612 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 613 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 614 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received 615 * @retval None 616 */ 617 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 618 619 /** 620 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 621 * @param __INSTANCE__ : Pointer to SDMMC register base 622 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 623 * This parameter can be one of the following values: 624 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 625 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 626 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 627 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 628 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 629 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 630 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 631 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 632 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 633 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 634 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 635 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 636 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 637 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 638 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 639 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 640 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 641 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 642 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 643 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 644 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 645 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 646 * @retval The new state of SDMMC_IT (SET or RESET). 647 */ 648 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 649 650 /** 651 * @brief Clears the SDMMC's interrupt pending bits. 652 * @param __INSTANCE__ : Pointer to SDMMC register base 653 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 654 * This parameter can be one or a combination of the following values: 655 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 656 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 657 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 658 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 659 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 660 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 661 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 662 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 663 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt 664 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 665 * @retval None 666 */ 667 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 668 669 /** 670 * @brief Enable Start the SD I/O Read Wait operation. 671 * @param __INSTANCE__ : Pointer to SDMMC register base 672 * @retval None 673 */ 674 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 675 676 /** 677 * @brief Disable Start the SD I/O Read Wait operations. 678 * @param __INSTANCE__ : Pointer to SDMMC register base 679 * @retval None 680 */ 681 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 682 683 /** 684 * @brief Enable Start the SD I/O Read Wait operation. 685 * @param __INSTANCE__ : Pointer to SDMMC register base 686 * @retval None 687 */ 688 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 689 690 /** 691 * @brief Disable Stop the SD I/O Read Wait operations. 692 * @param __INSTANCE__ : Pointer to SDMMC register base 693 * @retval None 694 */ 695 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 696 697 /** 698 * @brief Enable the SD I/O Mode Operation. 699 * @param __INSTANCE__ : Pointer to SDMMC register base 700 * @retval None 701 */ 702 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 703 704 /** 705 * @brief Disable the SD I/O Mode Operation. 706 * @param __INSTANCE__ : Pointer to SDMMC register base 707 * @retval None 708 */ 709 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 710 711 /** 712 * @brief Enable the SD I/O Suspend command sending. 713 * @param __INSTANCE__ : Pointer to SDMMC register base 714 * @retval None 715 */ 716 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 717 718 /** 719 * @brief Disable the SD I/O Suspend command sending. 720 * @param __INSTANCE__ : Pointer to SDMMC register base 721 * @retval None 722 */ 723 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 724 725 /** 726 * @} 727 */ 728 729 /** 730 * @} 731 */ 732 733 /* Exported functions --------------------------------------------------------*/ 734 /** @addtogroup SDMMC_LL_Exported_Functions 735 * @{ 736 */ 737 738 /* Initialization/de-initialization functions **********************************/ 739 /** @addtogroup HAL_SDMMC_LL_Group1 740 * @{ 741 */ 742 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 743 /** 744 * @} 745 */ 746 747 /* I/O operation functions *****************************************************/ 748 /** @addtogroup HAL_SDMMC_LL_Group2 749 * @{ 750 */ 751 /* Blocking mode: Polling */ 752 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 753 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 754 /** 755 * @} 756 */ 757 758 /* Peripheral Control functions ************************************************/ 759 /** @addtogroup HAL_SDMMC_LL_Group3 760 * @{ 761 */ 762 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 763 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 764 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 765 766 /* Command path state machine (CPSM) management functions */ 767 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 768 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 769 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 770 771 /* Data path state machine (DPSM) management functions */ 772 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 773 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 774 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 775 776 /* SDMMC Cards mode management functions */ 777 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 778 779 /** 780 * @} 781 */ 782 783 /** 784 * @} 785 */ 786 787 /** 788 * @} 789 */ 790 791 /** 792 * @} 793 */ 794 795 #ifdef __cplusplus 796 } 797 #endif 798 799 #endif /* __STM32F7xx_LL_SDMMC_H */ 800 801 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 802