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Searched refs:SET_BIT (Results 1 – 25 of 81) sorted by relevance

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/lk-master/target/dartuinoP0/display/
A DLS013B7DH06.c28 SET_BIT(result, j); in lcd_get_line()
31 SET_BIT(result, j + 1); in lcd_get_line()
34 SET_BIT(result, j + 2); in lcd_get_line()
44 SET_BIT(result, j); in lcd_get_line()
47 SET_BIT(result, j + 1); in lcd_get_line()
50 SET_BIT(result, j + 2); in lcd_get_line()
55 SET_BIT(result, j + 3); in lcd_get_line()
58 SET_BIT(result, j + 4); in lcd_get_line()
61 SET_BIT(result, j + 5); in lcd_get_line()
70 SET_BIT(result, j); in lcd_get_line()
[all …]
/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_hal_comp.h274 SET_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \
275 SET_BIT(COMP->CSR, COMP_CSR_COMP2EN))
293 SET_BIT(COMP->CSR, COMP_CSR_COMP2LOCK))
299 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
311 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
341 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
359 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
383 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
395 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
425 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
[all …]
A Dstm32f0xx_ll_i2c.h409 SET_BIT(I2Cx->CR1, I2C_CR1_PE); in LL_I2C_Enable()
505 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); in LL_I2C_DisableAnalogFilter()
656 SET_BIT(I2Cx->CR1, I2C_CR1_SBC); in LL_I2C_EnableSlaveByteControl()
693 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); in LL_I2C_EnableWakeUpFromStop()
732 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); in LL_I2C_EnableGeneralCall()
1056 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); in LL_I2C_EnableSMBusPEC()
1266 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1299 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); in LL_I2C_EnableIT_RX()
1434 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); in LL_I2C_EnableIT_TC()
1479 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
[all …]
A Dstm32f0xx_ll_rcc.h686 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
707 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
727 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
765 SET_BIT(RCC->CR, RCC_CR_HSION); in LL_RCC_HSI_Enable()
840 SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); in LL_RCC_HSI48_Enable()
890 SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); in LL_RCC_HSI14_Enable()
984 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); in LL_RCC_LSE_Enable()
1072 SET_BIT(RCC->CSR, RCC_CSR_LSION); in LL_RCC_LSI_Enable()
1524 SET_BIT(RCC->CR, RCC_CR_PLLON); in LL_RCC_PLL_Enable()
1806 SET_BIT(RCC->CIR, RCC_CIR_CSSC); in LL_RCC_ClearFlag_HSECSS()
[all …]
A Dstm32f0xx_hal_rcc.h668 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
991 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
1017 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
1060 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1069 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
1070 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1152 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
1169 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
1245 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
1444 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
[all …]
A Dstm32f0xx_ll_usart.h575 SET_BIT(USARTx->CR1, USART_CR1_UE); in LL_USART_Enable()
616 SET_BIT(USARTx->CR1, USART_CR1_UESM); in LL_USART_EnableInStopMode()
655 SET_BIT(USARTx->CR1, USART_CR1_RE); in LL_USART_EnableDirectionRx()
677 SET_BIT(USARTx->CR1, USART_CR1_TE); in LL_USART_EnableDirectionTx()
829 SET_BIT(USARTx->CR1, USART_CR1_MME); in LL_USART_EnableMuteMode()
1432 SET_BIT(USARTx->CR3, USART_CR3_RTSE); in LL_USART_EnableRTSHWFlowCtrl()
1458 SET_BIT(USARTx->CR3, USART_CR3_CTSE); in LL_USART_EnableCTSHWFlowCtrl()
1752 SET_BIT(USARTx->CR3, USART_CR3_IREN); in LL_USART_EnableIrda()
1861 SET_BIT(USARTx->CR3, USART_CR3_NACK); in LL_USART_EnableSmartcardNACK()
2219 SET_BIT(USARTx->CR3, USART_CR3_DEM); in LL_USART_EnableDEMode()
[all …]
A Dstm32f0xx_ll_cortex.h128 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); in LL_SYSTICK_SetClkSource()
155 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); in LL_SYSTICK_EnableIT()
205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
A Dstm32f0xx_ll_bus.h246 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
348 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
434 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
588 SET_BIT(RCC->APB1RSTR, Periphs); in LL_APB1_GRP1_ForceReset()
684 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB1_GRP2_EnableClock()
796 SET_BIT(RCC->APB2RSTR, Periphs); in LL_APB1_GRP2_ForceReset()
A Dstm32f0xx_ll_tim.h1047 SET_BIT(TIMx->CR1, TIM_CR1_CEN); in LL_TIM_EnableCounter()
1091 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); in LL_TIM_DisableUpdateEvent()
1215 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); in LL_TIM_EnableARRPreload()
1418 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); in LL_TIM_CC_EnablePreload()
1518 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
2437 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); in LL_TIM_IC_EnableXORCombination()
3838 SET_BIT(TIMx->EGR, TIM_EGR_UG); in LL_TIM_GenerateEvent_UPDATE()
3849 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); in LL_TIM_GenerateEvent_CC1()
3860 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); in LL_TIM_GenerateEvent_CC2()
3904 SET_BIT(TIMx->EGR, TIM_EGR_TG); in LL_TIM_GenerateEvent_TRIG()
[all …]
A Dstm32f0xx_ll_exti.h292 SET_BIT(EXTI->IMR, ExtiLine); in LL_EXTI_EnableIT_0_31()
443 SET_BIT(EXTI->EMR, ExtiLine); in LL_EXTI_EnableEvent_0_31()
590 SET_BIT(EXTI->RTSR, ExtiLine); in LL_EXTI_EnableRisingTrig_0_31()
728 SET_BIT(EXTI->FTSR, ExtiLine); in LL_EXTI_EnableFallingTrig_0_31()
861 SET_BIT(EXTI->SWIER, ExtiLine); in LL_EXTI_GenerateSWI_0_31()
A Dstm32f0xx_ll_pwr.h230 SET_BIT(PWR->CR, PWR_CR_DBP); in LL_PWR_EnableBkUpAccess()
354 SET_BIT(PWR->CR, PWR_CR_PVDE); in LL_PWR_EnablePVD()
403 SET_BIT(PWR->CSR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
521 SET_BIT(PWR->CR, PWR_CR_CSBF); in LL_PWR_ClearFlag_SB()
531 SET_BIT(PWR->CR, PWR_CR_CWUF); in LL_PWR_ClearFlag_WU()
A Dstm32f0xx_ll_crs.h239 SET_BIT(CRS->CR, CRS_CR_CEN); in LL_CRS_EnableFreqErrorCounter()
269 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); in LL_CRS_EnableAutoTrimming()
490 SET_BIT(CRS->CR, CRS_CR_SWSYNC); in LL_CRS_GenerateEvent_SWSYNC()
650 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); in LL_CRS_EnableIT_SYNCOK()
680 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); in LL_CRS_EnableIT_SYNCWARN()
710 SET_BIT(CRS->CR, CRS_CR_ERRIE); in LL_CRS_EnableIT_ERR()
740 SET_BIT(CRS->CR, CRS_CR_ESYNCIE); in LL_CRS_EnableIT_ESYNC()
A Dstm32f0xx_hal_rcc_ex.h959 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
973 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
990 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
1007 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1120 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1139 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1189 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
1205 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
1219 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
1733 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
[all …]
/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/
A Dstm32f0xx_hal_adc.c599 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); in HAL_ADC_DeInit()
938 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); in HAL_ADC_PollForConversion()
1032 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); in HAL_ADC_PollForEvent()
1047 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); in HAL_ADC_PollForEvent()
1050 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); in HAL_ADC_PollForEvent()
1410 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); in HAL_ADC_IRQHandler()
1466 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); in HAL_ADC_IRQHandler()
1490 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); in HAL_ADC_IRQHandler()
2092 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); in ADC_DMAConvCplt()
2164 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); in ADC_DMAError()
[all …]
A Dstm32f0xx_hal_gpio.c217 … SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); in HAL_GPIO_Init()
224 SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); in HAL_GPIO_Init()
236 SET_BIT(temp, GPIO_Init->Speed << (position * 2U)); in HAL_GPIO_Init()
242 SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); in HAL_GPIO_Init()
249 SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U)); in HAL_GPIO_Init()
261 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); in HAL_GPIO_Init()
269 SET_BIT(temp, iocurrent); in HAL_GPIO_Init()
277 SET_BIT(temp, iocurrent); in HAL_GPIO_Init()
286 SET_BIT(temp, iocurrent); in HAL_GPIO_Init()
294 SET_BIT(temp, iocurrent); in HAL_GPIO_Init()
[all …]
A Dstm32f0xx_hal_spi.c661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Transmit()
841 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Receive()
910 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); in HAL_SPI_Receive()
1201 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); in HAL_SPI_TransmitReceive()
1647 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); in HAL_SPI_Transmit_DMA()
1790 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); in HAL_SPI_Receive_DMA()
1947 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
1969 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2956 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); in SPI_DMAError()
3698 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); in SPI_CloseRxTx_ISR()
[all …]
A Dstm32f0xx_hal_flash_ex.c346 SET_BIT(FLASH->CR, FLASH_CR_OPTER); in HAL_FLASHEx_OBErase()
347 SET_BIT(FLASH->CR, FLASH_CR_STRT); in HAL_FLASHEx_OBErase()
522 SET_BIT(FLASH->CR, FLASH_CR_MER); in FLASH_MassErase()
523 SET_BIT(FLASH->CR, FLASH_CR_STRT); in FLASH_MassErase()
592 SET_BIT(FLASH->CR, FLASH_CR_OPTPG); in FLASH_OB_EnableWRP()
783 SET_BIT(FLASH->CR, FLASH_CR_OPTER); in FLASH_OB_RDP_LevelConfig()
784 SET_BIT(FLASH->CR, FLASH_CR_STRT); in FLASH_OB_RDP_LevelConfig()
843 SET_BIT(FLASH->CR, FLASH_CR_OPTPG); in FLASH_OB_UserConfig()
889 SET_BIT(FLASH->CR, FLASH_CR_OPTPG); in FLASH_OB_ProgramData()
982 SET_BIT(FLASH->CR, FLASH_CR_PER); in FLASH_PageErase()
[all …]
A Dstm32f0xx_hal_can.c258 SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); in HAL_CAN_Init()
281 SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); in HAL_CAN_Init()
291 SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); in HAL_CAN_Init()
301 SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); in HAL_CAN_Init()
315 SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); in HAL_CAN_Init()
380 SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); in HAL_CAN_DeInit()
477 SET_BIT(can_ip->FMR, CAN_FMR_FINIT); in HAL_CAN_ConfigFilter()
507 SET_BIT(can_ip->FS1R, filternbrbitpos); in HAL_CAN_ConfigFilter()
529 SET_BIT(can_ip->FM1R, filternbrbitpos); in HAL_CAN_ConfigFilter()
541 SET_BIT(can_ip->FFA1R, filternbrbitpos); in HAL_CAN_ConfigFilter()
[all …]
A Dstm32f0xx_hal_smartcard.c294 SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN); in HAL_SMARTCARD_Init()
308 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); in HAL_SMARTCARD_Init()
504 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); in HAL_SMARTCARD_Transmit()
507 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); in HAL_SMARTCARD_Transmit()
643 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); in HAL_SMARTCARD_Transmit_IT()
646 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); in HAL_SMARTCARD_Transmit_IT()
652 SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); in HAL_SMARTCARD_Transmit_IT()
700 SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); in HAL_SMARTCARD_Receive_IT()
744 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); in HAL_SMARTCARD_Transmit_DMA()
747 SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); in HAL_SMARTCARD_Transmit_DMA()
[all …]
A Dstm32f0xx_hal.c357 SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); in HAL_ResumeTick()
420 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); in HAL_DBGMCU_EnableDBGStopMode()
438 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in HAL_DBGMCU_EnableDBGStandbyMode()
A Dstm32f0xx_hal_pwr.c252 SET_BIT(PWR->CSR, WakeUpPinx); in HAL_PWR_EnableWakeUpPin()
410 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
437 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_rcc_ex.h509 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
517 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
525 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
704 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
712 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
736 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
760 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
768 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
968 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
[all …]
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/
A Dstm32f7xx_hal_pwr.c134 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_EnableBkUpAccess()
320 SET_BIT(PWR->CR1, PWR_CR1_PVDE); in HAL_PWR_EnablePVD()
355 SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
542 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
566 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
A Dstm32f7xx_hal.c394 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); in HAL_DBGMCU_EnableDBGSleepMode()
412 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); in HAL_DBGMCU_EnableDBGStopMode()
430 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in HAL_DBGMCU_EnableDBGStandbyMode()
/lk-master/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_flash_ramfunc.c115 SET_BIT(PWR->CR, PWR_CR_FISSR); in FLASH_FlashInterfaceCmd()
133 SET_BIT(PWR->CR, PWR_CR_FMSSR); in FLASH_FlashSleepModeCmd()

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